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(cherry picked from commit dc8ab9d35b261b6105a62949cfb47a3554531d0b)
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(cherry picked from commit beba1dd3561e38573ed9f507328caf7f8fb9f84a)
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(cherry picked from commit da58dc3b02999f3244d0eaf77180b828d85bd609)
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(cherry picked from commit 1cfe769c74d1a3a392bf1aaaf5c2dcc8273daf66)
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Fix fd.o bug 15766
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It turns out 855 has a different DSPARB layout than 915+. And 945+ have more
FIFO entries, so we have to allocate things differently. So on 855 split the
FIFO evenly again between A & B planes, and do the same on 945, where we have a
larger FIFO. Fixes an issue reported by Daniel Stone with the previous default
value.
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Add some debug code to catch FIFO underruns, which are normally bugs (unless
they occur during mode setting) and remove any plane C FIFO allocations, since
we don't use that plane at all. We may eventually need to be a little smarter
about this on platforms that use plane C for the popup.
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Update clock gating disable bits to match docs and allocate a power context
memory area so that newer chips can save state and power down the render unit.
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This reverts commit 0c00a638ef57aa9d6a3047176b0bfad733f781f0.
Those FIFO watermark regs are 945-ish, and cause problem
on G35.
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Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
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Basic support for panel fitting.
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The GMBUS was being left in SDVO pin access mode, which blocked our bit-banging
access to those pins. Thanks to Peter Jones for quick debugging turnaround
in getting this fixed.
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MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
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For i830M stolen mem size mask should always be 0x70.
Use 0xF0 for later chipsets should be ok, so behavior is
identical to kernel agp.
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where we put MMIO control reg in, and shared with intel_reg_dump
program.
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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The backlight control in the LVDS controller can either operate in 'normal'
mode or 'legacy' mode. In legacy mode, it uses the PCI config space register
0xf4 which can range from 0 to 0xff. In normal mode, it reads the range and
current value from the BLC_PWM_CTL register.
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The 24-bit frame and pixel counters were not described in detail and
will be useful for DRM.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Chips newer than the i830 can force the border color for the active period
of the screen, allowing the load detection to easily see the right data. In
addition, newer chips appear to have more sensible load detection hardware
which either ignores inactive periods on the screen or performs some
longer-term averaging. The i830 appears to provide unfiltered samples of the
detected load.
For the i830, then, emit a border at the bottom of the screen and, for load
detection, simply turn it purple and wait for the current line to be within
the border. Sample an entire scanline, counting the number of times the load
detection sees a monitor. In my testing, the presence of a monitor will
cause the detection to succeed every time, while the absense will cause it
to fail about 75% of the time. The code here, checks for presence at least
75% of the time, which should be adequate.
Also, as the new mode configuration code has already taken care to enable
the CRT output, eliminate much of the load detection code which is simply
duplicating functionality from the general mode setting code. This should
result in faster load detection as this code will now run in no more than
one frame time. It does burn the CPU the whole time though, polling the
displayed scanline register.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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Conflicts:
src/i810_reg.h
src/i830_display.c
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- Use the existing single/dual-channel state when available, as changing it
doesn't appear to work out.
- Set the power state of the CLKB and B0-B3 pairs according to whether
choose to go dual-channel or not.
- Restore the LVDS register at the appropriate point (before DPLLs are
re-programmed.
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The LVDS register now contains lots of new controls for dual-channel LVDS control
along with dither enabling. The PFIT register has a lot fewer controls as a result.
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This should fix a number of issues with i855s, particularly with integrated
LVDS panels.
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The previous allocator worked in multiple passes, with (at least) one of
setting up allocations, another to attempt to adjust those for tiling, and
then a pass to set up the offsets and fix them in memory.
The new allocator is simpler, allocating memory immediately if possible,
setting up tiling up front, and choosing offsets immediately. AGP memory
is only allocated to back actual memory used, saving some memory that would
have been allocated for padding previous. It will also allow dynamic freeing
and reallocation of memory, which will be useful for framebuffer resizing.
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Additionally, don't attempt to set double-wide on the 965, where there is
no such thing any more (not that we'd ever see modes high enough to trigger
it).
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This includes not reporting some fields on hardware where those bits are
reserved, correcting one of the hardware error bit numbers, and reducing
the severity of the debugging output warnings.
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This extends the output funcs to have a callback for when it's time to
configure properties, and another for when the server has changed a property
whose value isn't pending a mode set. (Pending properties are to be picked up
by the driver at mode_set time).
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Outputs and Crtcs now have a driver-independent representation which should
permit generic code to control RandR 1.2 and startup configuration.
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In the past, the GTT has always been sized just large enough to map the whole
graphics aperture. However, apparently on the G965 that isn't the case, and
it is actually 512KB on hardware with a 256MB aperture. This resulted in X
not bothering to allocate memory for 256KB that it thought was already mapped
into stolen memory, and thus garbage rendering (particularly visible in large
video modes that displayed this unallocated memory). The kernel happens to
get the right answer by hardwiring a 512KB GTT size already, but that may not
be true on future hardware.
Instead, we use a convenient field in PGETBL_CTL that's specifically for the
GTT size rather than the aperture size, which gets us the answer we want.
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Place crtc/output in separate structure at head
of driver private structure. Use this from the config code
to make it driver-independent. Still lots of effectively driver
independent code that continues to use driver dependent stuff,
but that will change.
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