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Dump some of the audio registers at server startup time.
(II) intel(0): AUD_CONFIG: 0x00000004
(II) intel(0): AUD_HDMIW_STATUS: 0x00000000
(II) intel(0): AUD_CONV_CHCNT: 0x00000000
(II) intel(0): VIDEO_DIP_CTL: 0x20000600
(II) intel(0): AUD_PINW_CNTR: 0x00000040
(II) intel(0): AUD_CNTL_ST: 0x00002000
(II) intel(0): AUD_PIN_CAP: 0x00000094
(II) intel(0): AUD_PINW_CAP: 0x004073bd
(II) intel(0): AUD_PINW_UNSOLRESP: 0x80000008
(II) intel(0): AUD_OUT_DIG_CNVT: 0x00000001
(II) intel(0): AUD_OUT_CWCAP: 0x00006211
(II) intel(0): AUD_GRP_CAP: 0x00000004
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
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We detect TV connect status by setting DAC voltage level override
values as 0.7 voltage for DAC_A/B/C. The corresponding 2-bits shold be 0x2,
In order correctly to set last bit as 0, at first we must clean it.
It fixed freedesktop.org bug #21204
Signed-off-by: Ma Ling <ling.ma@intel.com>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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We use force CRT detect trigger bit(1 << 3) to detect VGA in hot plug mode,
which triggers a CRT hotplug/unplug detection cycle independent of the
interrupt enable bit(1 << 9), so keep bit 9.
And although spec says CRT_HOTPLUG_ACTIVATION_PERIOD_64(1 << 8) is only useful
for mobile platform, it is also required to detect vga on G4x platform correctly.
Tested the patch on G45/G43/Q45 platforms with no regressions
It fixed freedesktop.org bug #21120 and part of bug #21210.
Signed-off-by: Ma Ling <ling.ma@intel.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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CVS keywords, comments about how the source was once reformatted,
and the ad-hoc changelog comment in in i830_driver.c
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Almost all digital TVs accept broadcast RGB values from 16 to 235 for each channel,
otherwise for those uncompensated videos, when RGB values are set from 0 to 255,
they will shows black and whiter clamping, which seriously degrades picture quality.
The patch will enable the broadcast RGB mode for hdtv according to user's setting.
It fixed bug #14486
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Since the change to scan-line based video sync, (rather than vblank-
based), we've only been getting tear-free video on one of the two
pipes. This fixes that bug by using the correct constant for waiting
on PIPEA.
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Either way, the goal is tear-free video playing. But waiting for
a scan-line window not only has the advantage of being cheaper
for small windows, but also avoids hanging the GPU in the case
of the pipe getting turned off, (by screensaver, for example),
while a batch is waiting for a VBLANK that will never occur.
This fixes that GPU hang.
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Add an Xv attribute XV_SYNC_TO_VBLANK which has three values -1(auto), 0(off)
and 1(on) to control whether textured adapter synchronizes the screen
update to the vblank. The default value is -1(auto).
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Enable audio output for the integrated HDMI of Intel G45 chipset
by introducing the SDVO_AUDIO_ENABLE bit.
Signed-off-by: Wu Fengguang <wfg@linux.intel.com>
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The GM45 b-spec requires the use of the longer hotplug activation period,
but does not require looping twice over the detection logic. With this
patch, CRT detection appears solid on my GM45.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Driver should keep those fields according with spec.
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Render standby is known to cause possible hang issue on some
mobile chips, so always disable it.
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Conflicts:
configure.ac
src/reg_dumper/Makefile.am
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The batchbuffers are managed using libdrm and bufmgr_fake, and dispatched from
the ring from userland.
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Fix fd.o bug 15766
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It turns out 855 has a different DSPARB layout than 915+. And 945+ have more
FIFO entries, so we have to allocate things differently. So on 855 split the
FIFO evenly again between A & B planes, and do the same on 945, where we have a
larger FIFO. Fixes an issue reported by Daniel Stone with the previous default
value.
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Add some debug code to catch FIFO underruns, which are normally bugs (unless
they occur during mode setting) and remove any plane C FIFO allocations, since
we don't use that plane at all. We may eventually need to be a little smarter
about this on platforms that use plane C for the popup.
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Update clock gating disable bits to match docs and allocate a power context
memory area so that newer chips can save state and power down the render unit.
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This reverts commit 0c00a638ef57aa9d6a3047176b0bfad733f781f0.
Those FIFO watermark regs are 945-ish, and cause problem
on G35.
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Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
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Basic support for panel fitting.
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The GMBUS was being left in SDVO pin access mode, which blocked our bit-banging
access to those pins. Thanks to Peter Jones for quick debugging turnaround
in getting this fixed.
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MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
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For i830M stolen mem size mask should always be 0x70.
Use 0xF0 for later chipsets should be ok, so behavior is
identical to kernel agp.
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where we put MMIO control reg in, and shared with intel_reg_dump
program.
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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