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Almost all digital TVs accept broadcast RGB values from 16 to 235 for each channel,
otherwise for those uncompensated videos, when RGB values are set from 0 to 255,
they will shows black and whiter clamping, which seriously degrades picture quality.
The patch will enable the broadcast RGB mode for hdtv according to user's setting.
It fixed bug #14486
(cherry picked from commit 69388953ce889080d5f014123d89bf3eb45f3d8d)
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Since the change to scan-line based video sync, (rather than vblank-
based), we've only been getting tear-free video on one of the two
pipes. This fixes that bug by using the correct constant for waiting
on PIPEA.
(cherry picked from commit 0a0731c11d10392cdc55ecc04e4e3575c8b3fe57)
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Either way, the goal is tear-free video playing. But waiting for
a scan-line window not only has the advantage of being cheaper
for small windows, but also avoids hanging the GPU in the case
of the pipe getting turned off, (by screensaver, for example),
while a batch is waiting for a VBLANK that will never occur.
This fixes that GPU hang.
(cherry picked from commit bc3312fd7c03d09a231dfebfe390fe668ad15d1e)
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Add an Xv attribute XV_SYNC_TO_VBLANK which has three values -1(auto), 0(off)
and 1(on) to control whether textured adapter synchronizes the screen
update to the vblank. The default value is -1(auto).
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Enable audio output for the integrated HDMI of Intel G45 chipset
by introducing the SDVO_AUDIO_ENABLE bit.
Signed-off-by: Wu Fengguang <wfg@linux.intel.com>
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The GM45 b-spec requires the use of the longer hotplug activation period,
but does not require looping twice over the detection logic. With this
patch, CRT detection appears solid on my GM45.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Driver should keep those fields according with spec.
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Render standby is known to cause possible hang issue on some
mobile chips, so always disable it.
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Conflicts:
configure.ac
src/reg_dumper/Makefile.am
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The batchbuffers are managed using libdrm and bufmgr_fake, and dispatched from
the ring from userland.
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Fix fd.o bug 15766
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It turns out 855 has a different DSPARB layout than 915+. And 945+ have more
FIFO entries, so we have to allocate things differently. So on 855 split the
FIFO evenly again between A & B planes, and do the same on 945, where we have a
larger FIFO. Fixes an issue reported by Daniel Stone with the previous default
value.
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Add some debug code to catch FIFO underruns, which are normally bugs (unless
they occur during mode setting) and remove any plane C FIFO allocations, since
we don't use that plane at all. We may eventually need to be a little smarter
about this on platforms that use plane C for the popup.
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Update clock gating disable bits to match docs and allocate a power context
memory area so that newer chips can save state and power down the render unit.
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This reverts commit 0c00a638ef57aa9d6a3047176b0bfad733f781f0.
Those FIFO watermark regs are 945-ish, and cause problem
on G35.
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Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
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Basic support for panel fitting.
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The GMBUS was being left in SDVO pin access mode, which blocked our bit-banging
access to those pins. Thanks to Peter Jones for quick debugging turnaround
in getting this fixed.
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MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
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For i830M stolen mem size mask should always be 0x70.
Use 0xF0 for later chipsets should be ok, so behavior is
identical to kernel agp.
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where we put MMIO control reg in, and shared with intel_reg_dump
program.
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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The backlight control in the LVDS controller can either operate in 'normal'
mode or 'legacy' mode. In legacy mode, it uses the PCI config space register
0xf4 which can range from 0 to 0xff. In normal mode, it reads the range and
current value from the BLC_PWM_CTL register.
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The 24-bit frame and pixel counters were not described in detail and
will be useful for DRM.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Chips newer than the i830 can force the border color for the active period
of the screen, allowing the load detection to easily see the right data. In
addition, newer chips appear to have more sensible load detection hardware
which either ignores inactive periods on the screen or performs some
longer-term averaging. The i830 appears to provide unfiltered samples of the
detected load.
For the i830, then, emit a border at the bottom of the screen and, for load
detection, simply turn it purple and wait for the current line to be within
the border. Sample an entire scanline, counting the number of times the load
detection sees a monitor. In my testing, the presence of a monitor will
cause the detection to succeed every time, while the absense will cause it
to fail about 75% of the time. The code here, checks for presence at least
75% of the time, which should be adequate.
Also, as the new mode configuration code has already taken care to enable
the CRT output, eliminate much of the load detection code which is simply
duplicating functionality from the general mode setting code. This should
result in faster load detection as this code will now run in no more than
one frame time. It does burn the CPU the whole time though, polling the
displayed scanline register.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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