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- allow FBC and Tiling to be forced off if configured to do so
- only touch FBC registers if pI830->fb_compression is true
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- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
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- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
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"true" in your xorg.conf). Should save ~0.5W during typical 2D usage.
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Move clone/crtc config into each output where it's easier to understand (no
need for a switch statement in I830PrepareOutputs. Also, split DVO into
three sub-types (TMDS, LVDS, TVOUT) as those have different cloning
abilities.
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Chips newer than the i830 can force the border color for the active period
of the screen, allowing the load detection to easily see the right data. In
addition, newer chips appear to have more sensible load detection hardware
which either ignores inactive periods on the screen or performs some
longer-term averaging. The i830 appears to provide unfiltered samples of the
detected load.
For the i830, then, emit a border at the bottom of the screen and, for load
detection, simply turn it purple and wait for the current line to be within
the border. Sample an entire scanline, counting the number of times the load
detection sees a monitor. In my testing, the presence of a monitor will
cause the detection to succeed every time, while the absense will cause it
to fail about 75% of the time. The code here, checks for presence at least
75% of the time, which should be adequate.
Also, as the new mode configuration code has already taken care to enable
the CRT output, eliminate much of the load detection code which is simply
duplicating functionality from the general mode setting code. This should
result in faster load detection as this code will now run in no more than
one frame time. It does burn the CPU the whole time though, polling the
displayed scanline register.
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Reported by: Haihao Xiang <haihao.xiang@intel.com>
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This disables all outputs on EnterVT as the SDVO output can confuse
the VGA output if the BIOS has enabled it on the same pipe but X
isn't going to use the SDVO.
Worked out on irc with keithp
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It had been necessary to allow more than a small amount of memory to be
allocated, but now those old small allocations people had configured are
getting in the way.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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With the fixes to the 2D frame buffer allocation that allows up to 65536
lines of 2D frame buffer in XAA mode, the old linear allocation hacks are no
longer necessary.
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A closing brace was left inside #ifdef XF86DRI_MM while the matching
open brace was outside.
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Reported by JM Ibanez
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crestline
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last_3d set to LAST_3D_OTHER indicates that the 3D hardware has unknown
state.
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AdjustFrame is strictly for legacy compatibility; calling it on EnterVT
wrecks crtc positions.
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Conflicts:
src/i810_reg.h
src/i830_display.c
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- Use the existing single/dual-channel state when available, as changing it
doesn't appear to work out.
- Set the power state of the CLKB and B0-B3 pairs according to whether
choose to go dual-channel or not.
- Restore the LVDS register at the appropriate point (before DPLLs are
re-programmed.
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git://proxy.ims.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline
Conflicts:
src/i830_display.c
Change LVDS output and postread like upstream. This might
need to be retested on 965GM LVDS.
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Misplaced brace broke builds with older DRM libraries.
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This eliminates all of the cursor rotation code and other cursor management
infrastructure, leaving a fairly simple hardware layer in its place.
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Conflicts:
src/i830_dri.c
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With the new mode setting code, rotation is handled outside of the driver,
so the old usage of the 'shadow' module is no longer needed. Code to
initialize the crtc structures has been moved out of the driver and into the
modes code.
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This is a partial revert of 7358642e64ab6d13bc1dc1a44703ee66d715ff61
If we don't allocate it now, when the DRM version is too low there won't be any
memory allocated and DRI will fail. Instead, waste the memory in the i915tex
case for now, and leave fixing it right (check DRM version up front and decide
which memory manager to set up) to later.
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pI830->mmSize is in kB.
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Conflicts:
src/i830_display.c
src/i830_driver.c
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Make the application of crtc desiredModes generic code instead of
per-driver by creating xf86SetDesiredModes from the code that was in EnterVT
and calling it.
Also, move the frame buffer clear until just before mode setting to make
sure things are mapped correctly.
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Conflicts:
src/i830.h
src/i830_dri.c
src/i830_dri.h
src/i830_driver.c
src/i830_memory.c
src/i830_xaa.c
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It takes the offset and size in pages, not bytes.
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Only one of them can be active.
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Conflicts:
configure.ac
src/i830_driver.c
src/i830_modes.c
src/i830_video.c
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