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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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DDX will check it for EXA_OFFSCREEN_PIXMAPS flag
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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Reported by JM Ibanez.
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This slipped in as a debugging aid, and never got turned off. The driver
appears to work fine without it on an i915 system, and for the non-default EXA
option, we'd rather see issues found than continue running with debugging aids
and hiding them behind bad performance.
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This allows setting the size to 0 when a pipe gets disabled.
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The previous allocator worked in multiple passes, with (at least) one of
setting up allocations, another to attempt to adjust those for tiling, and
then a pass to set up the offsets and fix them in memory.
The new allocator is simpler, allocating memory immediately if possible,
setting up tiling up front, and choosing offsets immediately. AGP memory
is only allocated to back actual memory used, saving some memory that would
have been allocated for padding previous. It will also allow dynamic freeing
and reallocation of memory, which will be useful for framebuffer resizing.
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This seems like a typo, which causes screen artifacts.
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The now-generic (kind of) EXA code will be cleaned up and moved to generic
files in a later commit.
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Previously, we tried to use 2 points instead of 3 to describe the source
rectangles, which mostly just worked for scaling.
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For EXA, this requires version 2.1 of EXA to do rotation, as the VT switching
issues were too complicated otherwise.
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A side effect is the reduction in vertex dispatch, which is nice.
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This reduces max framebuffer width and increases max framebuffer height on
965, reduces max X/Y on pre-965 EXA (could have caused mis-rendering), and
increases max X/Y on 965 EXA (would have prevented acceleration).
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Several new global functions were not put into the header file leading to
potential mismatches between declaration and definition.
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I830EntityIndex is shared between 810 and newer driver.
Move most EXA rendering state into I830 structure.
Declare shared variables in shared header files rather than .c.
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Not split offscreen mem for exa, but alloc a dedicated one
for G965 states.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
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NULL vs. 0
make some variables static
remove redundant variables
There are only a few sparse warnings left now: some bitfield warnings
and a few 'mixing code and declarations' warnings from the ring macros.
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This does not include ps program, which will be added
in g4a form.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
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Autodetect libdrm version, disable new memory manager on older libraries.
Move new M_T_ defines from i830.h to i830_xf86Crtc.h. Add many system
headers to define functions. Use i830PipeSetBase at end of mode setting
code to set DSP*BASE and flush changes. Don't duplicate PipeSetBase call
from screen init function. Make initial RandR configuration code usable on
older versions of extension so the server doesn't start in a panning mode.
Use xfree instead of free in i830_tv.c.
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This replaces other debug sync options sprinkled around the EXA code. It
doesn't change the mis-rendering of text on the 915.
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The I830Sync version has additional code for the 965.
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Replace COLOR_BLT_CMD with XY_COLOR_BLT_CMD, by which
device would care for direction and provide a (x,y) coord
interface. This fixes pixmap artifacts even in no composite
case.
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Conflicts:
src/i915_exa_render.c
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efficent way and implement blit correctly.
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This reverts commit 433cb6ba82698676f6f72e09834aba4d64611d54.
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Issue texture coord set with proper scale value.
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