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This doesn't help with the most common use-while-unbound cases, which are
from the hardware side.
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This allows us to allocate tiled buffers in buffer objects. In the process
I removed the fence division that we had for tiled buffers on pre-965. If we
resurrect that code, it should probably be managed by just dividing all the
objects in roughly half and fencing those halves (to reduce the alignment
requirement), instead of using giant fences until we run out of space and then
trying to deal with scarce space on the last (or not) buffer. Halving
our tiled objects would use 6/8 of our fence registers on that hardware.
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We can't guarantee the offset will stay the same using the current DRM
interface, but the correct solution is fixing our code to allow these objects
to move. Breaks TTM mode of the DRI driver for now.
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The current offset is used every time in render setup.
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And cursor mem counting for dri mem manager is not relate
to overlay.
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Conflicts:
src/i830.h
src/i830_driver.c
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This requires EXA 2.2 (server 1.3) for rotated performance with EXA, because
the i830_memory.c allocation may not fall within what EXA considers the
offscreen area, so the PixmapIsOffscreen hook is needed.
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This should fix issues with XV being allocated into XAA's tiled pixmap
cache and resulting bad rendering. Its also brings us closer to being able
to shrink the size of the pixmap cache on XAA, which is of limited utility.
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Conflicts:
src/i830_dri.c
src/i830_memory.c
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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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Remove an extra "FBC enabled" message from i830_memory.c (only report errors
if they occur), and don't print the "forcing FBC on" message if tiling was
already enabled, as it's redundant and confusing.
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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A number of other interfaces of ours don't allow buffer offsets to be updated
after screeninit. This attempts to catalog why for each one, so that they
can be fixed one by one.
This happens to restore the EXA offscreen allocator for now, as a fixed-offset
object.
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To do this, we have to deal with buffer offsets being set at EnterVT time
instead of screen init time. We've wanted to move this direction for a long
time, but there are repercussions. The EXA offscreen memory manager has to
be disabled, because it can't be moved. That will be replaced by BO-backed
pixmaps soon. Also unresolved is whether our moving
front/back/depth/texture buffers will break the classic-mode DRI driver.
This code doesn't actually work yet.
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This is a step towards being able to expose buffer objects through the screen
private to DRI clients, instead of having them have to use the fake buffer
object type.
This fails in two ways. First, the kernel memory manager is not currently
suitable for doing the physical allocations we need, so we still use AGP for
those. Additionally, the DRI lock can't be initialized early enough for us, so
these buffer object allocations fail. This will be fixed by improving the
DRM interface.
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The upper bits would have been inappropriately dropped on G33-class hardware,
and on G965-class hardware in a 32-bit environment. The only use of physical
addresses on these should be for FBC, though, and FBC requires addresses
below 4GB. This is unresolved.
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- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
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pitch.
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- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
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"true" in your xorg.conf). Should save ~0.5W during typical 2D usage.
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Be sure to check G33 chip type in:
- sdvo output
- Y-major tile
- crt detect
- and xaa composite
Sorry for that I should have fixed them very earlier...
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Which have to use gfx vm offset fot setup overlay regs.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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965G needs state mem buffer to setup render pipeline.
Thanks Barry Scrott for report this.
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With the fixes to the 2D frame buffer allocation that allows up to 65536
lines of 2D frame buffer in XAA mode, the old linear allocation hacks are no
longer necessary.
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We should alloc xaa_linear mem in LinearAlloc case, otherwise
we get crash when initializing xf86 fb manager.
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