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2D pitch limit applys to all chips. Pre-965 chip has
8KB pitch limit for 3D. 965 supports max pitch by current
exa (128KB).
(cherry picked from commit 8187a5a16f8bd8f0ba5e7f5357f355928b3b8f07)
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The homogeneous coordinate computation in the core server cannot be used for
many legal matrices as it overflows. Just use floats in the driver; faster
and avoids troubles.
When compositing with bilinear filter, don't push the dst coordinates around
as that makes the output blurry when pixels are aligned.
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Projective transforms require un-normalized texture coordinates and the use
of the texldp instruction. The coordinates are passed as x/y/z/w (the z is
unused, but there isn't a vertext format for just x/y/w).
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Move some declarations and don't declare an extra variable with the
same name, to fix warnings about mixed declarations and code.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Whoa, gcc got a lot smarter about warnings. If iXXX_get_dest_format()
doesn't support the picture format passed in it won't initialize the
uint32_t pointed to by dst_format and return FALSE.
What gcc now can detect is if dst_format is used without checking the
return value, it might be used uninitialized. This patch makes sure
we always check the return value before using dst_format.
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From spec, i915 engine uses green channel when reading from 8bit
color buffer for blending, and also writes back green channel.
Fix blend factor in dest alpha case by using dest color instead.
Now rendercheck can pass a8 tests.
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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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Fence setting is in mapstate actually. This fixes rotation in
tiled fb case, thanks Keith to report this.
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Make it to check fence register for dest buffer.
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- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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