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The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen6_upload_invariant_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Sandybdrige requires an elaborate dance to flush caches without
hanging the gpu. See public docs Vol2Part1 1.7.4.1 PIPE_CONTROL
or the corrensponding code in mesa/kernel.
This (together with the corresponding patch for the kernel) seems to
fix the hangs in cairo-perf-traces I'm seeing on my snb machine.
v2: Incorporate review from Chris Wilson. For paranoia keep all three
PIPE_CONTROL cmds in the same batchbuffer to avoid upsetting the gpu.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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I mistakenly set GEN7_PS_MAX_THREAD_SHIFT to 23; it's actually 24 on
Ivybridge. Not only did this halve our thread count, it caused us to
write 1 into a bit 23, which is marked as MBZ (must be zero).
Furthermore, it made us write an even number into this field, which is
apparently not allowed. Apparently we were just lucky it worked.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The configuration is same as that on Sandybridge, but
many state commands are changed
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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The driver is still built but is no longer under active development so
move it and supporting files to a new directory.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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