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path: root/src/intel_batchbuffer.c
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2013-01-30uxa: Harden against failures to submit batchbuffersChris Wilson
If we fail to submit a batchbuffer, the driver is broken and likely to continue to fail to render. Give up, and fallback to swrast so that the session remains usable. References: https://bugs.freedesktop.org/show_bug.cgi?id=59771 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-01-11intel: Throttle harderChris Wilson
Filling the rings is a very unpleasant user experience, so cap the number of batches we allow to be inflight at any one time. Interestingly, as also found with SNA, throttling can improve performance by reducing RSS. However, typically throughput is improved (at the expense of latency) by oversubscribing work to the GPU and a 10-20% slowdown is commonplace for cairo-traces. Notably, x11perf is less affected and in particular application level benchmarks show no change. Note that this exposes another bug in libdrm-intel 2.4.40 on gen2/3. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-11-30Convert generation counter to octalChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-05-23intel: convert to new screen conversion APIsDave Airlie
The compat header takes care of the old server vs new server. this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-15uxa: Simplify flush trackingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-03-15uxa: Kill the complicated in-flight trackingChris Wilson
Reference leak hunting. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-11-16Compile out UXA if so desiredChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-10-11snb: implement PIPE_CONTROL workaroundDaniel Vetter
Sandybdrige requires an elaborate dance to flush caches without hanging the gpu. See public docs Vol2Part1 1.7.4.1 PIPE_CONTROL or the corrensponding code in mesa/kernel. This (together with the corresponding patch for the kernel) seems to fix the hangs in cairo-perf-traces I'm seeing on my snb machine. v2: Incorporate review from Chris Wilson. For paranoia keep all three PIPE_CONTROL cmds in the same batchbuffer to avoid upsetting the gpu. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-05-09Add support for Ivybridge chipset.Eric Anholt
This gets display and 2D blit acceleration up and running. No Render acceleration is provided yet.
2011-05-07Ensure that the partial batch is flushed upon the blockhandlerChris Wilson
Currently, we require that a batch containing a dirty bo be submitted before we mark the device as requiring a flush. So if we never submit a batch between block handlers, we can end up sleeping without ever flushing either the partial batch or the rendering to the scanout. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36776 Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-08intel: Restore manual flush for old kernelsChris Wilson
Daniel Vetter pointed out that the automagic flush by the kernel for the busy-ioctl was only introduced upstream in 2.6.37. So we still need to manually emit a flush on old kernels. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-08Tell users to grab i915_error_state on gpu hangsDaniel Vetter
Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-04-07gen6: Invalidate texture cacheChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04Take advantage of the kernel flush for dirty bo in the busy ioctlChris Wilson
Rather than just creating and submitting a batch that simply contains a flush in order to periodically ensure that rendering reaches the scanout, we can simply ask the kernel whether the scanout is busy. The kernel will then submit a flush on our behalf if it is dirty, which takes advantage of the kernel's dirty state tracking. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04i965: segregate each vertex element into its own bufferChris Wilson
Reduce the number of relocations emitted by only emitting one relocation per vertex element per vertex buffer. References: https://bugs.freedesktop.org/show_bug.cgi?id=35733 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03Wait on the current buffer to complete when running synchronously.Chris Wilson
And remove the vestigal wait upon changing crtc as this is more properly done in the kernel. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03i965: Amalgamate surface binding tablesChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03i965: Upload an entire vbo in a single pwrite, rather than per-rectangleChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-05Wait for any pending rendering before switching modes.Chris Wilson
A perennial problem we have is the accursed WAIT_FOR_EVENT hangs, which occur when we switch the framebuffer before the WAIT_FOR_EVENT completes and upsets the GPU. We have tried more subtle approaches to detected these and fix them up in the kernel, to no avail. What we need to do is to delay the framebuffer flip until the WAIT completes, which is quite tricky in the kernel without new ioctls and round-trips. Instead, apply the big hammer from userspace and synchronise all rendering before changing the framebuffer. I expect this not to cause noticeable latency on switching modes (far less than the actual modeswitch) and should stop these hangs once and for all. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31401 (...) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01add BLT ring supportZou Nan hai
gen6+ platform has a BLT engine with seperate command streamer to support BLT commands. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: merge trivial conflict] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01Xv: setup pipeline for Xv on SandybridgeXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-10-07Include a chipset generation number to clarify device specific paths.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-25Rename common infrastructure to the intel namespace.Chris Wilson
After splitting out the i810 driver into its own legacy directory, we can identify the common routines not as i830 but as intel. This clarifies the code which *is* i830 specific. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>