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2014-08-05intel: Use NOACCEL to avoid a symbol clash on old XorgChris Wilson
Old Xorg xf86str.h defines NONE preventing us from using it within an enum. Use NOACCEL instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-07-27configure: Expose no acceleration by default (--with-default-accel=none)Chris Wilson
Why? I am not sure, but it seems equally as valid as allowing the switch to uxa/glamor as default. The runtime equivalent is Option "AccelMethod". Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-07-23sna: Disable rendering with the DRM device whilst away from VTChris Wilson
As root, X gets away with many things, including submitting commands to the DRM device whilst it is no longer authorised (i.e. when it has relinquished master to another client across a VT switch). In the non-root future, if we attempt to use the device whilst unauthorized the rendering will be lost and we will mark the device as unusable. So flush our render queue to the device around a VT switch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-06-06sna: Report KMS driver versionChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-06-02intel: Add common routines and configure probing for DRI3Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-03-18uxa: Add support for server managed fds (via intel_device)Chris Wilson
Based on the patch by Hans de Goede, this removes the handling of drmOpen() and DRM_MASTER from within uxa and instead uses the common routines. This reduces the duplicate code from within uxa, and enables new features such as server managed fds. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-03intel: Handle fallback probing without match_dataChris Wilson
One extreme fallback path through the xf86PlatformProbe results in a call without any match data. As we have a device by this point, we can simply do a reverse match. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-03intel: Remove dependence upon having PciInfoChris Wilson
After some probing mechanisms, we may end up with a valid device without knowing its PCI address a priori. Having a valid device, we can just query it for the correct device id, and can safely abort any path that requires PCI information that we don't have. (Those paths are not valid under such hosting anyway - if it may be required, we could reconstruct the address.) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-02intel: Pass the platform device along to the open routinesChris Wilson
This allows us to pass along more metadata along with the platform device in future. Currently we pass the device path, but in a hosted environment we should be passing along the authorized fd from the host. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-09-07Revert "sna: Add XMir support"Chris Wilson
This reverts commit 42d94356f65972eb7fb8991234a4e9388c4c2031. Ordered-by: The Management.
2013-09-04sna: Add XMir supportChris Wilson
With lots of updates by Christopher James Halse Rogers as he updated the XMir API - but now supposedly frozen! "<RAOF> ickle: I think the xmir api should be pretty much stable now, barring people coming up with more awesome ways of doing things." Signed-off-by: Christopher James Halse Rogers <raof@ubuntu.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-08-23intel: Add experimental rendernode supportChris Wilson
Render nodes allow clients full access to off-screen rendering and GPU offload, without assuming any master responsiblities (for device and display management). As they have a more limited interface, they can be used in a more permissive manner. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-08-09intel: Disable incompatible features whilst hostedChris Wilson
Start adding the infrastructure to disable direct hardware access if X is being run under a system compositor (aka "hosted"). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Remove the unused SDV PCI IDsChris Wilson
As a first step towards working out what to do with the remaining used-once PCI IDs, delete the used-never ones. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Remove the unused bridge PCI-IDsChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Always define the PCI-IDsChris Wilson
If the macros conflict with another definition on the system, that is actually a useful warning in this case as it means there exists a typo somewhere. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Remove some unused macrosChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Move some backend specific macros out of the common headerChris Wilson
All the IS_GEN/IS_DEVICE are only used by the UXA backend, so move them to its headers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-30sna: Store the path used to open the device and pass to DRIChris Wilson
Avoid having to search the device tree once again in order to simply recover the path we used to open the device. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-23sna: Only open the /dev/dri/cardX device onceChris Wilson
Merge the device open in the main driver with the probing so that we can open the path explicitly passed in by the PlatformProbe and keep that fd around for the main driver and so avoid a later search. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-05-14Adding more reserved PCI IDs for Haswell.Rodrigo Vivi
As Chris mentioned there is a tendency for us to find out more PCI IDs only when users report. So let's add all new reserved Haswell IDs. I didn't have better names for this reserved ids and didn't want to use rsvd1 and rsvd2 groups, so I decided to use "B" and "E" that stands for the last id digit. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2013-05-14Fix Haswell GT3 names.Rodrigo Vivi
When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2013-04-27Add all reserved PCI-IDs for HaswellChris Wilson
There is a tendency for a product to ship based on a 'reserved' PCI-ID prior to us being notified about it. In other words, the first we find out about such a product is when customers start complaining about their shiny new hardware not being supported... References: https://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-03-01Fix Haswell CRW PCI-IDsChris Wilson
As we missed the PCI-ID for the CRW GT1 variant, we would not have enabled render support for those particular Haswell machines. Reported-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-05intel: add more ValleyView PCI IDsChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-11-30Convert generation counter to octalChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-09-14Add basic support for ValleyViewChris Wilson
Bind to the ValleyView SDV for verifying the render routines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-07Add Haswell PCI IDsPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03Pass the chipset info through driverPrivate rather than a global pointerChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03Unexport intel_chipsetsChris Wilson
Only used by the core module code, so make it static. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03uxa: add IS_HSW() macro to distinguish Haswell from IvybridgeGwenole Beauchesne
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-07-23intel: Refactor the common chipset detection/overrideChris Wilson
Reduce the duplicate messages for which type of chip we by amalgamating the common code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-05-24Unify options handling between UXA and SNAEugeni Dodonov
Unifies available options for both UXA and SNA drivers, and moves them into a common header file, intel_opts.h. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-30Add support for Ivy Bridge GT2 Server chipsetEugeni Dodonov
Sometimes known as Bromlow. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-18Silence uxa-only compilationChris Wilson
Kill the stray warning for the undeclared extern used by the module loader. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-09Add support for Ivybridge chipset.Eric Anholt
This gets display and 2D blit acceleration up and running. No Render acceleration is provided yet.
2011-03-09Give each user of tiling separate xorg.conf optionsChris Wilson
So that you can indeed allocate a linear framebuffer if you so desire without breaking mesa. Adds: Section "Driver" Option "LinearFramebuffer" "False|True" # default false EndSection to xorg.conf Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-17Fix IGD and IGDNG constants to be comprehensibleAdam Jackson
Since, with GPU-on-package, it's hard to talk about a model number for a specific chipset like 855GM, just use the platform names. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-07Include a chipset generation number to clarify device specific paths.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-30Always use tiling on SandybridgeZhenyu Wang
Sandybridge requires kind of buffer must be tiling, like depth. And we would or have all tiling cases handled fine. So not allow user to turn off tiling on Sandybridge+ may be fine. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-09-16Add alternate pci-id for B43Chris Wilson
Confirmed by http://en.wikipedia.org/wiki/Intel_GMA Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30221 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07Add more sandybridge graphics device idsZhenyu Wang
New ids for GT2 and GT2+ on desktop and mobile sandybridge, and server sandybridge device ids.
2010-08-23Add sandybridge D0 supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-07-09Add support for I854.Chris Wilson
I spotted that the kernel knew of the I854, but the pci-id was never added to the ddx. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-25i810: Move into a legacy directory.Chris Wilson
The driver is still built but is no longer under active development so move it and supporting files to a new directory. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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