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path: root/src/intel_uxa.c
AgeCommit message (Expand)Author
2011-05-29Cleanup gen2 tiling confusionDaniel Vetter
2011-05-29Fix relaxed tiling on gen2Daniel Vetter
2011-05-29i830: amalgamate consecutive composites into a single primitiveChris Wilson
2011-04-04don't do batch_submits in uxa block handler if vtswitchedOwain G. Ainsworth
2011-03-16i965: Amalgamate surface binding tablesChris Wilson
2011-03-16uxa: Relax fencing some more for gen3Chris Wilson
2011-03-16Support BLT acceleration on gen6Owain G. Ainsworth
2011-03-16Update priv->stride after bo reallocationChris Wilson
2011-03-16Create the UXA generational resources during screen createOwain G. Ainsworth
2011-03-16Don't replace the scanout bo through PutImageChris Wilson
2011-03-16Revert "i965: Invalidate pixmap binding location on reuse."Owain G. Ainsworth
2011-03-16i965: Invalidate pixmap binding location on reuse.Chris Wilson
2011-03-16Always flush the batch before blocking for new X requestsChris Wilson
2011-03-16uxa: Prevent reading past the last byte on upload/downloadChris Wilson
2011-03-16i965: Upload an entire vbo in a single pwrite, rather than per-rectangleChris Wilson
2011-03-16Fix violation of gen6 requirements for depthbuffer tiling.Eric Anholt
2011-03-16Include a chipset generation number to clarify device specific paths.Owain G. Ainsworth
2011-03-16uxa: Re-enable acceleration.Chris Wilson
2011-03-16Revert "Clear pixmap->devPrivate.ptr [regression in 7c7294e]"Chris Wilson
2011-03-16Clear pixmap->devPrivate.ptr [regression from 7c7294e]Chris Wilson
2011-03-16shadow+dri2: Allow dri2 to be independently enabled with shadowOwain G. Ainsworth
2011-03-16Split shadow handling routines to their own file.Chris Wilson
2010-09-13uxa: Apply source clipping to blitsChris Wilson
2010-09-12Enable a shadow buffer and disable GPU acceleration.Chris Wilson
2010-09-12Force use of GTT and fence registers for mapping tiled objectsChris Wilson
2010-09-12Remove accel_pitch_alignmentChris Wilson
2010-09-12Replace ROUND_* macros with ALIGN.Matt Turner
2010-09-12Rename common infrastructure to the intel namespace.Owain G. Ainsworth