| Age | Commit message (Collapse) | Author |
|---|
|
It is to prepare for Xv on Ivybridge. The difference from Sandybridge
is that all message payload must be in GRF registers instead of MRF registers
on Ivybridge. We will only redefine some M4 macros for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
It is weird that some rendercheck cases only work fine with headerless write.
Need to update intel-gen4asm to support headerless write
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
To prepare for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
Need to update intel-gen4asm to build these fragments
Signed--off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
The two fragments will be reused for sampling YUV surface
and send doesn't have implied move on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
We only set up one sampler, because all of our sampling is the same. By
using a non-zero index for the other two samplers, we'd dereference (likely)
zeroed data, resulting in using NEAREST filtering. This was a regression in
40671132cb3732728703c6444f4577467fa9223f which incidentally switched from
having 6 samplers to 1.
Bug #22895, #19856
|
|
This file is not even referenced by any Makefile.am
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
|
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
|
Also check intel-gen4asm tool here for new -g option, which is
required to compile new programs.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
|
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
