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path: root/src/sna/gen5_render.c
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2014-05-16sna/video: Only migrate the destination windowChris Wilson
By using move-area-to-gpu and specifying that we overwrite the target area, we can optimize away any needless damage migration. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-04-15sna: Mark partial composite operations upfrontChris Wilson
Rather than guess in the backend when we are going to be called for multiple boxes, rely on the frontend declaring it correctly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-04-04sna/gen2+: Beware the unattached ShmPixmapChris Wilson
When dereferences priv, make sure it exists first. ShmPixmaps for example, may not have one, nor do very small buffers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-04-04sna/gen2+: Replace composite sources with solids where possibleChris Wilson
If the composite reads entirely from within a large pixmap which is a clear color, just replace the source with a solid. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-03-14sna: Allow some leeway when deciding to discard common translationsChris Wilson
Under PictFilterNearest, we can ignore fractional translations (not all renderers discard those.) And if we are being approximate, we can loosen our tolerance as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-03-13sna: Nullify extra fill.opsChris Wilson
I forgot that the initial memset(&fill, 0, sizeof(fill)) was no longer performed and we rely on explicit initialisation during the setup, so add the missing fields. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76088 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-02-12sna/gen5: Flush the render cache between operationsChris Wilson
When we change the blend mode between operations, it appears that we must flush the render cache or else we risk render corruption. This is usually noticeable in rendering of single glyphs. This was originally fixed for bug 51422, but was reintroduced by commit 37eb7343be1aeeb90a860096756603a577df1a77 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sat Dec 1 09:40:11 2012 +0000 sna/gen5: Inspired by gen4, reorder the flushing and the desire to reduce the impact of this w/a. Reported-by: itumaykin@gmail.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74882 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-02-12sna: Support native primary plane rotationsChris Wilson
Use the display hardware for simple rotations, when exported through the rotation property on the CRTC. As the kernel support is not yet merged upstream, the feature is hidden behind --enable-rotation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-02-12sna/gen5: Use the DBG option ALWAYS_FLUSH to force a full flushChris Wilson
When flushing between operations, we can choose between doing a full flush to memory, or just a pipeline flush. For debugging it is better to do the full flush to rule out cache effects. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-02-12sna/gen5: Add a DBG option to force flushes between operationsChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-02-03sna/gen4,5: Fix setting pipe control cache flush bitsEdward Sheldrake
Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture cache invalidate is only available from Cantiga onwards.
2014-01-29sna/gen4+: Assert that the cached binding location is validChris Wilson
We can at least check that it is in the right region (i.e. not past where the current surface has been allocated from). References: https://bugs.freedesktop.org/show_bug.cgi?id=74176 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-01-24sna/gen2+: Inspect composite flags to discard unneeded CPU damageChris Wilson
We can now check whether the Composite operation will require existing CPU damage and if not discard it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-01-23sna: Avoid erroneous discarding operations for partial compositesChris Wilson
Composite operations were presumed to cover their entire width x height area. However, a few paths submit boxes that do not cover the clip region and so the optimisation made during prepare to discard completely overwritten data is incorrect (and leads to corruption - stale data is seen which the client expected to have been overdrawn). So along these more unusual paths, we must add a flag to prevent the overzealous discard. Notably, xfce4 triggers this as it uses a lot of unantialiased trapezoids in its theme drawing. References: https://bugs.freedesktop.org/show_bug.cgi?id=69528 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-01-07sna/gen4: Check for available batch space before restoring state after CA passChris Wilson
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73348 References: https://bugs.freedesktop.org/show_bug.cgi?id=55500 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-11-28sna: Tidy up an assertion on an uninitialised variableChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-11-22sna: Tidy up fallback from render composite to blt compositeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-11-19sna/gen4+: Clear redirect bo before falling back to BLT pathsChris Wilson
Just in case we later try to take action on the already freed redirection. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-11-02sna: Eliminate the redundancy between is_mappable/can_mapChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-30sna: Check for wedged after submittingChris Wilson
If we submit prior to an operation, check that we didn't just wedge the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-10sna/gen4+: Share a few common routinesChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-10sna: Pass usage hint down to render fill routinesChris Wilson
For the scanlines emitted for rendering Core drawing primitives, it is preferable to use the BLT engine, so pass those hints down. Reported-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-09sna/gen3+: Flush vertex buffer after computing resizeChris Wilson
Upon aligning the buffer, we may enlarge the vbo to accomodate the vertex alignment and push the current index past the end of the buffer. Move the space check from before the alignment computation to afterwards. Reported-by: Jiri Slaby <jirislaby@gmail.com> References: https://bugs.freedesktop.org/show_bug.cgi?id=47597 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-04sna/gen5: Replace pipe-control with full MI_FLUSH for required CS stallChris Wilson
It appears that we need top-of-pipe synchronisation for changing of certain state, and that the gen5 pipecontrol instruction is insufficient. So we have to fall back on the good old MI_FLUSH in order to make sure that the GPU invalidates its state correctly. Reported-by: Clemens Eisserer <linuxhippy@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51422 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-10-03intel: Remove dependence upon having PciInfoChris Wilson
After some probing mechanisms, we may end up with a valid device without knowing its PCI address a priori. Having a valid device, we can just query it for the correct device id, and can safely abort any path that requires PCI information that we don't have. (Those paths are not valid under such hosting anyway - if it may be required, we could reconstruct the address.) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-09-27sna/gen4+: Handle very large copies more gracefullyChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-09-25sna/gen[35]: Remove dead code for choosing between BLT/render compositeChris Wilson
For these gen, we always want to use BLT where possible - even if it incurs a context switch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-09-18intel: Compile fixes for base install of SLED11.sp3Chris Wilson
Highlights of that distribution include xorg-xserver-1.6.5, kernel 3.0.76 and gcc-4.3. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-28intel: Remove some unused macrosChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-23sna/gen5: The cached value of the pipelined pointers key requires 32-bitsChris Wilson
Storing only the low 16-bits of the key for the pipelined state meant that we forced an update with every new drawing op - with the side effect of flushing the render cache. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67157 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-22sna: Fix DBG compilationChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-22sna/gen5: Rework the flush after blend state changesChris Wilson
QA complained that the full flush to memory was too much of a performance hit, so let's try a lighter weight non-stalling pipe flush without. References: https://bugs.freedesktop.org/show_bug.cgi?id=67157 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-13sna: Skip copying to the intermediate target if we will completely overwrite itChris Wilson
Occasionally when forced to use an intermediate destination surface, we know that we will completely overwrite the contents of the surface and so we can forgo the initial copy from the target. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-07-12sna/gen5: Add some more DBGChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-28sna/gen2+: Consider precision in render operation placementChris Wilson
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66297 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-26sna/gen4+: Fix determination of intermediate extentsChris Wilson
Complete logic fail for finding the bounding box of the boxes to be copied. Reported-by: Clemens Eisserer <linuxhippy@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66168 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-23sna/gen5: Elide the forced flush after a drawrectChris Wilson
Presume that the non-pipelined drawrect is sufficient to serialise operations to the render cache. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-23sna/gen5: Force a write flush when changing blend modesChris Wilson
Otherwise it appears that the hardware will readback from memory bypassing its render cache after a change of modes. There is probably a lot more subtly to it than this, but this appears to be a good first approximation. Reported-by: Clemens Eisserer <linuxhippy@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51422 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-14sna/gen3+: Remove redundant clearing of clear hint in video playbackChris Wilson
The clear hint is correctly updated when performing the move-to-gpu and so it is being superfluously repeated by the callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-13sna/gen2+: Promote a conditional dirty into an assertionChris Wilson
If the target bo is not bound when we start to emit the composite state for the operation, we are screwed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-05-28sna: Make the backend identifier more informativeChris Wilson
This is useful, for example, with the multiple gen7 variants. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-04-12sna/gen5: Force a MI_FLUSH between using the BLT and RENDER enginesChris Wilson
There is a workaround that says the first RENDER command following use of the BLT should be a non-pipelined command. To be safe, emit a MI_FLUSH before setting up the invariants. Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1168066 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-03-27sna/gen4+: Set read-write allocation mode for the target render cacheChris Wilson
As we often first clear the destination before performing a blend, we get a performance boost if that first write populates the render cache. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-03-14sna/gen5+: Add missing float casts in computation of scaled src offsetsChris Wilson
Without the casts, the division ends up as 0 rather than the fractional offset into the texture. The casts were missed in the claimed fix: commit 89038ddb96aabc4bc1f04402b2aca0ce546e8bf3 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Feb 28 14:35:54 2013 +0000 sna/video: Correct scaling of source offsets Reported-by: Roman Elshin <roman.elshin@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62343 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-28sna/video: Correct scaling of source offsetsChris Wilson
When applying pan and zoom to a mismatched video, it would inevitably miscompute the origin and scale factors. Reported-by: Matti Hamalainen <ccr@tnsp.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61610 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-26sna: Reverse inverted assertionsChris Wilson
Oops, the assertions that we had sufficient free space was inverted. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-26sna/gen4+: Begin specialising vertex programs for ISAChris Wilson
Allow use of advanced ISA when available by detecting support at runtime. This initial work just uses GCC to emit varying ISA, future work could use hand written code for these hot spots. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-25sna/gen3+: Restart vertex space checks after lock contentionChris Wilson
If we end up contending for the vertex lock, we need to double check there is sufficient vertex space left for us. Bugzill: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1124576 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-25sna/gen3+: Assert that nbox is not 0Chris Wilson
Various assertions to track down a potential programming error. References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1124576 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-02-08sna/gen4: Split the have_render flag in separate prefer_gpu hintsChris Wilson
The idea is to implement more fine-grained checks as we may want different heuristics for desktops with GT1s than for mobile GT2s, etc. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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