| Age | Commit message (Collapse) | Author |
|---|
|
According to several users, a default brightness of 0 results in much better TV
output. Improved control of these parameters will be provided by Randr1.3,
which will standardize several output properties across various chips.
|
|
Allows users to use 1080p modes on TV out, see bug #13034.
|
|
i830_reg.h only contains 3d engine cmds for 8XX chips.
|
|
where we put MMIO control reg in, and shared with intel_reg_dump
program.
|
|
Open the "actual_brightness" file as read only, since we only read from it.
Also set an initial backlight_duty_cycle at init time so we don't set the
brightness to 0 at startup.
|
|
Several people have reported that they see frequent FBC related display
corruption on 965GM, so disable it for now. Users wanting to enable it can use
the driver option "Framebuffercompression" to override the default.
|
|
Needed for the new debug code
|
|
We need to look at "actual_brightness" rather than "brightness". The former
contains the brightness value the kernel driver has actually set, while the
latter is merely what the user requested.
|
|
To be consistent, it should say 'plane' rather than 'pipe'.
|
|
Just for completeness.
|
|
Some of the hw state restoration callbacks may want to use the ring for various
things like stopping video playback, so leave the ring enabled until we get
back from RestoreHWState. Also rename the functions so that their purpose is
clearer and remove a couple of redundant lines.
|
|
This slightly reworks my last fbc patch. We don't
support tiled front buffer with XAA now, so also
disable fbc on it. If tiled alloc failed, disable
fbc too.
|
|
The PLL spreadsheet makes the precise register ranges allowed for each mode
quite clear, and shows a few inaccuracies in the b-spec. In particular, the
N register value may range from 1 to 6 instead of 3 to 8. This should close
the gap we've seen in the reachable frequencies.
|
|
|
|
|
|
This really isn't an error in general. If vblank pipe setup really fails for
some reason, it'll be obvious enough when the user tries to use vblank events
for something.
Patch from Hong Liu.
|
|
This commit fixes backlight support for several platforms.
Except on recent machines supporting the IGD OpRegion specification,
backlight control is rather platform specific. In some cases, we can
program the native backlight control regsiters directly without any
trouble. On others, we need to use the legacy backlight control
register. On still others, we need a combination of the two. And on
some platforms, none of the above will work, so we go through the
kernel backlight interface, which provides a platform specific driver
for backlight control.
|
|
Check against DPLL_A instead of DPLL_B before writing PIPEACONF.
Thanks to Colin Guthrie for his sharp eyes.
|
|
Needed in the XF86DRI_MM case.
|
|
Remove unused 'ret' variable, move pI830 under #ifdef XF86DRI_MM in
i830_allocate_memory.
|
|
|
|
If EXA is compiled into the driver, default to using it for acceleration.
Hopefully we can remove XAA entirely one day.
|
|
When calling the video DPMS off function, make sure we zero out the current
crtc so that it will be properly re-set up next time video is turned on.
Fix from Peter Clifton with changes by Keith Packard.
|
|
The overlay width & height scaling clamp check was reversed. Fix that and
update the comment.
|
|
In the absence of full suspend/resume support in the kernel, we have to
save/restore state in Enter/LeaveVT. For 8xx chips, 3D state may be lost
during suspend/resume, so re-emit the basic setup at EnterVT time.
Patch from Peter Clifton.
|
|
While I'm here, fix the chip description to be LVDS instead of TMDS in i2c
device.
|
|
If the DPLL isn't enabled or is in VGA mode, writing the PIPEnCONF registers
may cause a hang or crash. So ensure the DPLL is in the proper state before
writing them.
Another excellent fix from Peter Clifton.
|
|
Fix a long standing bug in the framebuffer compression code (thanks to
Pierre Willenbrock!) that prevented FBC from working correctly if the front
buffer was anywhere but fence register 0.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Add a VGA AR dumping function so we can debug text mode problems too.
|
|
This shows one of the reasons for the gaps: with the other settings, the VCO
is too low inside the gap. However, it also points out another issue: we
aren't using the high end of the VCO range due to some other limits being hit.
|
|
|
|
While here, move similar nickle scripts under src/scripts/
|
|
This shouldn't make a difference now, but for upcoming EXA/batch changes it
will be more useful
|
|
|
|
|
|
|
|
Failure to do so led to the memset() at EnterVT being done to an invalid
offset.
|
|
When restoring the palette, we weren't checking to make sure the
associated pipe was enabled before writing the registers. In some
configurations, this led to a driver crash. Add new routines to handle
palette save/restore and verify that the pipes are on before we touch
the registers (could easily be changed to enable/disable the pipes
around the save/restore as well).
|
|
|
|
This doesn't help with the most common use-while-unbound cases, which are
from the hardware side.
|
|
|
|
|
|
This allows us to allocate tiled buffers in buffer objects. In the process
I removed the fence division that we had for tiled buffers on pre-965. If we
resurrect that code, it should probably be managed by just dividing all the
objects in roughly half and fencing those halves (to reduce the alignment
requirement), instead of using giant fences until we run out of space and then
trying to deal with scarce space on the last (or not) buffer. Halving
our tiled objects would use 6/8 of our fence registers on that hardware.
|
|
|
