From f4c05973d391bdb0a9b0eadb155548310baa98fd Mon Sep 17 00:00:00 2001 From: Wang Zhenyu Date: Tue, 5 Jun 2007 11:07:41 -0700 Subject: Add support for the G33, Q33, and Q35 chipsets. These chipsets require that the hardware status page be referenced by an offset in the GTT rather than a physical memory address, so the X Server allocates it rather than the DRM. --- src/common.h | 20 +++++++++++++++++++- src/i810_driver.c | 9 +++++++++ src/i810_reg.h | 15 ++++++++++----- src/i830.h | 1 + src/i830_common.h | 5 +++++ src/i830_dri.c | 22 ++++++++++++++++++++++ src/i830_driver.c | 38 +++++++++++++++++++++++++++++++++++++- src/i830_exa.c | 2 +- src/i830_memory.c | 21 +++++++++++++++++++++ src/i830_video.c | 2 +- 10 files changed, 126 insertions(+), 9 deletions(-) diff --git a/src/common.h b/src/common.h index c879333a..2369a750 100644 --- a/src/common.h +++ b/src/common.h @@ -361,6 +361,21 @@ extern int I810_DEBUG; #define PCI_CHIP_I965_GM_BRIDGE 0x2A00 #endif +#ifndef PCI_CHIP_G33_G +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_G33_G_BRIDGE 0x29C0 +#endif + +#ifndef PCI_CHIP_Q35_G +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q35_G_BRIDGE 0x29B0 +#endif + +#ifndef PCI_CHIP_Q33_G +#define PCI_CHIP_Q33_G 0x29D2 +#define PCI_CHIP_Q33_G_BRIDGE 0x29D0 +#endif + #define IS_I810(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I810 || \ pI810->PciInfo->chipType == PCI_CHIP_I810_DC100 || \ pI810->PciInfo->chipType == PCI_CHIP_I810_E) @@ -378,7 +393,10 @@ extern int I810_DEBUG; #define IS_I945GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_GM || pI810->PciInfo->chipType == PCI_CHIP_I945_GME) #define IS_I965GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_GM || pI810->PciInfo->chipType == PCI_CHIP_I965_GME) #define IS_I965G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_G || pI810->PciInfo->chipType == PCI_CHIP_I965_G_1 || pI810->PciInfo->chipType == PCI_CHIP_I965_Q || pI810->PciInfo->chipType == PCI_CHIP_I946_GZ || pI810->PciInfo->chipType == PCI_CHIP_I965_GM || pI810->PciInfo->chipType == PCI_CHIP_I965_GME) -#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810)) +#define IS_G33CLASS(pI810) (pI810->PciInfo->chipType == PCI_CHIP_G33_G ||\ + pI810->PciInfo->chipType == PCI_CHIP_Q35_G ||\ + pI810->PciInfo->chipType == PCI_CHIP_Q33_G) +#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810)) #define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810)) diff --git a/src/i810_driver.c b/src/i810_driver.c index 5b04a476..972b6d50 100644 --- a/src/i810_driver.c +++ b/src/i810_driver.c @@ -147,6 +147,9 @@ static SymTabRec I810Chipsets[] = { {PCI_CHIP_I946_GZ, "946GZ"}, {PCI_CHIP_I965_GM, "965GM"}, {PCI_CHIP_I965_GME, "965GME/GLE"}, + {PCI_CHIP_G33_G, "G33"}, + {PCI_CHIP_Q35_G, "Q35"}, + {PCI_CHIP_Q33_G, "Q33"}, {-1, NULL} }; @@ -173,6 +176,9 @@ static PciChipsets I810PciChipsets[] = { {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA}, {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA}, {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, RES_SHARED_VGA}, + {PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA}, + {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA}, + {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA}, {-1, -1, RES_UNDEFINED } }; @@ -620,6 +626,9 @@ I810Probe(DriverPtr drv, int flags) case PCI_CHIP_I946_GZ: case PCI_CHIP_I965_GM: case PCI_CHIP_I965_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: xf86SetEntitySharable(usedChips[i]); /* Allocate an entity private if necessary */ diff --git a/src/i810_reg.h b/src/i810_reg.h index 234d124f..8df664e0 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -525,6 +525,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PGETBL_SIZE_512KB (0 << 1) #define PGETBL_SIZE_256KB (1 << 1) #define PGETBL_SIZE_128KB (2 << 1) +#define G33_PGETBL_SIZE_MASK (3 << 8) +#define G33_PGETBL_SIZE_1M (1 << 8) +#define G33_PGETBL_SIZE_2M (2 << 8) #define I830_PTE_BASE 0x10000 #define PTE_ADDRESS_MASK 0xfffff000 @@ -2076,12 +2079,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define I830_GMCH_MEM_64M 0x1 #define I830_GMCH_MEM_128M 0 -#define I830_GMCH_GMS_MASK 0x70 -#define I830_GMCH_GMS_DISABLED 0x00 +#define I830_GMCH_GMS_MASK 0xF0 +#define I830_GMCH_GMS_DISABLED 0x00 #define I830_GMCH_GMS_LOCAL 0x10 -#define I830_GMCH_GMS_STOLEN_512 0x20 -#define I830_GMCH_GMS_STOLEN_1024 0x30 -#define I830_GMCH_GMS_STOLEN_8192 0x40 +#define I830_GMCH_GMS_STOLEN_512 0x20 +#define I830_GMCH_GMS_STOLEN_1024 0x30 +#define I830_GMCH_GMS_STOLEN_8192 0x40 #define I830_RDRAM_CHANNEL_TYPE 0x03010 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) @@ -2096,6 +2099,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) #define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4) #define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4) +#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) +#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) #define I85X_CAPID 0x44 #define I85X_VARIANT_MASK 0x7 diff --git a/src/i830.h b/src/i830.h index 76cc6e87..e4d50706 100644 --- a/src/i830.h +++ b/src/i830.h @@ -319,6 +319,7 @@ typedef struct _I830Rec { i830_memory *depth_buffer; i830_memory *textures; /**< Compatibility texture memory */ i830_memory *memory_manager; /**< DRI memory manager aperture */ + i830_memory *hw_status; /* for G33 hw status page alloc */ int TexGranularity; int drmMinor; diff --git a/src/i830_common.h b/src/i830_common.h index f853ccd8..5c2d919e 100644 --- a/src/i830_common.h +++ b/src/i830_common.h @@ -54,6 +54,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define DRM_I830_DESTROY_HEAP 0x0c #define DRM_I830_SET_VBLANK_PIPE 0x0d #define DRM_I830_GET_VBLANK_PIPE 0x0e +#define DRM_I830_HWS_PAGE_ADDR 0x11 typedef struct { @@ -224,4 +225,8 @@ typedef struct { int pipe; } drmI830VBlankPipe; +typedef struct { + uint64_t addr; +} drmI830HWS; + #endif /* _I830_DRM_H_ */ diff --git a/src/i830_dri.c b/src/i830_dri.c index 663ef148..a17770bf 100644 --- a/src/i830_dri.c +++ b/src/i830_dri.c @@ -232,6 +232,22 @@ I830SetParam(ScrnInfoPtr pScrn, int param, int value) return TRUE; } +static Bool +I830SetHWS(ScrnInfoPtr pScrn, int addr) +{ + I830Ptr pI830 = I830PTR(pScrn); + drmI830HWS hws; + + hws.addr = addr; + + if (drmCommandWrite(pI830->drmSubFD, DRM_I830_HWS_PAGE_ADDR, + &hws, sizeof(drmI830HWS))) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "G33 status page initialization Failed\n"); + return FALSE; + } + return TRUE; +} static Bool I830InitVisualConfigs(ScreenPtr pScreen) @@ -933,6 +949,12 @@ I830DRIDoMappings(ScreenPtr pScreen) return FALSE; } + if (IS_G33CLASS(pI830)) { + if (!I830SetHWS(pScrn, pI830->hw_status->offset)) { + DRICloseScreen(pScreen); + return FALSE; + } + } /* init to zero to be safe */ sarea->front_handle = 0; sarea->back_handle = 0; diff --git a/src/i830_driver.c b/src/i830_driver.c index 1290d6d3..3133d775 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -236,6 +236,9 @@ static SymTabRec I830Chipsets[] = { {PCI_CHIP_I946_GZ, "946GZ"}, {PCI_CHIP_I965_GM, "965GM"}, {PCI_CHIP_I965_GME, "965GME/GLE"}, + {PCI_CHIP_G33_G, "G33"}, + {PCI_CHIP_Q35_G, "Q35"}, + {PCI_CHIP_Q33_G, "Q33"}, {-1, NULL} }; @@ -256,6 +259,9 @@ static PciChipsets I830PciChipsets[] = { {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA}, {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA}, {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, RES_SHARED_VGA}, + {PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA}, + {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA}, + {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA}, {-1, -1, RES_UNDEFINED} }; @@ -436,6 +442,19 @@ I830DetectMemory(ScrnInfoPtr pScrn) default: FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL)); } + } else if (IS_G33CLASS(pI830)) { + /* G33's GTT size is detect in GMCH_CTRL */ + switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { + case G33_PGETBL_SIZE_1M: + gtt_size = 1024; + break; + case G33_PGETBL_SIZE_2M: + gtt_size = 2048; + break; + default: + FatalError("Unknown GTT size value: %08x\n", + (int)(gmch_ctrl & G33_PGETBL_SIZE_MASK)); + } } else { /* Older chipsets only had GTT appropriately sized for the aperture. */ gtt_size = pI830->FbMapSize / (1024*1024); @@ -473,6 +492,14 @@ I830DetectMemory(ScrnInfoPtr pScrn) if (IS_I9XX(pI830)) memsize = MB(64) - KB(range); break; + case G33_GMCH_GMS_STOLEN_128M: + if (IS_G33CLASS(pI830)) + memsize = MB(128) - KB(range); + break; + case G33_GMCH_GMS_STOLEN_256M: + if (IS_G33CLASS(pI830)) + memsize = MB(256) - KB(range); + break; } } else { switch (gmch_ctrl & I830_GMCH_GMS_MASK) { @@ -1076,6 +1103,15 @@ I830PreInit(ScrnInfoPtr pScrn, int flags) case PCI_CHIP_I965_GME: chipname = "965GME/GLE"; break; + case PCI_CHIP_G33_G: + chipname = "G33"; + break; + case PCI_CHIP_Q35_G: + chipname = "Q35"; + break; + case PCI_CHIP_Q33_G: + chipname = "Q33"; + break; default: chipname = "unknown chipset"; break; @@ -1430,7 +1466,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags) else pI830->CursorNeedsPhysical = FALSE; - if (IS_I965G(pI830)) + if (IS_I965G(pI830) || IS_G33CLASS(pI830)) pI830->CursorNeedsPhysical = FALSE; /* diff --git a/src/i830_exa.c b/src/i830_exa.c index 88d1b97b..bb60c0ac 100644 --- a/src/i830_exa.c +++ b/src/i830_exa.c @@ -509,7 +509,7 @@ I830EXAInit(ScreenPtr pScreen) pI830->EXADriverPtr->Composite = i830_composite; pI830->EXADriverPtr->DoneComposite = i830_done_composite; } else if (IS_I915G(pI830) || IS_I915GM(pI830) || - IS_I945G(pI830) || IS_I945GM(pI830)) + IS_I945G(pI830) || IS_I945GM(pI830) || IS_G33CLASS(pI830)) { pI830->EXADriverPtr->CheckComposite = i915_check_composite; pI830->EXADriverPtr->PrepareComposite = i915_prepare_composite; diff --git a/src/i830_memory.c b/src/i830_memory.c index 3ae10cfb..747cfcce 100644 --- a/src/i830_memory.c +++ b/src/i830_memory.c @@ -1312,6 +1312,22 @@ i830_allocate_texture_memory(ScrnInfoPtr pScrn) return TRUE; } +static Bool +i830_allocate_hwstatus(ScrnInfoPtr pScrn) +{ +#define HWSTATUS_PAGE_SIZE (4*1024) + I830Ptr pI830 = I830PTR(pScrn); + + pI830->hw_status = i830_allocate_memory(pScrn, "G33 hw status", + HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, 0); + if (pI830->hw_status == NULL) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Failed to allocate hw status page for G33.\n"); + return FALSE; + } + return TRUE; +} + Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn) { @@ -1319,6 +1335,11 @@ i830_allocate_3d_memory(ScrnInfoPtr pScrn) DPRINTF(PFX, "i830_allocate_3d_memory\n"); + if (IS_G33CLASS(pI830)) { + if (!i830_allocate_hwstatus(pScrn)) + return FALSE; + } + if (!i830_allocate_backbuffer(pScrn, &pI830->back_buffer, &pI830->back_tiled, "back buffer")) return FALSE; diff --git a/src/i830_video.c b/src/i830_video.c index b8726a80..e5efcaad 100644 --- a/src/i830_video.c +++ b/src/i830_video.c @@ -572,7 +572,7 @@ I830InitVideo(ScreenPtr pScreen) } /* Set up overlay video if we can do it at this depth. */ - if (!IS_I965G(pI830) && pScrn->bitsPerPixel != 8 && + if (!IS_I965G(pI830) && !IS_G33CLASS(pI830) && pScrn->bitsPerPixel != 8 && pI830->overlay_regs != NULL) { overlayAdaptor = I830SetupImageVideoOverlay(pScreen); -- cgit v1.2.3