From 1cbc59a917e7352fc68aa0e26b1575cbd0ceab0d Mon Sep 17 00:00:00 2001 From: Edward Sheldrake Date: Mon, 3 Feb 2014 09:34:33 +0000 Subject: sna/gen4,5: Fix setting pipe control cache flush bits Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture cache invalidate is only available from Cantiga onwards. --- src/sna/gen4_render.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/sna/gen4_render.h') diff --git a/src/sna/gen4_render.h b/src/sna/gen4_render.h index 53c7fc2f..64d11e66 100644 --- a/src/sna/gen4_render.h +++ b/src/sna/gen4_render.h @@ -112,7 +112,7 @@ #define GEN4_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define GEN4_PIPE_CONTROL_WC_FLUSH (1 << 12) #define GEN4_PIPE_CONTROL_IS_FLUSH (1 << 11) -#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) +#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) /* ctg+ */ #define GEN4_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define GEN4_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define GEN4_PIPE_CONTROL_LOCAL_PGTT (0 << 2) -- cgit v1.2.3