Bump up clock rate for ES1000 to allow higher resolutions

1 files changed, 5 insertions, 2 deletions

diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4b79f28..2d913c2 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1694,9 +1694,12 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
     if (info->ChipFamily == CHIP_FAMILY_RV100 && !info->HasCRTC2) {
         /* Avoid RN50 corruption due to memory bandwidth starvation.
          * 18 is an empirical value based on the databook and Windows driver.
-        */
+         *
+	 * Empirical value changed to 24 to raise pixel clock limit and
+	 * allow higher resolution modes on capable monitors
+	 */
         pll->max_pll_freq = min(pll->max_pll_freq,
-                               18 * info->mclk * 100 / pScrn->bitsPerPixel *
+                               24 * info->mclk * 100 / pScrn->bitsPerPixel *
                                info->RamWidth / 16);
     }