RADEON: implement CLUT adjust support

3 files changed, 74 insertions, 16 deletions

diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9192a9e..c4a5d11 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -980,8 +980,25 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc)
     if (!crtc->enabled)
 	return;
 
+    if (IS_AVIVO_VARIANT) {
+	OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
+
+	OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+	OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+	OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+	OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+	OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+	OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
+    }
+
     PAL_SELECT(radeon_crtc->crtc_id);
 
+    if (IS_AVIVO_VARIANT) {
+	OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
+	OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
+    }
+
     for (i = 0; i < 256; i++) {
 	OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
     }
@@ -995,13 +1012,8 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green,
 {
     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
     ScrnInfoPtr		pScrn = crtc->scrn;
-    RADEONInfoPtr info = RADEONPTR(pScrn);
     int i, j;
 
-    // fix me
-    if (IS_AVIVO_VARIANT)
-	return;
-
     if (pScrn->depth == 16) {
 	for (i = 0; i < 64; i++) {
 	    if (i <= 31) {
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index 4359eb8..7f532a8 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -92,12 +92,20 @@ do {									\
 
 #define OUTPAL_START(idx)						\
 do {									\
-    OUTREG8(RADEON_PALETTE_INDEX, (idx));				\
+    if (IS_AVIVO_VARIANT) {                                             \
+        OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx));				\
+    } else {                                                            \
+        OUTREG8(RADEON_PALETTE_INDEX, (idx));				\
+    }								        \
 } while (0)
 
 #define OUTPAL_NEXT(r, g, b)						\
 do {									\
-    OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));	\
+    if (IS_AVIVO_VARIANT) {                                             \
+        OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2));	\
+    } else {                                                               \
+        OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));	\
+    }								        \
 } while (0)
 
 #define OUTPAL_NEXT_CARD32(v)						\
@@ -113,20 +121,39 @@ do {									\
 
 #define INPAL_START(idx)						\
 do {									\
-    OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);				\
+    if (IS_AVIVO_VARIANT) {                                             \
+        OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx));				\
+    } else {                                                            \
+        OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);			\
+    }								        \
 } while (0)
 
-#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
+#define INPAL_NEXT()                                                    \
+do {									\
+    if (IS_AVIVO_VARIANT) {                                             \
+        INREG(AVIVO_DC_LUT_30_COLOR);                                   \
+    } else {                                                            \
+        INREG(RADEON_PALETTE_DATA);                                     \
+    }								        \
+} while (0)
 
 #define PAL_SELECT(idx)							\
 do {									\
-    if (!idx) {								\
-	OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &		\
-	       (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL);			\
-    } else {								\
-	OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |		\
-	       RADEON_DAC2_PALETTE_ACC_CTL);				\
-    }									\
+    if (IS_AVIVO_VARIANT) {                                             \
+        if (!idx) {							\
+	    OUTREG(AVIVO_DC_LUT_RW_SELECT, 0);                          \
+        } else {						        \
+	    OUTREG(AVIVO_DC_LUT_RW_SELECT, 1);                          \
+        }								\
+    } else {                                                            \
+        if (!idx) {							\
+	    OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &		\
+	           (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL);		\
+        } else {							\
+	    OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |		\
+	           RADEON_DAC2_PALETTE_ACC_CTL);			\
+        }								\
+    }								        \
 } while (0)
 
 #define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 1860fa4..8737d2e 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3402,6 +3402,25 @@
 #define AVIVO_D1CUR_POSITION                    0x6414
 #define AVIVO_D1CUR_HOT_SPOT                    0x6418
 
+#define AVIVO_DC_LUT_RW_SELECT                  0x6480
+#define AVIVO_DC_LUT_RW_MODE                    0x6484
+#define AVIVO_DC_LUT_RW_INDEX                   0x6488
+#define AVIVO_DC_LUT_SEQ_COLOR                  0x648c
+#define AVIVO_DC_LUT_PWL_DATA                   0x6490
+#define AVIVO_DC_LUT_30_COLOR                   0x6494
+#define AVIVO_DC_LUT_READ_PIPE_SELECT           0x6498
+#define AVIVO_DC_LUT_WRITE_EN_MASK              0x649c
+#define AVIVO_DC_LUT_AUTOFILL                   0x64a0
+
+#define AVIVO_DC_LUTA_CONTROL                   0x64c0
+#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE         0x64c4
+#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN        0x64c8
+#define AVIVO_DC_LUTA_BLACK_OFFSET_RED          0x64cc
+#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE         0x64d0
+#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN        0x64d4
+#define AVIVO_DC_LUTA_WHITE_OFFSET_RED          0x64d8
+
+
 #define AVIVO_D1MODE_VIEWPORT_START             0x6580
 #define AVIVO_D1MODE_VIEWPORT_SIZE              0x6584
 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT    0x6588