diff options
author | Adam Jackson <ajax@nwnk.net> | 2004-07-10 14:22:35 +0000 |
---|---|---|
committer | Adam Jackson <ajax@nwnk.net> | 2004-07-10 14:22:35 +0000 |
commit | 9b0ec803bd588d9af778bfd307ee6d958e4a1e73 (patch) | |
tree | 73628fca45ee30475c72880718c3e98a8ee83004 | |
parent | ccd95bfb291a0c70272fab6822ef379b83dc298d (diff) |
Bugzilla #849: Fix DRI pagesize assumptions in radeon and r128 drivers.
from mharris@, reviewed and applied to DRI by airlied@.
-rw-r--r-- | src/r128_dri.c | 20 | ||||
-rw-r--r-- | src/radeon_dri.c | 16 |
2 files changed, 12 insertions, 24 deletions
diff --git a/src/r128_dri.c b/src/r128_dri.c index 4dec476..2b35c33 100644 --- a/src/r128_dri.c +++ b/src/r128_dri.c @@ -56,15 +56,7 @@ #include "GL/glxtokens.h" #include "sarea.h" -/* ?? HACK - for now, put this here... */ -/* ?? Alpha - this may need to be a variable to handle UP1x00 vs TITAN */ -#if defined(__alpha__) -# define DRM_PAGE_SIZE 8192 -#elif defined(__ia64__) -# define DRM_PAGE_SIZE getpagesize() -#else -# define DRM_PAGE_SIZE 4096 -#endif +static size_t r128_drm_page_size; static void R128DRITransitionTo2d(ScreenPtr pScreen); static void R128DRITransitionTo3d(ScreenPtr pScreen); @@ -502,11 +494,11 @@ static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen) /* Initialize the CCE ring buffer data */ info->ringStart = info->agpOffset; - info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE; + info->ringMapSize = info->ringSize*1024*1024 + r128_drm_page_size; info->ringSizeLog2QW = R128MinBits(info->ringSize*1024*1024/8) - 1; info->ringReadOffset = info->ringStart + info->ringMapSize; - info->ringReadMapSize = DRM_PAGE_SIZE; + info->ringReadMapSize = r128_drm_page_size; /* Reserve space for vertex/indirect buffers */ info->bufStart = info->ringReadOffset + info->ringReadMapSize; @@ -655,11 +647,11 @@ static Bool R128DRIPciInit(R128InfoPtr info, ScreenPtr pScreen) /* Initialize the CCE ring buffer data */ info->ringStart = info->agpOffset; - info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE; + info->ringMapSize = info->ringSize*1024*1024 + r128_drm_page_size; info->ringSizeLog2QW = R128MinBits(info->ringSize*1024*1024/8) - 1; info->ringReadOffset = info->ringStart + info->ringMapSize; - info->ringReadMapSize = DRM_PAGE_SIZE; + info->ringReadMapSize = r128_drm_page_size; /* Reserve space for vertex/indirect buffers */ info->bufStart = info->ringReadOffset + info->ringReadMapSize; @@ -1016,6 +1008,8 @@ Bool R128DRIScreenInit(ScreenPtr pScreen) break; } + r128_drm_page_size = getpagesize(); + /* Create the DRI data structure, and fill it in before calling the DRIScreenInit(). */ if (!(pDRIInfo = DRICreateInfoRec())) return FALSE; diff --git a/src/radeon_dri.c b/src/radeon_dri.c index 6414b56..176adf8 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -56,15 +56,7 @@ #include "sarea.h" #include "radeon_sarea.h" -/* HACK - for now, put this here... */ -/* Alpha - this may need to be a variable to handle UP1x00 vs TITAN */ -#if defined(__alpha__) -# define DRM_PAGE_SIZE 8192 -#elif defined(__ia64__) -# define DRM_PAGE_SIZE getpagesize() -#else -# define DRM_PAGE_SIZE 4096 -#endif +static size_t radeon_drm_page_size; static Bool RADEONDRICloseFullScreen(ScreenPtr pScreen); @@ -701,11 +693,11 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) /* Initialize the CP ring buffer data */ info->ringStart = info->gartOffset; - info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; info->ringSizeLog2QW = RADEONMinBits(info->ringSize*1024*1024/8)-1; info->ringReadOffset = info->ringStart + info->ringMapSize; - info->ringReadMapSize = DRM_PAGE_SIZE; + info->ringReadMapSize = radeon_drm_page_size; /* Reserve space for vertex/indirect buffers */ info->bufStart = info->ringReadOffset + info->ringReadMapSize; @@ -1234,6 +1226,8 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) break; } + radeon_drm_page_size = getpagesize(); + /* Create the DRI data structure, and fill it in before calling the * DRIScreenInit(). */ |