radeon: add option to set pci aperture size from config file

This requires a drm > 1.26 to work

6 files changed, 76 insertions, 35 deletions

diff --git a/src/radeon.h b/src/radeon.h
index 37ca67d..c976b0a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -110,6 +110,7 @@ typedef enum {
     OPTION_XV_DMA,
     OPTION_FBTEX_PERCENT,
     OPTION_DEPTH_BITS,
+    OPTION_PCIAPER_SIZE,
 #ifdef USE_EXA
     OPTION_ACCEL_DFS,
 #endif
@@ -607,6 +608,7 @@ typedef struct {
 #endif
     Bool              have3DWindows;    /* Are there any 3d clients? */
 
+    unsigned int      pciAperSize;
     drmSize           gartSize;
     drm_handle_t         agpMemHandle;     /* Handle from drmAgpAlloc */
     unsigned long     gartOffset;
@@ -832,6 +834,7 @@ extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
 extern void        RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
 extern void        RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
 #ifdef XF86DRI
+extern int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value);
 extern void        RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
 #endif
 
diff --git a/src/radeon_common.h b/src/radeon_common.h
index be6dc8f..3f2c6ab 100644
--- a/src/radeon_common.h
+++ b/src/radeon_common.h
@@ -472,6 +472,7 @@ typedef struct drm_radeon_set_param {
 #define RADEON_SETPARAM_SWITCH_TILING   2
 #define RADEON_SETPARAM_PCIGART_LOCATION 3
 #define RADEON_SETPARAM_NEW_MEMMAP 4
+#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
 
 /* 1.14: Clients can allocate/free a surface
  */
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 39c72db..ee6192e 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -2078,7 +2078,11 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
     if (info->FbSecureSize==0)
       return;
 
-    info->pciGartSize = RADEON_PCIGART_TABLE_SIZE;
+    /* set the old default size of pci gart table */
+    if (info->pKernelDRMVersion->version_minor < 26)
+      info->pciGartSize = 32768;
+
+    info->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
 
     /* allocate space to back up PCIEGART table */
     info->pciGartBackup = xnfcalloc(1, info->pciGartSize);
@@ -2089,3 +2093,31 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
 
 
 }
+
+int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info   = RADEONPTR(pScrn);
+    int page_size  = getpagesize();
+    int ret_size;
+    int num_pages;
+
+    num_pages = (info->pciAperSize * 1024 * 1024) / page_size;
+    
+    ret_size = num_pages * sizeof(unsigned int);
+
+    return ret_size;
+}
+
+int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
+{
+    drmRadeonSetParam  radeonsetparam;
+    RADEONInfoPtr  info   = RADEONPTR(pScrn);
+    int ret;
+
+    memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
+    radeonsetparam.param = param;
+    radeonsetparam.value = value;
+    ret = drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
+			  &radeonsetparam, sizeof(drmRadeonSetParam));
+    return ret;
+}
diff --git a/src/radeon_dri.h b/src/radeon_dri.h
index 6fa7e35..3b54626 100644
--- a/src/radeon_dri.h
+++ b/src/radeon_dri.h
@@ -48,7 +48,7 @@
 
 #define RADEON_DEFAULT_CP_TIMEOUT     10000  /* usecs */
 
-#define RADEON_PCIGART_TABLE_SIZE     32768
+#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
 
 #define RADEON_CARD_TYPE_RADEON       1
 
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index d1cd790..ca0b201 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -153,6 +153,7 @@ static const OptionInfoRec RADEONOptions[] = {
     { OPTION_XV_DMA,         "DMAForXv",         OPTV_BOOLEAN, {0}, FALSE },
     { OPTION_FBTEX_PERCENT,  "FBTexPercent",     OPTV_INTEGER, {0}, FALSE },
     { OPTION_DEPTH_BITS,     "DepthBits",        OPTV_INTEGER, {0}, FALSE },
+    { OPTION_PCIAPER_SIZE,  "PCIAPERSize",      OPTV_INTEGER, {0}, FALSE },
 #ifdef USE_EXA
     { OPTION_ACCEL_DFS,      "AccelDFS",         OPTV_BOOLEAN, {0}, FALSE },
 #endif
@@ -1482,7 +1483,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
     /* if the card is PCI Express reserve the last 32k for the gart table */
 #ifdef XF86DRI
     if (info->cardType == CARD_PCIE && info->directRenderingEnabled)
-        info->FbSecureSize = RADEON_PCIGART_TABLE_SIZE;
+      /* work out the size of pcie aperture */
+        info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn);
     else
 #endif
 	info->FbSecureSize = 0;
@@ -2573,7 +2575,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
     info->ringSize      = RADEON_DEFAULT_RING_SIZE;
     info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
     info->gartTexSize   = RADEON_DEFAULT_GART_TEX_SIZE;
-
+    info->pciAperSize   = RADEON_DEFAULT_PCI_APER_SIZE;
     info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
 
     if ((xf86GetOptValInteger(info->Options,
@@ -2608,6 +2610,23 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
     }
 
     if (xf86GetOptValInteger(info->Options,
+			     OPTION_PCIAPER_SIZE, &(info->pciAperSize))) {
+      switch(info->pciAperSize) {
+      case 32:
+      case 64:
+      case 128:
+      case 256:
+	break;
+      default:
+	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+		       "Illegal pci aper size: %d MB\n",
+		       info->pciAperSize);
+	return FALSE;
+      }
+    }
+
+
+    if (xf86GetOptValInteger(info->Options,
 			     OPTION_BUFFER_SIZE, &(info->bufSize))) {
 	if (info->bufSize < 1 || info->bufSize >= (int)info->gartSize) {
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -3973,21 +3992,17 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 	}
     }
 
+#if defined(XF86DRI)
     /* Tell DRI about new memory map */
     if (info->directRenderingEnabled && info->newMemoryMap) {
-	drmRadeonSetParam  radeonsetparam;
-	RADEONTRACE(("DRI New memory map param\n"));
-	memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
-	radeonsetparam.param = RADEON_SETPARAM_NEW_MEMMAP;
-	radeonsetparam.value = 1;
-	if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
-			    &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) {
+        if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
 		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 			   "[drm] failed to enable new memory map\n");
 		RADEONDRICloseScreen(pScreen);
 		info->directRenderingEnabled = FALSE;		
 	}
     }
+#endif
     RADEONTRACE(("Initializing fb layer\n"));
 
     /* Init fb layer */
@@ -4065,15 +4080,15 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
     if (info->directRenderingEnabled && info->cardType==CARD_PCIE &&
         info->pKernelDRMVersion->version_minor >= 19)
     {
-      drmRadeonSetParam  radeonsetparam;
-      RADEONTRACE(("DRI PCIGART param\n"));
-      memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
-      radeonsetparam.param = RADEON_SETPARAM_PCIGART_LOCATION;
-      radeonsetparam.value = info->pciGartOffset;
-      if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
-			  &radeonsetparam, sizeof(drmRadeonSetParam)) < 0)
+      if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0)
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		   "[drm] failed set pci gart location\n");
+
+      if (info->pKernelDRMVersion->version_minor >= 26) {
+	if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->pciGartSize) < 0)
+	  xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+		     "[drm] failed set pci gart table size\n");
+      }
     }
     if (info->directRenderingEnabled) {
         RADEONTRACE(("DRI Finishing init !\n"));
@@ -4094,14 +4109,9 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 
 	/* we might already be in tiled mode, tell drm about it */
 	if (info->directRenderingEnabled && info->tilingEnabled) {
-	    drmRadeonSetParam  radeonsetparam;
-	    memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
-	    radeonsetparam.param = RADEON_SETPARAM_SWITCH_TILING;
-	    radeonsetparam.value = info->tilingEnabled ? 1 : 0; 
-	    if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
-		&radeonsetparam, sizeof(drmRadeonSetParam)) < 0)
-		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-		    "[drm] failed changing tiling status\n");
+	  if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+  	      xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+			 "[drm] failed changing tiling status\n");
 	}
     } else {
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 
@@ -6542,14 +6552,9 @@ _X_EXPORT Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
 #ifdef XF86DRI	
 	if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
 	    RADEONSAREAPrivPtr pSAREAPriv;
-	    drmRadeonSetParam  radeonsetparam;
-	    memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
-	    radeonsetparam.param = RADEON_SETPARAM_SWITCH_TILING;
-	    radeonsetparam.value = info->tilingEnabled ? 1 : 0;
-	    if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
-		&radeonsetparam, sizeof(drmRadeonSetParam)) < 0)
-		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-		    "[drm] failed changing tiling status\n");
+	  if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
+  	      xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+			 "[drm] failed changing tiling status\n");
 	    pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
 	    info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
 	}
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 8dd13f2..f9bcace 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -430,7 +430,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
 	if (info->cardType==CARD_PCIE)
 	  xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		     "Will use %d kb for PCI GART at offset 0x%08x\n",
-		     RADEON_PCIGART_TABLE_SIZE / 1024,
+		     info->pciGartSize / 1024,
 		     (int)info->pciGartOffset);
 
 	/* Reserve a static area for the back buffer the same size as the