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authorRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-01-26 18:23:41 +0000
committerRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-01-26 18:23:41 +0000
commita2b123f7672ea678290798786ecb408a86d8c683 (patch)
treeb3ee76a2664b7156875b5abb4891d0499e56994a /man
parente0df1e41724cd009fe7c833d2f9555f5d87e3202 (diff)
(Stephane Marchesin, me) Add support for color (framebuffer) tiling.
Convert all XAA accel code to use explicit dst and src offset pitch control to make it work. Use the new drm surface ioctls to set up the tiled surfaces (if dri is enabled).
Diffstat (limited to 'man')
-rw-r--r--man/radeon.man14
1 files changed, 14 insertions, 0 deletions
diff --git a/man/radeon.man b/man/radeon.man
index 82fb1ce..e7c34ff 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -407,6 +407,20 @@ For example, Option "MergedDPI" "100 100"
.br
The default value is
.B undefined.
+.TP
+.BI "Option \*qEnableColorTiling\*q \*q" "boolean" \*q
+Frame buffer can be addressed either in linear or tiled mode. Tiled mode can provide
+significant performance benefits with 3D applications, for 2D it shouldn't matter
+much. Tiling will be disabled if the virtual x resolution exceeds 2048, if option
+.B UseFBDev
+is used, or (if DRI is enabled) the drm module is too old.
+.br
+If this option is enabled, a new dri driver is required for direct rendering too.
+.br
+Color tiling will be automatically disabled in interlaced or doublescan screen modes.
+.br
+The default value is
+.B on.
.TP
.BI "Option \*qIgnoreEDID\*q \*q" boolean \*q
Do not use EDID data for mode validation, but DDC is still used