diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2006-02-15 23:36:55 +0000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2006-02-15 23:36:55 +0000 |
| commit | 8c6e5a6eb50d371fd4ec700c26aa628cb5f45731 (patch) | |
| tree | 7900c2d5bb580e02a27994c77a8bd6107cbd5375 /src/radeon_accel.c | |
| parent | d4ec0223029d8fe03a836a5a6e9a7cc8897b4c90 (diff) | |
The engine setup would trigger a bogus line write before the proper
addresses are setup, thus causing the card to try to bus master over
the system bus to some stale location (usually 0 but could depend on
whatever was used before X). Remove that useless init bit, and always
setup some good enough engine source & destination pointers in case we
have some other spurrious engine activity going on.
Diffstat (limited to 'src/radeon_accel.c')
| -rw-r--r-- | src/radeon_accel.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 1503298..0e0ede9 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -292,19 +292,19 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int pitch64; RADEONTRACE(("EngineRestore (%d/%d)\n", info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel)); - RADEONWaitForFifo(pScrn, 1); - - pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; - -/* RADEONWaitForFifo(pScrn, 2); + /* Setup engine location. This shouldn't be necessary since we + * set them appropriately before any accel ops, but let's avoid + * random bogus DMA in case we inadvertently trigger the engine + * in the wrong place (happened). + */ + RADEONWaitForFifo(pScrn, 2); OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset); - OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset);*/ + OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset); RADEONWaitForFifo(pScrn, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -326,9 +326,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) | RADEON_GMC_BRUSH_SOLID_COLOR | RADEON_GMC_SRC_DATATYPE_COLOR)); - RADEONWaitForFifo(pScrn, 7); - OUTREG(RADEON_DST_LINE_START, 0); - OUTREG(RADEON_DST_LINE_END, 0); + RADEONWaitForFifo(pScrn, 5); OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); |