diff options
author | Alex Deucher <alex@botch2.(none)> | 2007-08-26 18:07:50 -0400 |
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committer | Alex Deucher <alex@botch2.(none)> | 2007-08-26 18:07:50 -0400 |
commit | d43596e5f5d7c60f96b57bc3e743a9b40eb7109d (patch) | |
tree | b5774acbb83054731ddb8dc5351790ad1a17124b /src/radeon_crtc.c | |
parent | 47eb3327c258bb0cfd9a1d5677624b9988a39057 (diff) |
RADEON: Fix rotation. works now
Diffstat (limited to 'src/radeon_crtc.c')
-rw-r--r-- | src/radeon_crtc.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 026cd8a..e976e2c 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -188,7 +188,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, #endif save->crtc_offset_cntl = 0; - if (info->tilingEnabled) { + if (info->tilingEnabled && (crtc->rotatedData == NULL)) { if (IS_R300_VARIANT) save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | R300_CRTC_MICRO_TILE_BUFFER_DIS | @@ -207,7 +207,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, Base = pScrn->fbOffset; - if (info->tilingEnabled) { + if (info->tilingEnabled && (crtc->rotatedData == NULL)) { if (IS_R300_VARIANT) { /* On r300/r400 when tiling is enabled crtc_offset is set to the address of * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc @@ -249,6 +249,10 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, Base += offset; } + if (crtc->rotatedData != NULL) { + Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; + } + Base &= ~7; /* 3 lower bits are always 0 */ @@ -419,7 +423,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, #endif save->crtc2_offset_cntl = 0; - if (info->tilingEnabled) { + if (info->tilingEnabled && (crtc->rotatedData == NULL)) { if (IS_R300_VARIANT) save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | R300_CRTC_MICRO_TILE_BUFFER_DIS | @@ -438,7 +442,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, Base = pScrn->fbOffset; - if (info->tilingEnabled) { + if (info->tilingEnabled && (crtc->rotatedData == NULL)) { if (IS_R300_VARIANT) { /* On r300/r400 when tiling is enabled crtc_offset is set to the address of * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc @@ -480,6 +484,10 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, Base += offset; } + if (crtc->rotatedData != NULL) { + Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; + } + Base &= ~7; /* 3 lower bits are always 0 */ #ifdef XF86DRI @@ -560,7 +568,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, ? RADEON_CRTC2_V_SYNC_POL : 0)); - save->crtc2_pitch = ((info->CurrentLayout.displayWidth * pScrn->bitsPerPixel) + + save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); save->crtc2_pitch |= save->crtc2_pitch << 16; |