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authorDave Airlie <airlied@linux.ie>2006-09-22 06:35:34 +1000
committerDave Airlie <airlied@linux.ie>2006-09-22 06:35:34 +1000
commitd7fc79fd9f094ac462de0883af7e6030cb6195a6 (patch)
treee336dd561cb633c7b519d356925c54c7628378f9 /src/radeon_display.c
parent4a54886d510f26b29d27e5c9a73647554291b1a6 (diff)
radeon: add enable display function
Diffstat (limited to 'src/radeon_display.c')
-rw-r--r--src/radeon_display.c110
1 files changed, 110 insertions, 0 deletions
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 250b543..c660831 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -1348,6 +1348,116 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
}
}
+/* This is to be used enable/disable displays dynamically */
+void RADEONEnableDisplay(ScrnInfoPtr pScrn, RADEONController* pCRTC, BOOL bEnable)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONSavePtr save = &info->ModeReg;
+ unsigned char * RADEONMMIO = info->MMIO;
+ unsigned long tmp;
+
+ if (bEnable) {
+ if (pCRTC->pPort->MonType == MT_CRT) {
+ if (pCRTC->pPort->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp |= RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ } else if (pCRTC->pPort->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp |= RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ } else {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ }
+ }
+ RADEONDacPowerSet(pScrn, bEnable, (pCRTC->pPort->DACType == DAC_PRIMARY));
+ } else if (pCRTC->pPort->MonType == MT_DFP) {
+ if (pCRTC->pPort->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (pCRTC->pPort->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ }
+ } else if (pCRTC->pPort->MonType == MT_LCD) {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
+ usleep (info->PanelPwrDly * 1000);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+ }
+ } else {
+ if (pCRTC->pPort->MonType == MT_CRT || pCRTC->pPort->MonType == NONE) {
+ if (pCRTC->pPort->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ } else if (pCRTC->pPort->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ }
+ }
+ RADEONDacPowerSet(pScrn, bEnable, (pCRTC->pPort->DACType == DAC_PRIMARY));
+ }
+
+ if (pCRTC->pPort->MonType == MT_DFP || pCRTC->pPort->MonType == NONE) {
+ if (pCRTC->pPort->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (pCRTC->pPort->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ }
+ }
+
+ if (pCRTC->pPort->MonType == MT_LCD ||
+ (pCRTC->pPort->MonType == NONE && pCRTC->pPort->ConnectorType == CONNECTOR_PROPRIETARY)) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS);
+ tmp &= ~(RADEON_LVDS_BLON);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
+ }
+ }
+ pCRTC->IsActive = bEnable;
+}
+
/* Calculate display buffer watermark to prevent buffer underflow */
void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
{