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authorEric Anholt <anholt@freebsd.org>2004-06-16 09:25:58 +0000
committerEric Anholt <anholt@freebsd.org>2004-06-16 09:25:58 +0000
commitbea8085e04136b0ef513c17bb65c54069ec531e1 (patch)
tree8f9c7a4da5c6b8bb7db35eb8928d035d787157a0 /src/radeon_driver.c
parent7b588cda922992a8ee2d04853ba1533cf43592a3 (diff)
DRI trunk-20040613 importDRI-trunk-20040613
Diffstat (limited to 'src/radeon_driver.c')
-rw-r--r--src/radeon_driver.c2046
1 files changed, 1450 insertions, 596 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4f56827..bfc50c4 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -56,15 +56,19 @@
* overlay planes
*
* Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge.
+ *
+ * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com)
+ * based on the sis driver by Thomas Winischhofer.
+ *
*/
/* Driver data structures */
#include "radeon.h"
#include "radeon_macros.h"
-#include "radeon_pci.h"
#include "radeon_probe.h"
#include "radeon_reg.h"
#include "radeon_version.h"
+#include "radeon_mergedfb.h"
#ifdef XF86DRI
#define _XF86DRI_SERVER_
@@ -81,6 +85,7 @@
/* X and server generic header files */
#include "xf86.h"
#include "xf86_OSproc.h"
+#include "xf86PciInfo.h"
#include "xf86RAC.h"
#include "xf86Resources.h"
#include "xf86cmap.h"
@@ -93,6 +98,9 @@
#ifndef MAX
#define MAX(a,b) ((a)>(b)?(a):(b))
#endif
+#ifndef MIN
+#define MIN(a,b) ((a)>(b)?(b):(a))
+#endif
/* Forward definitions for driver functions */
static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen);
@@ -103,6 +111,14 @@ static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode,
int flags);
+static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
+
+static void RADEONGetMergedFBOptions(ScrnInfoPtr pScrn);
+static int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
+
+/* psuedo xinerama support */
+
+extern Bool RADEONnoPanoramiXExtension;
typedef enum {
OPTION_NOACCEL,
@@ -110,12 +126,13 @@ typedef enum {
OPTION_DAC_6BIT,
OPTION_DAC_8BIT,
#ifdef XF86DRI
- OPTION_IS_PCI,
+ OPTION_BUS_TYPE,
OPTION_CP_PIO,
OPTION_USEC_TIMEOUT,
OPTION_AGP_MODE,
OPTION_AGP_FW,
OPTION_GART_SIZE,
+ OPTION_GART_SIZE_OLD,
OPTION_RING_SIZE,
OPTION_BUFFER_SIZE,
OPTION_DEPTH_MOVE,
@@ -126,12 +143,18 @@ typedef enum {
OPTION_DDC_MODE,
OPTION_MONITOR_LAYOUT,
OPTION_IGNORE_EDID,
- OPTION_CRTC2_OVERLAY,
- OPTION_CLONE_MODE,
- OPTION_CLONE_HSYNC,
- OPTION_CLONE_VREFRESH,
OPTION_FBDEV,
- OPTION_VIDEO_KEY
+ OPTION_VIDEO_KEY,
+ OPTION_MERGEDFB,
+ OPTION_CRT2HSYNC,
+ OPTION_CRT2VREFRESH,
+ OPTION_CRT2POS,
+ OPTION_METAMODES,
+ OPTION_MERGEDDPI,
+ OPTION_NORADEONXINERAMA,
+ OPTION_CRT2ISSCRN0,
+ OPTION_DISP_PRIORITY,
+ OPTION_PANEL_SIZE
} RADEONOpts;
const OptionInfoRec RADEONOptions[] = {
@@ -140,11 +163,12 @@ const OptionInfoRec RADEONOptions[] = {
{ OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE },
#ifdef XF86DRI
- { OPTION_IS_PCI, "ForcePCIMode", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE },
{ OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE },
{ OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE },
{ OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE },
{ OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE },
{ OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE },
@@ -156,21 +180,21 @@ const OptionInfoRec RADEONOptions[] = {
{ OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_MONITOR_LAYOUT, "MonitorLayout", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_CRTC2_OVERLAY , "OverlayOnCRTC2", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_CLONE_MODE, "CloneMode", OPTV_ANYSTR, {0}, FALSE },
- { OPTION_CLONE_HSYNC, "CloneHSync", OPTV_ANYSTR, {0}, FALSE },
- { OPTION_CLONE_VREFRESH, "CloneVRefresh", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
+ { OPTION_MERGEDFB, "MergedFB", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_CRT2HSYNC, "CRT2HSync", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_CRT2VREFRESH, "CRT2VRefresh", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_CRT2POS, "CRT2Position", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_METAMODES, "MetaModes", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_MERGEDDPI, "MergedDPI", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_NORADEONXINERAMA, "NoMergedXinerama", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_CRT2ISSCRN0, "MergedXineramaCRT2IsScreen0", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
-RADEONRAMRec RADEONRAM[] = { /* Memory Specifications
- From Radeon Manual */
- { 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SDRAM" },
- { 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SDRAM" },
-};
-
static const char *vgahwSymbols[] = {
"vgaHWFreeHWRec",
"vgaHWGetHWRec",
@@ -302,6 +326,7 @@ static const char *driSymbols[] = {
"DRIScreenInit",
"DRIUnlock",
"GlxSetVisualConfigs",
+ "DRICreatePCIBusID",
NULL
};
@@ -381,6 +406,24 @@ static struct
{720, 400, 70},
};
+static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] =
+{
+ {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_UNKNOW*/
+ {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_LEGACY*/
+ {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RADEON*/
+ {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV100*/
+ {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS100*/
+ {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV200*/
+ {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS200*/
+ {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/
+ {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/
+ {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/
+ {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x400f7/*0x40111*/}, {0, 0}}, /*CHIP_FAMILY_RV280*/
+ {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/
+ {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/
+ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/
+};
+
extern int gRADEONEntityIndex;
struct RADEONInt10Save {
@@ -448,15 +491,15 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
(((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) {
/* Restore the saved registers */
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring MEM_CNTL (%08x), setting to %08x\n",
- CardTmp, pSave->MEM_CNTL);
+ "Restoring MEM_CNTL (%08lx), setting to %08lx\n",
+ (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL);
OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL);
CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
if (CardTmp != pSave->MEMSIZE) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring CONFIG_MEMSIZE (%08x), setting to %08x\n",
- CardTmp, pSave->MEMSIZE);
+ "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n",
+ (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE);
OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE);
}
}
@@ -464,8 +507,9 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
CardTmp = INREG(RADEON_MPP_TB_CONFIG);
if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring MPP_TB_CONFIG<31:24> (%02x), setting to %02x\n",
- CardTmp >> 24, pSave->MPP_TB_CONFIG >> 24);
+ "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n",
+ (unsigned long)CardTmp >> 24,
+ (unsigned long)pSave->MPP_TB_CONFIG >> 24);
CardTmp &= 0x00ffffffu;
CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u);
OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
@@ -484,6 +528,48 @@ static Bool RADEONGetRec(ScrnInfoPtr pScrn)
/* Free our private RADEONInfoRec */
static void RADEONFreeRec(ScrnInfoPtr pScrn)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ if(info->CRT2HSync) xfree(info->CRT2HSync);
+ info->CRT2HSync = NULL;
+ if(info->CRT2VRefresh) xfree(info->CRT2VRefresh);
+ info->CRT2VRefresh = NULL;
+ if(info->MetaModes) xfree(info->MetaModes);
+ info->MetaModes = NULL;
+ if(info->CRT2pScrn) {
+ if(info->CRT2pScrn->modes) {
+ while(info->CRT2pScrn->modes)
+ xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes);
+ }
+ if(info->CRT2pScrn->monitor) {
+ if(info->CRT2pScrn->monitor->Modes) {
+ while(info->CRT2pScrn->monitor->Modes)
+ xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes);
+ }
+ if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC);
+ xfree(info->CRT2pScrn->monitor);
+ }
+ xfree(info->CRT2pScrn);
+ info->CRT2pScrn = NULL;
+ }
+ if(info->CRT1Modes) {
+ if(info->CRT1Modes != pScrn->modes) {
+ if(pScrn->modes) {
+ pScrn->currentMode = pScrn->modes;
+ do {
+ DisplayModePtr p = pScrn->currentMode->next;
+ if(pScrn->currentMode->Private)
+ xfree(pScrn->currentMode->Private);
+ xfree(pScrn->currentMode);
+ pScrn->currentMode = p;
+ } while(pScrn->currentMode != pScrn->modes);
+ }
+ pScrn->currentMode = info->CRT1CurrentMode;
+ pScrn->modes = info->CRT1Modes;
+ info->CRT1CurrentMode = NULL;
+ info->CRT1Modes = NULL;
+ }
+ }
+
if (!pScrn || !pScrn->driverPrivate) return;
xfree(pScrn->driverPrivate);
pScrn->driverPrivate = NULL;
@@ -673,7 +759,7 @@ static void RADEONBlank(ScrnInfoPtr pScrn)
default:
break;
}
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL,
RADEON_CRTC2_DISP_DIS,
~(RADEON_CRTC2_DISP_DIS));
@@ -704,7 +790,7 @@ static void RADEONUnblank(ScrnInfoPtr pScrn)
default:
break;
}
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL,
0,
~(RADEON_CRTC2_DISP_DIS));
@@ -785,7 +871,7 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT
OUTREG(info->DDCReg,
INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < 10; i++) {
usleep(15000);
if (INREG(info->DDCReg) & RADEON_GPIO_Y_1)
break;
@@ -1301,19 +1387,6 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
if (!pRADEONEnt->MonType2)
pRADEONEnt->MonType2 = RADEONCrtIsPhysicallyConnected(pScrn, !pRADEONEnt->ReversedDAC);
- /* no display detected on DVI port*/
- if (pRADEONEnt->MonType1 == MT_NONE) {
- if (pRADEONEnt->MonType2 != MT_NONE) {
- /* Only one detected on VGA, let it to be primary */
- pRADEONEnt->MonType1 = pRADEONEnt->MonType2;
- pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2;
- pRADEONEnt->MonType2 = MT_NONE;
- } else {
- /* Non detected, Default to a CRT connected */
- pRADEONEnt->MonType1 = MT_CRT;
- }
- }
-
if(pRADEONEnt->ReversedTMDS) {
/* always keep internal TMDS as primary head */
if (pRADEONEnt->MonType1 == MT_DFP ||
@@ -1330,6 +1403,20 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
}
}
}
+
+ /* no display detected on DVI port*/
+ if (pRADEONEnt->MonType1 == MT_NONE) {
+ if (pRADEONEnt->MonType2 != MT_NONE) {
+ /* Only one detected on VGA, let it to be primary */
+ pRADEONEnt->MonType1 = pRADEONEnt->MonType2;
+ pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2;
+ pRADEONEnt->MonType2 = MT_NONE;
+ pRADEONEnt->MonInfo2 = NULL;
+ } else {
+ /* Non detected, Default to a CRT connected */
+ pRADEONEnt->MonType1 = MT_CRT;
+ }
+ }
}
if(s) {
@@ -1363,9 +1450,6 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n");
info->OverlayOnCRTC2 = FALSE;
- if (xf86ReturnOptValBool(info->Options, OPTION_CRTC2_OVERLAY, FALSE)) {
- info->OverlayOnCRTC2 = TRUE;
- }
if (pRADEONEnt->MonType2 == MT_NONE)
pRADEONEnt->HasSecondary = FALSE;
@@ -1421,8 +1505,8 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONMMIO = info->MMIO;
- info->Clone = FALSE;
- info->CloneType = MT_NONE;
+ /* info->MergedFB = FALSE; */
+ info->MergeType = MT_NONE;
if(info->HasCRTC2) {
if(info->IsSecondary) {
@@ -1431,8 +1515,9 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->DisplayType = pRADEONEnt->MonType1;
if(!pRADEONEnt->HasSecondary) {
- if ((info->CloneType = pRADEONEnt->MonType2))
- info->Clone = TRUE;
+ if ((info->MergeType = pRADEONEnt->MonType2)) {
+ /* info->MergedFB = TRUE; */
+ }
}
}
} else {
@@ -1443,9 +1528,9 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
(info->IsSecondary ? "Secondary" : "Primary"),
info->DisplayType);
- if (info->Clone)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone Display == Type %d\n",
- info->CloneType);
+ if (info->MergedFB)
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Secondary Display == Type %d\n",
+ info->MergeType);
info->HBlank = 0;
info->HOverPlus = 0;
@@ -1456,7 +1541,8 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->DotClock = 0;
info->UseBiosDividers = FALSE;
- if (info->DisplayType == MT_LCD && info->VBIOS) {
+ if (info->DisplayType == MT_LCD && info->VBIOS &&
+ !(xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) {
tmp = RADEON_BIOS16(info->FPBIOSstart + 0x40);
if (!tmp) {
info->PanelPwrDly = 200;
@@ -1491,10 +1577,14 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
(info->FeedbackDivider > 3)) {
info->UseBiosDividers = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS provided dividers will be used.");
+ "BIOS provided dividers will be used.\n");
}
- for (i = 0; i < 20; i++) {
+ /* We don't use a while loop here just in case we have a corrupted BIOS image.
+ The max number of table entries is 23 at present, but may grow in future.
+ To ensure it works with future revisions we loop it to 32.
+ */
+ for (i = 0; i < 32; i++) {
tmp0 = RADEON_BIOS16(tmp+64+i*2);
if (tmp0 == 0) break;
if ((RADEON_BIOS16(tmp0) == info->PanelXRes) &&
@@ -1513,9 +1603,60 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->Flags = 0;
}
}
+
+ if (info->DotClock == 0) {
+ DisplayModePtr tmp_mode = NULL;
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "No valid timing info from BIOS.\n");
+ /* No timing information for the native mode,
+ use whatever specified in the Modeline.
+ If no Modeline specified, we'll just pick
+ the VESA mode at 60Hz refresh rate which
+ is likely to be the best for a flat panel.
+ */
+ tmp_mode = pScrn->monitor->Modes;
+ while(tmp_mode) {
+ if ((tmp_mode->HDisplay == info->PanelXRes) &&
+ (tmp_mode->VDisplay == info->PanelYRes)) {
+
+ float refresh =
+ (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal;
+ if ((abs(60.0 - refresh) < 1.0) ||
+ (tmp_mode->type == 0)) {
+ info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay;
+ info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay;
+ info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart;
+ info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay;
+ info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay;
+ info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart;
+ info->DotClock = tmp_mode->Clock;
+ info->Flags = 0;
+ break;
+ }
+ tmp_mode = tmp_mode->next;
+ }
+ }
+ if ((info->DotClock == 0) && !pRADEONEnt->MonInfo1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Panel size is not correctly detected.\n"
+ "Please try to use PanelSize option for correct settings.\n");
+ return FALSE;
+ }
+ }
}
}
}
+
+ if (info->VBIOS) {
+ tmp = RADEON_BIOS16(info->FPBIOSstart + 0x30);
+ info->sclk = RADEON_BIOS16(tmp + 8) / 100.0;
+ info->mclk = RADEON_BIOS16(tmp + 10) / 100.0;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No valid info for SCLK/MCLK for display bandwidth calculation.\n");
+ info->sclk = 200.00;
+ info->mclk = 200.00;
+ }
+
return TRUE;
}
@@ -1633,6 +1774,56 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
return TRUE;
}
+static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ CARD32 tmp;
+ int i, n;
+
+ for (i=0; i<4; i++) {
+ info->tmds_pll[i].value = 0;
+ info->tmds_pll[i].freq = 0;
+ }
+
+ if (info->VBIOS) {
+ tmp = RADEON_BIOS16(info->FPBIOSstart + 0x34);
+ if (tmp) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DFP table revision: %d\n", RADEON_BIOS8(tmp));
+ if (RADEON_BIOS8(tmp) == 3) {
+ n = RADEON_BIOS8(tmp + 5) + 1;
+ if (n > 4) n = 4;
+ for (i=0; i<n; i++) {
+ info->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08);
+ info->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10);
+ }
+ return;
+ }
+
+ /* revision 4 has some problem as it appears in RV280,
+ comment it off for new, use default instead */
+ /*
+ else if (RADEON_BIOS8(tmp) == 4) {
+ int stride = 0;
+ n = RADEON_BIOS8(tmp + 5) + 1;
+ if (n > 4) n = 4;
+ for (i=0; i<n; i++) {
+ info->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08);
+ info->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10);
+ if (i == 0) stride += 10;
+ else stride += 6;
+ }
+ return;
+ }
+ */
+ }
+ }
+
+ for (i=0; i<4; i++) {
+ info->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value;
+ info->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq;
+ }
+}
/* Read PLL parameters from BIOS block. Default to typical values if
* there is no BIOS.
@@ -1658,7 +1849,6 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn)
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QN:
case PCI_CHIP_R200_QO:
- case PCI_CHIP_R200_Ql:
case PCI_CHIP_R200_BB:
pll->reference_freq = 2700;
pll->reference_div = 12;
@@ -1789,6 +1979,99 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
return TRUE;
}
+/* Set up MC_FB_LOCATION and related registers */
+static void
+RADEONSetFBLocation(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 mc_fb_location;
+ CARD32 mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
+
+ if (info->IsIGP) {
+ mc_fb_location = INREG(RADEON_NB_TOM);
+
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL,
+ INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000);
+
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200)) {
+ /* This is to workaround the asic bug for RMX, some versions
+ of BIOS don't have this register initialized correctly.
+ */
+ OUTREGP(RADEON_CRTC_MORE_CNTL, RADEON_CRTC_H_CUTOFF_ACTIVE_EN,
+ ~RADEON_CRTC_H_CUTOFF_ACTIVE_EN);
+ }
+ } else
+#ifdef XF86DRI
+ if ( info->directRenderingEnabled && info->drmMinor < 10 ) {
+ mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U;
+ } else
+#endif
+ {
+ CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
+
+ mc_fb_location = (aper0_base >> 16)
+ | ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1)
+ ) & 0xffff0000U);
+ }
+
+ info->fbLocation = (mc_fb_location & 0xffff) << 16;
+
+ if (((mc_agp_location & 0xffff) << 16) !=
+ ((mc_fb_location & 0xffff0000U) + 0x10000)) {
+ mc_agp_location = mc_fb_location & 0xffff0000U;
+ mc_agp_location |= (mc_agp_location + 0x10000) >> 16;
+ }
+
+ RADEONWaitForIdleMMIO(pScrn);
+
+ OUTREG(RADEON_MC_FB_LOCATION, mc_fb_location);
+ OUTREG(RADEON_MC_AGP_LOCATION, mc_agp_location);
+ OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
+ if (info->HasCRTC2)
+ OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
+ OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
+}
+
+static void RADEONGetVRamType(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 tmp;
+
+ if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
+ (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
+ info->IsDDR = TRUE;
+ else
+ info->IsDDR = FALSE;
+
+ tmp = INREG(RADEON_MEM_CNTL);
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
+ tmp &= R300_MEM_NUM_CHANNELS_MASK;
+ switch (tmp) {
+ case 0: info->RamWidth = 64; break;
+ case 1: info->RamWidth = 128; break;
+ case 2: info->RamWidth = 256; break;
+ default: info->RamWidth = 128; break;
+ }
+ } else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200)){
+ if (tmp & RV100_HALF_MODE) info->RamWidth = 32;
+ else info->RamWidth = 64;
+ } else {
+ if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128;
+ else info->RamWidth = 64;
+ }
+
+ /* This may not be correct, as some cards can have half of channel disabled
+ * ToDo: identify these cases
+ */
+}
+
/* This is called by RADEONPreInit to handle config file overrides for
* things like chipset and memory regions. Also determine memory size
* and type. If memory type ever needs an override, put it in this
@@ -1799,9 +2082,11 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
EntityInfoPtr pEnt = info->pEnt;
GDevPtr dev = pEnt->device;
- int offset = 0; /* RAM Type */
MessageType from;
unsigned char *RADEONMMIO = info->MMIO;
+#ifdef XF86DRI
+ const char *s;
+#endif
/* Chipset */
from = X_PROBED;
@@ -1868,45 +2153,27 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_R200_BB:
+ case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
- case PCI_CHIP_R200_QI:
- case PCI_CHIP_R200_QJ:
- case PCI_CHIP_R200_QK:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
- case PCI_CHIP_R200_QN:
- case PCI_CHIP_R200_QO:
- case PCI_CHIP_R200_Qh:
- case PCI_CHIP_R200_Qi:
- case PCI_CHIP_R200_Qj:
- case PCI_CHIP_R200_Qk:
- case PCI_CHIP_R200_Ql:
info->ChipFamily = CHIP_FAMILY_R200;
break;
- case PCI_CHIP_RV200_QW: /* RV200 desktop */
- case PCI_CHIP_RV200_QX:
- info->ChipFamily = CHIP_FAMILY_RV200;
- break;
-
case PCI_CHIP_RADEON_LW:
case PCI_CHIP_RADEON_LX:
info->IsMobility = TRUE;
+ case PCI_CHIP_RV200_QW: /* RV200 desktop */
+ case PCI_CHIP_RV200_QX:
info->ChipFamily = CHIP_FAMILY_RV200;
break;
- case PCI_CHIP_RV250_Id:
- case PCI_CHIP_RV250_Ie:
- case PCI_CHIP_RV250_If:
- case PCI_CHIP_RV250_Ig:
- info->ChipFamily = CHIP_FAMILY_RV250;
- break;
-
case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Le:
case PCI_CHIP_RV250_Lf:
case PCI_CHIP_RV250_Lg:
info->IsMobility = TRUE;
+ case PCI_CHIP_RV250_If:
+ case PCI_CHIP_RV250_Ig:
info->ChipFamily = CHIP_FAMILY_RV250;
break;
@@ -1917,18 +2184,13 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
info->IsIGP = TRUE;
break;
+ case PCI_CHIP_RV280_5C61:
+ case PCI_CHIP_RV280_5C63:
+ info->IsMobility = TRUE;
case PCI_CHIP_RV280_5960:
case PCI_CHIP_RV280_5961:
case PCI_CHIP_RV280_5962:
- case PCI_CHIP_RV280_5963:
- info->ChipFamily = CHIP_FAMILY_RV280;
- break;
-
- case PCI_CHIP_RV280_5968:
- case PCI_CHIP_RV280_5969:
- case PCI_CHIP_RV280_596A:
- case PCI_CHIP_RV280_596B:
- info->IsMobility = TRUE;
+ case PCI_CHIP_RV280_5964:
info->ChipFamily = CHIP_FAMILY_RV280;
break;
@@ -1944,15 +2206,29 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_RV350_NP:
+ case PCI_CHIP_RV350_NQ:
+ case PCI_CHIP_RV350_NR:
+ case PCI_CHIP_RV350_NS:
+ case PCI_CHIP_RV350_NT:
+ case PCI_CHIP_RV350_NV:
info->IsMobility = TRUE;
case PCI_CHIP_RV350_AP:
- case PCI_CHIP_RV350_AR:
+ case PCI_CHIP_RV350_AQ:
+ case PCI_CHIP_RV360_AR:
+ case PCI_CHIP_RV350_AS:
+ case PCI_CHIP_RV350_AT:
+ case PCI_CHIP_RV350_AV:
info->ChipFamily = CHIP_FAMILY_RV350;
break;
+ case PCI_CHIP_R350_AH:
+ case PCI_CHIP_R350_AI:
+ case PCI_CHIP_R350_AJ:
case PCI_CHIP_R350_AK:
case PCI_CHIP_R350_NH:
+ case PCI_CHIP_R350_NI:
case PCI_CHIP_R350_NK:
+ case PCI_CHIP_R360_NJ:
info->ChipFamily = CHIP_FAMILY_R350;
break;
@@ -1969,7 +2245,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
pScrn->memPhysBase = info->LinearAddr;
if (dev->MemBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Linear address override, using 0x%08x instead of 0x%08x\n",
+ "Linear address override, using 0x%08lx instead of 0x%08lx\n",
dev->MemBase,
info->LinearAddr);
info->LinearAddr = dev->MemBase;
@@ -1987,7 +2263,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000;
if (dev->BiosBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS address override, using 0x%08x instead of 0x%08x\n",
+ "BIOS address override, using 0x%08lx instead of 0x%08lx\n",
dev->BiosBase,
info->BIOSAddr);
info->BIOSAddr = dev->BiosBase;
@@ -2002,34 +2278,18 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
from = X_PROBED;
if (info->FBDev)
pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
- else if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ else if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200) ||
(info->ChipFamily == CHIP_FAMILY_RS300)) {
CARD32 tom = INREG(RADEON_NB_TOM);
- pScrn->videoRam = (((tom >> 16) -
- (tom & 0xffff) + 1) << 6);
- OUTREG(RADEON_MC_FB_LOCATION, tom);
- OUTREG(RADEON_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
- OUTREG(RADEON_DISPLAY2_BASE_ADDR, (tom & 0xffff) << 16);
- OUTREG(RADEON_OV0_BASE_ADDR, (tom & 0xffff) << 16);
- /* This is supposed to fix the crtc2 noise problem.
- */
- OUTREG(RADEON_GRPH2_BUFFER_CNTL,
- INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000);
-
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)) {
- /* This is to workaround the asic bug for RMX, some versions
- of BIOS dosen't have this register initialized correctly.
- */
- OUTREGP(RADEON_CRTC_MORE_CNTL, RADEON_CRTC_H_CUTOFF_ACTIVE_EN,
- ~RADEON_CRTC_H_CUTOFF_ACTIVE_EN);
- }
+ pScrn->videoRam = (((tom >> 16) -
+ (tom & 0xffff) + 1) << 6);
- }
- else
+ OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
+ } else {
pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
+ }
/* Some production boards of m6 will return 0 if it's 8 MB */
if (pScrn->videoRam == 0) pScrn->videoRam = 8192;
@@ -2046,8 +2306,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
info1 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
info1->FbMapSize = pScrn->videoRam * 1024;
info->LinearAddr += pScrn->videoRam * 1024;
- info1->Clone = FALSE;
- info1->CurCloneMode = NULL;
+ info1->MergedFB = FALSE;
}
info->R300CGWorkaround =
@@ -2058,13 +2317,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
info->BusCntl = INREG(RADEON_BUS_CNTL);
- /* RAM */
- switch (info->MemCntl >> 30) {
- case 0: offset = 0; break; /* 64-bit SDR SDRAM */
- case 1: offset = 1; break; /* 64-bit DDR SDRAM */
- default: offset = 0;
- }
- info->ram = &RADEONRAM[offset];
+ RADEONGetVRamType(pScrn);
if (dev->videoRam) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -2077,71 +2330,44 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
pScrn->videoRam &= ~1023;
info->FbMapSize = pScrn->videoRam * 1024;
xf86DrvMsg(pScrn->scrnIndex, from,
- "VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name);
+ "VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR");
#ifdef XF86DRI
/* AGP/PCI */
- if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) {
- info->IsPCI = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI-only mode\n");
- } else {
- switch (info->Chipset) {
-#if 0
- case PCI_CHIP_RADEON_XX: info->IsPCI = TRUE; break;
-#endif
- case PCI_CHIP_RV100_QY:
- case PCI_CHIP_RV100_QZ:
- case PCI_CHIP_RADEON_LW:
- case PCI_CHIP_RADEON_LX:
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- case PCI_CHIP_RADEON_QD:
- case PCI_CHIP_RADEON_QE:
- case PCI_CHIP_RADEON_QF:
- case PCI_CHIP_RADEON_QG:
- case PCI_CHIP_R200_BB:
- case PCI_CHIP_R200_QH:
- case PCI_CHIP_R200_QI:
- case PCI_CHIP_R200_QJ:
- case PCI_CHIP_R200_QK:
- case PCI_CHIP_R200_QL:
- case PCI_CHIP_R200_QM:
- case PCI_CHIP_R200_QN:
- case PCI_CHIP_R200_QO:
- case PCI_CHIP_R200_Qh:
- case PCI_CHIP_R200_Qi:
- case PCI_CHIP_R200_Qj:
- case PCI_CHIP_R200_Qk:
- case PCI_CHIP_R200_Ql:
- case PCI_CHIP_RV200_QW:
- case PCI_CHIP_RV200_QX:
- case PCI_CHIP_RV250_Id:
- case PCI_CHIP_RV250_Ie:
- case PCI_CHIP_RV250_If:
- case PCI_CHIP_RV250_Ig:
- case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Le:
- case PCI_CHIP_RV250_Lf:
- case PCI_CHIP_RV250_Lg:
- case PCI_CHIP_RV280_5960:
- case PCI_CHIP_RV280_5961:
- case PCI_CHIP_RV280_5962:
- case PCI_CHIP_RV280_5963:
- case PCI_CHIP_RV280_5968:
- case PCI_CHIP_RV280_5969:
- case PCI_CHIP_RV280_596A:
- case PCI_CHIP_RV280_596B:
- case PCI_CHIP_R300_AD:
- case PCI_CHIP_R300_AE:
- case PCI_CHIP_R300_AF:
- case PCI_CHIP_R300_AG:
- case PCI_CHIP_R300_ND:
- case PCI_CHIP_R300_NE:
- case PCI_CHIP_R300_NF:
- case PCI_CHIP_R300_NG:
- default: info->IsPCI = FALSE; break;
+ if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) {
+ if (strcmp(s, "AGP") == 0) {
+ info->IsPCI = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n");
+ } else if (strcmp(s, "PCI") == 0) {
+ info->IsPCI = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n");
+ } else if (strcmp(s, "PCIE") == 0) {
+ info->IsPCI = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "PCI Express not supported yet, use PCI mode\n");
+ } else {
+ s = NULL;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Invalid BusType option, use detected type\n");
}
}
+
+ if (!s) {
+ CARD32 tmp = pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG);
+ /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
+ Following detection method works for all cards tested so far.
+ Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
+ However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
+ restarts next time.
+ */
+ pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, tmp | RADEON_AGP_ENABLE);
+ if (pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG) & RADEON_AGP_ENABLE) {
+ info->IsPCI = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AGP card detected\n");
+ } else {
+ info->IsPCI = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PCI card detected\n");
+ }
+ pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, tmp);
+ }
#endif
return TRUE;
@@ -2172,6 +2398,9 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data)
val |= (Clock ? 0:RADEON_GPIO_EN_1);
val |= (data ? 0:RADEON_GPIO_EN_0);
OUTREG(info->DDCReg, val);
+
+ /* read back to improve reliability on some cards. */
+ val = INREG(info->DDCReg);
}
static Bool RADEONI2cInit(ScrnInfoPtr pScrn)
@@ -2480,25 +2709,29 @@ static DisplayModePtr RADEONDDCModes(ScrnInfoPtr pScrn)
/* XFree86's xf86ValidateModes routine doesn't work well with DDC modes,
* so here is our own validation routine.
*/
-static int RADEONValidateDDCModes(ScrnInfoPtr pScrn, char **ppModeName,
- RADEONMonitorType DisplayType)
+static int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
+ RADEONMonitorType DisplayType, int crtc2)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn1);
DisplayModePtr p;
DisplayModePtr last = NULL;
DisplayModePtr first = NULL;
DisplayModePtr ddcModes = NULL;
int count = 0;
int i, width, height;
+ ScrnInfoPtr pScrn = pScrn1;
- pScrn->virtualX = pScrn->display->virtualX;
- pScrn->virtualY = pScrn->display->virtualY;
+ if (crtc2)
+ pScrn = info->CRT2pScrn;
+
+ pScrn->virtualX = pScrn1->display->virtualX;
+ pScrn->virtualY = pScrn1->display->virtualY;
if (pScrn->monitor->DDC && !info->UseBiosDividers) {
int maxVirtX = pScrn->virtualX;
int maxVirtY = pScrn->virtualY;
- if ((DisplayType != MT_CRT) && !info->IsSecondary) {
+ if ((DisplayType != MT_CRT) && (!info->IsSecondary) && (!crtc2)) {
/* The panel size we collected from BIOS may not be the
* maximum size supported by the panel. If not, we update
* it now. These will be used if no matching mode can be
@@ -2514,7 +2747,7 @@ static int RADEONValidateDDCModes(ScrnInfoPtr pScrn, char **ppModeName,
/* If primary head is a flat panel, use RMX by default */
if ((!info->IsSecondary && DisplayType != MT_CRT) &&
- !info->ddc_mode) {
+ (!info->ddc_mode) && (!crtc2)) {
/* These values are effective values after expansion.
* They are not really used to set CRTC registers.
*/
@@ -2621,8 +2854,13 @@ static int RADEONValidateDDCModes(ScrnInfoPtr pScrn, char **ppModeName,
p->type |= M_T_USERDEF;
}
- pScrn->virtualX = pScrn->display->virtualX = maxVirtX;
- pScrn->virtualY = pScrn->display->virtualY = maxVirtY;
+ if (crtc2) {
+ pScrn->virtualX = maxVirtX;
+ pScrn->virtualY = maxVirtY;
+ } else {
+ pScrn->virtualX = pScrn->display->virtualX = maxVirtX;
+ pScrn->virtualY = pScrn->display->virtualY = maxVirtY;
+ }
}
/* Close the doubly-linked mode list, if we found any usable modes */
@@ -2680,7 +2918,7 @@ static DisplayModePtr RADEONFPNativeMode(ScrnInfoPtr pScrn)
pScrn->virtualY = MAX(pScrn->virtualY, info->PanelYRes);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "No valid mode specified, force to native mdoe\n");
+ "No valid mode specified, force to native mode\n");
}
return new;
@@ -2914,243 +3152,166 @@ static void RADEONSetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
}
}
-static int RADEONValidateCloneModes(ScrnInfoPtr pScrn)
+static int RADEONValidateMergeModes(ScrnInfoPtr pScrn1)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn1);
ClockRangePtr clockRanges;
- DisplayModePtr tmp_mode = NULL;
- DisplayModePtr clone_mode, save_mode;
- int modesFound = 0;
- int count = 0;
- int tmp_hdisplay = 0;
- int tmp_vdisplay = 0;
- int i, save_n_hsync, save_n_vrefresh;
- range save_hsync, save_vrefresh;
- char *s;
- char **clone_mode_names = NULL;
- Bool ddc_mode = info->ddc_mode;
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ int modesFound;
+ ScrnInfoPtr pScrn = info->CRT2pScrn;
- /* Save all infomations that will be changed by clone mode validateion */
- save_mode = pScrn->modes;
- pScrn->modes = NULL;
+ /* fill in pScrn2 */
+ pScrn->videoRam = pScrn1->videoRam;
+ pScrn->depth = pScrn1->depth;
+ pScrn->numClocks = pScrn1->numClocks;
+ pScrn->progClock = pScrn1->progClock;
+ pScrn->fbFormat = pScrn1->fbFormat;
+ pScrn->videoRam = pScrn1->videoRam;
+ pScrn->maxHValue = pScrn1->maxHValue;
+ pScrn->maxVValue = pScrn1->maxVValue;
+ pScrn->xInc = pScrn1->xInc;
- /* Clone display mode names, duplicate all mode names for primary
- * head. Allocate one more, in case pScrn->display->modes[0] ==
- * NULL */
- while (pScrn->display->modes[count]) count++;
- clone_mode_names = xnfalloc((count+2) * sizeof(char*));
- for (i = 0; i < count; i++) {
- clone_mode_names[i] = xnfalloc(strlen(pScrn->display->modes[i]) + 1);
- strcpy(clone_mode_names[i], pScrn->display->modes[i]);
+ if (info->NoVirtual) {
+ pScrn1->display->virtualX = 0;
+ pScrn1->display->virtualY = 0;
}
- clone_mode_names[count] = NULL;
- clone_mode_names[count+1] = NULL;
- pScrn->progClock = TRUE;
+ if (pScrn->monitor->DDC) {
+ /* If we still don't know sync range yet, let's try EDID.
+ *
+ * Note that, since we can have dual heads, Xconfigurator
+ * may not be able to probe both monitors correctly through
+ * vbe probe function (RADEONProbeDDC). Here we provide an
+ * additional way to auto-detect sync ranges if they haven't
+ * been added to XF86Config manually.
+ */
+ if (pScrn->monitor->nHsync <= 0)
+ RADEONSetSyncRangeFromEdid(pScrn, 1);
+ if (pScrn->monitor->nVrefresh <= 0)
+ RADEONSetSyncRangeFromEdid(pScrn, 0);
+ }
+ /* Get mode information */
+ pScrn->progClock = TRUE;
clockRanges = xnfcalloc(sizeof(*clockRanges), 1);
clockRanges->next = NULL;
clockRanges->minClock = info->pll.min_pll_freq;
clockRanges->maxClock = info->pll.max_pll_freq * 10;
clockRanges->clockIndex = -1;
- clockRanges->interlaceAllowed = (info->CloneType == MT_CRT);
- clockRanges->doubleScanAllowed = (info->CloneType == MT_CRT);
+ clockRanges->interlaceAllowed = (info->MergeType == MT_CRT);
+ clockRanges->doubleScanAllowed = (info->MergeType == MT_CRT);
- /* Only take one clone mode from config file for now, rest of clone
- * modes will copy from primary head.
+ /* We'll use our own mode validation routine for DFP/LCD, since
+ * xf86ValidateModes does not work correctly with the DFP/LCD modes
+ * 'stretched' from their native mode.
*/
- if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_MODE))) {
- if (sscanf(s, "%dx%d", &tmp_hdisplay, &tmp_vdisplay) == 2) {
- if(count > 0) free(clone_mode_names[0]);
- else count++;
- clone_mode_names[0] = xnfalloc(strlen(s)+1);
- sprintf(clone_mode_names[0], "%dx%d", tmp_hdisplay, tmp_vdisplay);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone mode %s in config file is used\n");
- }
- }
-
- for (i = 0; i < count; i++) {
- if (sscanf(clone_mode_names[i], "%dx%d",
- &tmp_hdisplay, &tmp_vdisplay) == 2) {
- if (pScrn->display->virtualX < tmp_hdisplay)
- pScrn->display->virtualX = tmp_hdisplay;
- if (pScrn->display->virtualY < tmp_vdisplay)
- pScrn->display->virtualY = tmp_vdisplay;
- }
- }
+ if (info->MergeType == MT_CRT && !info->ddc_mode) {
- save_hsync = pScrn->monitor->hsync[0];
- save_vrefresh = pScrn->monitor->vrefresh[0];
- save_n_hsync = pScrn->monitor->nHsync;
- save_n_vrefresh = pScrn->monitor->nVrefresh;
-
- pScrn->monitor->DDC = NULL;
- pScrn->monitor->nHsync = 0;
- pScrn->monitor->nVrefresh = 0;
+ modesFound =
+ xf86ValidateModes(pScrn,
+ pScrn->monitor->Modes,
+ pScrn1->display->modes,
+ clockRanges,
+ NULL, /* linePitches */
+ 8 * 64, /* minPitch */
+ 8 * 1024, /* maxPitch */
+ 64 * pScrn1->bitsPerPixel, /* pitchInc */
+ 128, /* minHeight */
+ 8 * 1024, /*2048,*/ /* maxHeight */
+ pScrn1->display->virtualX ? pScrn1->virtualX : 0,
+ pScrn1->display->virtualY ? pScrn1->virtualY : 0,
+ info->FbMapSize,
+ LOOKUP_BEST_REFRESH);
- if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_HSYNC))) {
- if (sscanf(s, "%f-%f", &pScrn->monitor->hsync[0].lo,
- &pScrn->monitor->hsync[0].hi) == 2) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "HSync for CloneMode from config file: %s\n", s);
- pScrn->monitor->nHsync = 1;
- } else {
- pScrn->monitor->nHsync = 0;
- }
- }
+ if (modesFound == -1) return 0;
- if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_VREFRESH))) {
- if (sscanf(s, "%f-%f", &pScrn->monitor->vrefresh[0].lo,
- &pScrn->monitor->vrefresh[0].hi) == 2) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "VRefresh for CloneMode from config file: %s\n", s);
- pScrn->monitor->nVrefresh = 1;
- } else {
- pScrn->monitor->nVrefresh = 0;
+ xf86PruneDriverModes(pScrn);
+ if (!modesFound || !pScrn->modes) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n");
+ return 0;
}
- }
-
- pScrn->monitor->DDC = pRADEONEnt->MonInfo2;
- if (pScrn->monitor->DDC) {
- if ((pScrn->monitor->nVrefresh == 0) || (pScrn->monitor->nHsync == 0)) {
- if (pScrn->monitor->nHsync == 0)
- RADEONSetSyncRangeFromEdid(pScrn, 1);
- if (pScrn->monitor->nVrefresh == 0)
- RADEONSetSyncRangeFromEdid(pScrn, 0);
- }
- } else if (info->ddc_mode) {
- ddc_mode = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "No DDC data available for clone mode, "
- "DDCMode option is dismissed\n");
- }
- if (info->CloneType == MT_CRT && !ddc_mode) {
- modesFound =
- xf86ValidateModes(pScrn, pScrn->monitor->Modes,
- clone_mode_names,
- clockRanges,
- NULL, /* linePitches */
- 8 * 64, /* minPitch */
- 8 * 1024, /* maxPitch */
- 64 * pScrn->bitsPerPixel, /* pitchInc */
- 128, /* minHeight */
- 2048, /* maxHeight */
- pScrn->display->virtualX,
- pScrn->display->virtualY,
- info->FbMapSize,
- LOOKUP_BEST_REFRESH);
} else {
- /* Try to add DDC modes */
- info->IsSecondary = TRUE; /*fake secondary head*/
- modesFound = RADEONValidateDDCModes(pScrn, clone_mode_names,
- info->CloneType);
- info->IsSecondary = FALSE;
+ /* First, free any allocated modes during configuration, since
+ * we don't need them
+ */
+ while (pScrn->modes)
+ xf86DeleteMode(&pScrn->modes, pScrn->modes);
+ while (pScrn->modePool)
+ xf86DeleteMode(&pScrn->modePool, pScrn->modePool);
+
+ /* Next try to add DDC modes */
+ modesFound = RADEONValidateDDCModes(pScrn, pScrn1->display->modes,
+ info->MergeType, 1);
/* If that fails and we're connect to a flat panel, then try to
* add the flat panel modes
*/
- if (modesFound < 1 && info->CloneType != MT_CRT) {
- modesFound =
- xf86ValidateModes(pScrn, pScrn->monitor->Modes,
- clone_mode_names,
- clockRanges,
- NULL, /* linePitches */
- 8 * 64, /* minPitch */
- 8 * 1024, /* maxPitch */
- 64 * pScrn->bitsPerPixel, /* pitchInc */
- 128, /* minHeight */
- 2048, /* maxHeight */
- pScrn->display->virtualX,
- pScrn->display->virtualY,
- info->FbMapSize,
- LOOKUP_BEST_REFRESH);
- }
- }
-
- if (modesFound > 0) {
- int valid = 0;
- save_mode = pScrn->modes;
- xf86SetCrtcForModes(pScrn, 0);
- xf86PrintModes(pScrn);
- for (i = 0; i < modesFound; i++) {
-
- while (pScrn->modes->status != MODE_OK) {
- pScrn->modes = pScrn->modes->next;
- }
- if (!pScrn->modes) break;
-
- if (pScrn->modes->Clock != 0.0) {
-
- clone_mode = xnfcalloc (1, sizeof (DisplayModeRec));
- if (!clone_mode) break;
- memcpy(clone_mode, pScrn->modes, sizeof(DisplayModeRec));
- clone_mode->name = xnfalloc(strlen(pScrn->modes->name) + 1);
- strcpy(clone_mode->name, pScrn->modes->name);
-
- if (!info->CurCloneMode) {
- info->CloneModes = clone_mode;
- info->CurCloneMode = clone_mode;
- clone_mode->prev = NULL;
- } else {
- clone_mode->prev = tmp_mode;
- clone_mode->prev->next = clone_mode;
- }
- valid++;
+ if (info->MergeType != MT_CRT) {
- tmp_mode = clone_mode;
- clone_mode->next = NULL;
+ /* some panels have DDC, but don't have internal scaler.
+ * in this case, we need to validate additional modes
+ * by using on-chip RMX.
+ */
+ int user_modes_asked = 0, user_modes_found = 0, i;
+ DisplayModePtr tmp_mode = pScrn->modes;
+ while (pScrn1->display->modes[user_modes_asked]) user_modes_asked++;
+ if (tmp_mode) {
+ for (i = 0; i < modesFound; i++) {
+ if (tmp_mode->type & M_T_USERDEF) user_modes_found++;
+ tmp_mode = tmp_mode->next;
+ }
}
- pScrn->modes = pScrn->modes->next;
- }
-
- /* no longer needed, free it */
- pScrn->modes = save_mode;
- while (pScrn->modes)
- xf86DeleteMode(&pScrn->modes, pScrn->modes);
- pScrn->modes = NULL;
- /* modepool is no longer needed, free it */
- while (pScrn->modePool)
- xf86DeleteMode(&pScrn->modePool, pScrn->modePool);
- pScrn->modePool = NULL;
+ if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) {
+ /* when panel size is not valid, try to validate
+ * mode using xf86ValidateModes routine
+ * This can happen when DDC is disabled.
+ */
+ /* if (info->PanelXRes < 320 || info->PanelYRes < 200) */
+ modesFound =
+ xf86ValidateModes(pScrn,
+ pScrn->monitor->Modes,
+ pScrn1->display->modes,
+ clockRanges,
+ NULL, /* linePitches */
+ 8 * 64, /* minPitch */
+ 8 * 1024, /* maxPitch */
+ 64 * pScrn1->bitsPerPixel, /* pitchInc */
+ 128, /* minHeight */
+ 8 * 1024, /*2048,*/ /* maxHeight */
+ pScrn1->display->virtualX,
+ pScrn1->display->virtualY,
+ info->FbMapSize,
+ LOOKUP_BEST_REFRESH);
- modesFound = valid;
- }
+ }
+ }
- /* Clone_mode_names list is no longer needed, free it. */
- if (clone_mode_names) {
- for (i = 0; clone_mode_names[i]; i++) {
- free(clone_mode_names[i]);
- clone_mode_names[i] = NULL;
+ /* Setup the screen's clockRanges for the VidMode extension */
+ if (!pScrn->clockRanges) {
+ pScrn->clockRanges = xnfcalloc(sizeof(*(pScrn->clockRanges)), 1);
+ memcpy(pScrn->clockRanges, clockRanges, sizeof(*clockRanges));
+ pScrn->clockRanges->strategy = LOOKUP_BEST_REFRESH;
}
- free(clone_mode_names);
- clone_mode_names = NULL;
- }
-
- /* We need to restore all changed info for the primary head */
-
- pScrn->monitor->hsync[0] = save_hsync;
- pScrn->monitor->vrefresh[0] = save_vrefresh;
- pScrn->monitor->nHsync = save_n_hsync;
- pScrn->monitor->nVrefresh = save_n_vrefresh;
-
- /*
- * Also delete the clockRanges (if it was setup) since it will be
- * set up during the primary head initialization.
- */
- while (pScrn->clockRanges) {
- ClockRangesPtr CRtmp = pScrn->clockRanges;
- pScrn->clockRanges = pScrn->clockRanges->next;
- xfree(CRtmp);
+ /* Fail if we still don't have any valid modes */
+ if (modesFound < 1) {
+ if (info->MergeType == MT_CRT) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid DDC modes found for this CRT\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Try turning off the \"DDCMode\" option\n");
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid mode found for this DFP/LCD\n");
+ }
+ return 0;
+ }
}
-
-
return modesFound;
}
+
/* This is called by RADEONPreInit to validate modes and compute
* parameters for all of the valid modes.
*/
@@ -3160,6 +3321,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
ClockRangePtr clockRanges;
int modesFound;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ char *s;
/* This option has two purposes:
*
@@ -3188,48 +3350,21 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
*
* Note: This option will be dismissed if no DDC data is available.
*/
+
+ if (info->MergedFB) {
+ if (!(pScrn->display->virtualX))
+ info->NoVirtual = TRUE;
+ else
+ info->NoVirtual = FALSE;
+ }
+
info->ddc_mode =
xf86ReturnOptValBool(info->Options, OPTION_DDC_MODE, FALSE);
- /* don't use RMX if we have a dual-tdms panels */
+ /* don't use RMX if we have a dual-tmds panels */
if (pRADEONEnt->MonType2 == MT_DFP)
info->ddc_mode = TRUE;
- /* Here is a hack for cloning first display on the second head. If
- * we don't do this, when both heads are connected, the same CRTC
- * will be used to drive them according to the capability of the
- * primary head. This can cause an unstable or blank screen, or
- * even worse it can damage a monitor. This feature is also
- * important for laptops (using M6, M7), where the panel can't be
- * disconnect when one wants to use the CRT port. Although 2
- * Screens can be set up in the config file for displaying same
- * content on two monitors, it has problems with cursor, overlay,
- * DRI.
- */
- if (info->HasCRTC2) {
- if (info->Clone) {
-
- /* If we have 2 screens from the config file, we don't need
- * to do clone thing, let each screen handles one head.
- */
- if (!pRADEONEnt->HasSecondary) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Clone modes validation ------------ \n");
-
- modesFound = RADEONValidateCloneModes(pScrn);
- if (modesFound < 1) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid mode found for CRTC2 clone\n");
- info->Clone = FALSE;
- info->CurCloneMode = NULL;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Total of %d clone modes found ------------ \n\n",
- modesFound);
- }
- }
- }
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Validating modes on %s head ---------\n",
info->IsSecondary ? "Secondary" : "Primary");
@@ -3245,6 +3380,59 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
"No DDC data available, DDCMode option is dismissed\n");
}
+ if ((info->DisplayType == MT_DFP) ||
+ (info->DisplayType == MT_LCD)) {
+ if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) {
+ int PanelX, PanelY;
+ DisplayModePtr tmp_mode = NULL;
+ if (sscanf(s, "%dx%d", &PanelX, &PanelY) == 2) {
+ info->PanelXRes = PanelX;
+ info->PanelYRes = PanelY;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Panel size is forced to: %s\n", s);
+
+ /* We can't trust BIOS or DDC timings anymore,
+ Use whatever specified in the Modeline.
+ If no Modeline specified, we'll just pick the VESA mode at
+ 60Hz refresh rate which is likely to be the best for a flat panel.
+ */
+ info->ddc_mode = FALSE;
+ pScrn->monitor->DDC = NULL;
+ tmp_mode = pScrn->monitor->Modes;
+ while(tmp_mode) {
+ if ((tmp_mode->HDisplay == PanelX) &&
+ (tmp_mode->VDisplay == PanelY)) {
+
+ float refresh =
+ (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal;
+ if ((abs(60.0 - refresh) < 1.0) ||
+ (tmp_mode->type == 0)) {
+ info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay;
+ info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay;
+ info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart;
+ info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay;
+ info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay;
+ info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart;
+ info->DotClock = tmp_mode->Clock;
+ info->Flags = 0;
+ break;
+ }
+ }
+ tmp_mode = tmp_mode->next;
+ }
+ if (info->DotClock == 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid timing info for specified panel size.\n"
+ "Please specify the Modeline for this panel\n");
+ return FALSE;
+ }
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Invalid PanelSize value: %s\n", s);
+ }
+ }
+ }
+
if (pScrn->monitor->DDC) {
/* If we still don't know sync range yet, let's try EDID.
*
@@ -3317,7 +3505,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
/* Next try to add DDC modes */
modesFound = RADEONValidateDDCModes(pScrn, pScrn->display->modes,
- info->DisplayType);
+ info->DisplayType, 0);
/* If that fails and we're connect to a flat panel, then try to
* add the flat panel modes
@@ -3388,30 +3576,110 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
xf86SetCrtcForModes(pScrn, 0);
- /* We need to adjust virtual size if the clone modes have larger
- * display size.
- */
- if (info->Clone && info->CloneModes) {
- DisplayModePtr clone_mode = info->CloneModes;
- while (1) {
- if ((clone_mode->HDisplay > pScrn->virtualX) ||
- (clone_mode->VDisplay > pScrn->virtualY)) {
- pScrn->virtualX =
- pScrn->display->virtualX = clone_mode->HDisplay;
- pScrn->virtualY =
- pScrn->display->virtualY = clone_mode->VDisplay;
- RADEONSetPitch(pScrn);
+ if (info->HasCRTC2) {
+ if (info->MergedFB) {
+
+ /* If we have 2 screens from the config file, we don't need
+ * to do clone thing, let each screen handles one head.
+ */
+ if (!pRADEONEnt->HasSecondary) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Validating CRTC2 modes for MergedFB ------------ \n");
+
+ modesFound = RADEONValidateMergeModes(pScrn);
+ if (modesFound < 1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid mode found for CRTC2, disabling MergedFB\n");
+ info->MergedFB = FALSE;
+ }
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Total of %d CRTC2 modes found for MergedFB------------ \n",
+ modesFound);
}
- if (!clone_mode->next) break;
- clone_mode = clone_mode->next;
}
}
pScrn->currentMode = pScrn->modes;
+ if(info->MergedFB) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Modes for CRT1: ********************\n");
+ }
xf86PrintModes(pScrn);
+ if(info->MergedFB) {
+
+ xf86SetCrtcForModes(info->CRT2pScrn, INTERLACE_HALVE_V);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Modes for CRT2: ********************\n");
+
+ xf86PrintModes(info->CRT2pScrn);
+
+ info->CRT1Modes = pScrn->modes;
+ info->CRT1CurrentMode = pScrn->currentMode;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Generating MergedFB mode list\n");
+
+ if (info->NoVirtual) {
+ pScrn->display->virtualX = 0;
+ pScrn->display->virtualY = 0;
+ }
+ pScrn->modes = RADEONGenerateModeList(pScrn, info->MetaModes,
+ info->CRT1Modes, info->CRT2pScrn->modes,
+ info->CRT2Position);
+
+ if(!pScrn->modes) {
+
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to parse MetaModes or no modes found. MergeFB mode disabled.\n");
+ if(info->CRT2pScrn) {
+ if(info->CRT2pScrn->modes) {
+ while(info->CRT2pScrn->modes)
+ xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes);
+ }
+ if(info->CRT2pScrn->monitor) {
+ if(info->CRT2pScrn->monitor->Modes) {
+ while(info->CRT2pScrn->monitor->Modes)
+ xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes);
+ }
+ if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC);
+ xfree(info->CRT2pScrn->monitor);
+ }
+ xfree(info->CRT2pScrn);
+ }
+ pScrn->modes = info->CRT1Modes;
+ info->CRT1Modes = NULL;
+ info->MergedFB = FALSE;
+
+ }
+ }
+
+ if (info->MergedFB) {
+ /* If no virtual dimension was given by the user,
+ * calculate a sane one now. Adapts pScrn->virtualX,
+ * pScrn->virtualY and pScrn->displayWidth.
+ */
+ RADEONRecalcDefaultVirtualSize(pScrn);
+ info->CRT2pScrn->virtualX = pScrn->virtualX;
+ info->CRT2pScrn->virtualY = pScrn->virtualY;
+ RADEONSetPitch(pScrn);
+ RADEONSetPitch(info->CRT2pScrn);
+
+ pScrn->modes = pScrn->modes->next; /* We get the last from GenerateModeList() */
+ pScrn->currentMode = pScrn->modes;
+
+ /* Update CurrentLayout */
+ info->CurrentLayout.mode = pScrn->currentMode;
+ info->CurrentLayout.displayWidth = pScrn->displayWidth;
+ }
+
/* Set DPI */
- xf86SetDpi(pScrn, 0, 0);
+ /* xf86SetDpi(pScrn, 0, 0); */
+
+ if(info->MergedFB)
+ RADEONMergedFBSetDpi(pScrn, info->CRT2pScrn, info->CRT2Position);
+ else
+ xf86SetDpi(pScrn, 0, 0);
/* Get ScreenInit function */
if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
@@ -3523,8 +3791,10 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
}
}
- if (xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE, (int *)&(info->gartSize))) {
+ if ((xf86GetOptValInteger(info->Options,
+ OPTION_GART_SIZE, (int *)&(info->gartSize))) ||
+ (xf86GetOptValInteger(info->Options,
+ OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) {
switch (info->gartSize) {
case 4:
case 8:
@@ -3638,6 +3908,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
RADEONInfoPtr info;
xf86Int10InfoPtr pInt10 = NULL;
void *int10_save = NULL;
+ const char *s;
+
RADEONTRACE(("RADEONPreInit\n"));
if (pScrn->numEntities != 1) return FALSE;
@@ -3646,9 +3918,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->IsSecondary = FALSE;
- info->Clone = FALSE;
- info->CurCloneMode = NULL;
- info->CloneModes = NULL;
+ info->MergedFB = FALSE;
info->IsSwitching = FALSE;
info->MMIO = NULL;
@@ -3662,7 +3932,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->MMIOAddr = info->PciInfo->memBase[2] & 0xffffff00;
if (info->pEnt->device->IOBase) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "MMIO address override, using 0x%08x instead of 0x%08x\n",
+ "MMIO address override, using 0x%08lx instead of 0x%08lx\n",
info->pEnt->device->IOBase,
info->MMIOAddr);
info->MMIOAddr = info->pEnt->device->IOBase;
@@ -3770,6 +4040,18 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->videoKey = 0x1E;
}
+ info->DispPriority = 1;
+ if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) {
+ if (strcmp(s, "AUTO") == 0) {
+ info->DispPriority = 1;
+ } else if (strcmp(s, "BIOS") == 0) {
+ info->DispPriority = 0;
+ } else if (strcmp(s, "HIGH") == 0) {
+ info->DispPriority = 2;
+ } else
+ info->DispPriority = 1;
+ }
+
if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE)) {
/* check for Linux framebuffer device */
@@ -3804,6 +4086,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONGetBIOSParameters(pScrn, pInt10))
goto fail;
+
+ if (info->DisplayType == MT_DFP)
+ RADEONGetTMDSInfo(pScrn);
+
+ /* collect MergedFB options */
+ /* only parse mergedfb options on the primary head.
+ Mergedfb is already disabled in xinerama/screen based
+ multihead */
+ if (!info->IsSecondary)
+ RADEONGetMergedFBOptions(pScrn);
if (!RADEONGetPLLParameters(pScrn)) goto fail;
@@ -3940,7 +4232,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
}
}
- if (info->Clone) {
+ if (info->MergedFB) {
PAL_SELECT(1);
if (info->CurrentLayout.depth == 15) {
/* 15bpp mode. This sends 32 values. */
@@ -4057,14 +4349,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
- if (info->CurCloneMode) {
- info->CloneFrameX0 =
- (pScrn->virtualX - info->CurCloneMode->HDisplay) / 2;
- info->CloneFrameY0 =
- (pScrn->virtualY - info->CurCloneMode->VDisplay) / 2;
- RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0, TRUE);
- }
-
/* Visual setup */
miClearVisualTypes();
if (!miSetVisualTypes(pScrn->depth,
@@ -4093,48 +4377,52 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
"Acceleration disabled, not initializing the DRI\n");
info->directRenderingEnabled = FALSE;
} else if (maxy <= pScrn->virtualY * 3) {
- xf86DrvMsg(scrnIndex, X_WARNING,
- "Static buffer allocation failed -- "
- "need at least %d kB video memory\n",
+ xf86DrvMsg(scrnIndex, X_ERROR,
+ "Static buffer allocation failed. Disabling DRI.\n");
+ xf86DrvMsg(scrnIndex, X_ERROR,
+ "At least %d kB of video memory needed at this "
+ "resolution and depth.\n",
(pScrn->displayWidth * pScrn->virtualY *
info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
info->directRenderingEnabled = FALSE;
- } else if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200) ||
- (info->ChipFamily == CHIP_FAMILY_RS300)) {
+ } else if (info->ChipFamily >= CHIP_FAMILY_R300) {
info->directRenderingEnabled = FALSE;
xf86DrvMsg(scrnIndex, X_WARNING,
"Direct rendering not yet supported on "
- "IGP320/330/340/350, 7000, 9000 integrated chips\n");
- } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350) ||
- (info->ChipFamily == CHIP_FAMILY_RV350)) {
+ "Radeon 9500 and newer cards\n");
+ } else if (info->IsSecondary) {
+ info->directRenderingEnabled = FALSE;
+ } else if (xf86IsEntityShared(info->pEnt->index)) {
+ /* Xinerama has sync problem with DRI, disable it for now */
info->directRenderingEnabled = FALSE;
xf86DrvMsg(scrnIndex, X_WARNING,
- "Direct rendering not yet supported on "
- "Radeon 9500/9700 and newer cards\n");
- } else {
- if (info->IsSecondary)
- info->directRenderingEnabled = FALSE;
- else {
- /* Xinerama has sync problem with DRI, disable it for now */
- if (xf86IsEntityShared(info->pEnt->index)) {
- info->directRenderingEnabled = FALSE;
- xf86DrvMsg(scrnIndex, X_WARNING,
- "Direct Rendering Disabled -- "
- "Dual-head configuration is not working with "
- "DRI at present.\n"
- "Please use only one Device/Screen "
- "section in your XFConfig file.\n");
- } else {
- info->directRenderingEnabled =
- RADEONDRIScreenInit(pScreen);
- }
+ "Direct Rendering Disabled -- "
+ "Dual-head configuration is not working with "
+ "DRI at present.\n"
+ "Please use the radeon MergedFB option if you "
+ "want Dual-head with DRI.\n");
+#if 0
+ } else if ( pScrn->virtualX > 2048 || pScrn->virtualY > 2048 ) {
+ if (info->No2048Limit) {
+ info->directRenderingEnabled = RADEONDRIScreenInit(pScreen);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRI forced on with virtual screen of greater than 2048.\n");
+ } else {
+ info->directRenderingEnabled = FALSE;
+ xf86DrvMsg(scrnIndex, X_WARNING,
+ "Direct Rendering Disabled -- "
+ "Virtual resolution exceeds 2048 "
+ "(hardware limitation)\n");
}
+#endif
+ } else {
+ info->directRenderingEnabled = RADEONDRIScreenInit(pScreen);
}
}
#endif
+ RADEONSetFBLocation(pScrn);
+
if (!fbScreenInit(pScreen, info->FB,
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
@@ -4366,13 +4654,13 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
info->textureSize/1024, info->textureOffset);
info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- (info->frontOffset >> 10));
+ ((info->frontOffset + info->fbLocation) >> 10));
info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- (info->backOffset >> 10));
+ ((info->backOffset + info->fbLocation) >> 10));
info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) |
- (info->depthOffset >> 10));
+ ((info->depthOffset + info->fbLocation) >> 10));
} else
#endif
{
@@ -4462,7 +4750,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
int width, height;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor (scanline %d)\n",
+ "Using hardware cursor (scanline %ld)\n",
info->cursor_start / pScrn->displayWidth
/ info->CurrentLayout.pixel_bytes);
if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
@@ -4503,6 +4791,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
info->CloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = RADEONCloseScreen;
+ /* Wrap some funcs for MergedFB */
+ if(info->MergedFB) {
+ info->PointerMoved = pScrn->PointerMoved;
+ pScrn->PointerMoved = RADEONMergePointerMoved;
+ /* Psuedo xinerama */
+ if(info->UseRADEONXinerama) {
+ RADEONnoPanoramiXExtension = FALSE;
+ RADEONXineramaExtensionInit(pScrn);
+ }
+ }
+
/* Note unused options */
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
@@ -4513,9 +4812,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
/* Now that mi, fb, drm and others have
done their thing, complete the DRI
setup. */
- info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen);
+ if (!(info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen))) {
+ RADEONAccelInitMMIO(pScreen, info->accel);
+ }
}
if (info->directRenderingEnabled) {
+ if ((info->DispPriority == 1) && (!info->IsPCI)) {
+ /* we need to re-calculate bandwidth because of AGPMode difference. */
+ RADEONInitDispBandwidth(pScrn);
+ }
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering disabled\n");
@@ -4561,7 +4866,7 @@ static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
CARD32 tmp;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- if (pRADEONEnt->HasSecondary || info->Clone) {
+ if (pRADEONEnt->HasSecondary || info->MergedFB) {
tmp = INREG(RADEON_DAC_CNTL2);
OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL);
usleep(100000);
@@ -4622,6 +4927,7 @@ static void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
+ OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl);
}
/* Write CRTC2 registers */
@@ -4659,7 +4965,7 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
if ((info->DisplayType == MT_DFP && info->IsSecondary) ||
- info->CloneType == MT_DFP) {
+ info->MergeType == MT_DFP) {
OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid);
OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid);
OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
@@ -4820,6 +5126,7 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
~(RADEON_PLL_DIV_SEL));
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_R350) ||
(info->ChipFamily == CHIP_FAMILY_RV350)) {
if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
@@ -4861,7 +5168,7 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
| RADEON_PPLL_ATOMIC_UPDATE_EN
| RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
- xf86DrvMsg(0, X_INFO, "Wrote: rd=%d, fd=%d, pd=%d\n",
+ xf86DrvMsg(0, X_INFO, "Wrote: rd=%ld, fd=%ld, pd=%ld\n",
restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
(restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
@@ -5020,7 +5327,7 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore)
if (!pRADEONEnt->IsSecondaryRestored)
RADEONRestoreCommonRegisters(pScrn, restore);
- if (info->Clone) {
+ if (info->MergedFB) {
RADEONRestoreCrtc2Registers(pScrn, restore);
RADEONRestorePLL2Registers(pScrn, restore);
}
@@ -5061,6 +5368,8 @@ static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
save->bus_cntl = INREG(RADEON_BUS_CNTL);
save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
+ save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
+ save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
}
/* Read miscellaneous registers which might be destroyed by an fbdevHW call */
@@ -5102,6 +5411,7 @@ static void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
+ save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
}
/* Read flat panel registers */
@@ -5122,6 +5432,11 @@ static void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL);
save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL);
save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
+
+ if (info->ChipFamily == CHIP_FAMILY_RV280) {
+ /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
+ save->tmds_pll_cntl ^= (1 << 22);
+ }
}
/* Read CRTC2 registers */
@@ -5218,7 +5533,7 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONSaveCrtcRegisters(pScrn, save);
RADEONSaveFPRegisters(pScrn, save);
- if (info->Clone) {
+ if (info->MergedFB) {
RADEONSaveCrtc2Registers(pScrn, save);
RADEONSavePLL2Registers(pScrn, save);
}
@@ -5290,12 +5605,14 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
if (info->R300CGWorkaround) R300CGWorkaround(pScrn);
OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
#if 0
/* M6 card has trouble restoring text mode for its CRT.
* This is fixed elsewhere and will be removed in the future.
*/
- if ((xf86IsEntityShared(info->pEnt->index) || info->Clone)
+ if ((xf86IsEntityShared(info->pEnt->index) || info->MergedFB)
&& info->IsM6)
OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
#endif
@@ -5362,6 +5679,324 @@ static void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
}
+/* Calculate display buffer watermark to prevent buffer underflow */
+static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONInfoPtr info2 = NULL;
+
+ DisplayModePtr mode1, mode2;
+
+ CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0;
+ float mem_tcas;
+ int k1, c;
+ CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4};
+ CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4};
+ CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+
+ CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+ CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+ CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
+
+ float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0};
+ float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7};
+ float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5};
+
+ float mem_bw, peak_disp_bw;
+ float min_mem_eff = 0.8;
+ float sclk_eff, sclk_delay;
+ float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
+ float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2;
+ float pix_clk, pix_clk2; /* in MHz */
+ int cur_size = 16; /* in octawords */
+ int critical_point, critical_point2;
+ int stop_req, max_stop_req;
+ float read_return_rate, time_disp1_drop_priority;
+
+ if (pRADEONEnt->pSecondaryScrn) {
+ if (info->IsSecondary) return;
+ info2 = RADEONPTR(pRADEONEnt->pSecondaryScrn);
+ } else if (info->MergedFB) info2 = info;
+
+ /*
+ * Determine if there is enough bandwidth for current display mode
+ */
+ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
+
+ mode1 = info->CurrentLayout.mode;
+ if (info->MergedFB) {
+ mode1 = ((RADEONMergedDisplayModePtr)info->CurrentLayout.mode->Private)->CRT1;
+ mode2 = ((RADEONMergedDisplayModePtr)info->CurrentLayout.mode->Private)->CRT2;
+ } else if ((pRADEONEnt->HasSecondary) && info2) {
+ mode2 = info2->CurrentLayout.mode;
+ } else {
+ mode2 = NULL;
+ }
+
+ pix_clk = mode1->Clock/1000.0;
+ if (mode2)
+ pix_clk2 = mode2->Clock/1000.0;
+ else
+ pix_clk2 = 0;
+
+ peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes);
+ if (info2)
+ peak_disp_bw += (pix_clk2 * info2->CurrentLayout.pixel_bytes);
+
+ if (peak_disp_bw >= mem_bw * min_mem_eff) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "You may not have enough display bandwidth for current mode\n"
+ "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
+ }
+
+ /* CRTC1
+ Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ */
+ stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
+
+ /* setup Max GRPH_STOP_REQ default value */
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
+ (info->ChipFamily == CHIP_FAMILY_RV200) ||
+ (info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280) ||
+ (info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300))
+ max_stop_req = 0x5c;
+ else
+ max_stop_req = 0x7c;
+ if (stop_req > max_stop_req)
+ stop_req = max_stop_req;
+
+ /* Get values from the EXT_MEM_CNTL register...converting its contents. */
+ temp = INREG(RADEON_MEM_TIMING_CNTL);
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
+ mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2];
+ mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0];
+ mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4];
+ } else { /* RV200 and later */
+ mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0];
+ mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
+ mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
+ }
+
+ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
+ temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
+ data = (temp & (7<<20)) >> 20;
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
+ mem_tcas = MemTcas [data];
+ } else {
+ mem_tcas = MemTcas2 [data];
+ }
+
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
+
+ /* on the R300, Tcas is included in Trbs.
+ */
+ temp = INREG(RADEON_MEM_CNTL);
+ data = (R300_MEM_NUM_CHANNELS_MASK & temp);
+ if (data == 2) {
+ if (R300_MEM_USE_CD_CH_ONLY & temp) {
+ temp = INREG(R300_MC_IND_INDEX);
+ temp &= ~R300_MC_IND_ADDR_MASK;
+ temp |= R300_MC_READ_CNTL_CD_mcind;
+ OUTREG(R300_MC_IND_INDEX, temp);
+ temp = INREG(R300_MC_IND_DATA);
+ data = (R300_MEM_RBS_POSITION_C_MASK & temp);
+ } else {
+ temp = INREG(R300_MC_READ_CNTL_AB);
+ data = (R300_MEM_RBS_POSITION_A_MASK & temp);
+ }
+ } else {
+ temp = INREG(R300_MC_READ_CNTL_AB);
+ data = (R300_MEM_RBS_POSITION_A_MASK & temp);
+ }
+
+ mem_trbs = MemTrbs[data];
+ mem_tcas += mem_trbs;
+ }
+
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
+ /* DDR64 SCLK_EFF = SCLK for analysis */
+ sclk_eff = info->sclk;
+ } else {
+#ifdef XF86DRI
+ if (info->directRenderingEnabled)
+ sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0);
+ else
+#endif
+ sclk_eff = info->sclk;
+ }
+
+ /* Find the memory controller latency for the display client.
+ */
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
+ /*not enough for R350 ???*/
+ /*
+ if (!mode2) sclk_delay = 150;
+ else {
+ if (info->RamWidth == 256) sclk_delay = 87;
+ else sclk_delay = 97;
+ }
+ */
+ sclk_delay = 250;
+ } else {
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
+ info->IsIGP) {
+ if (info->IsDDR) sclk_delay = 41;
+ else sclk_delay = 33;
+ } else {
+ if (info->RamWidth == 128) sclk_delay = 57;
+ else sclk_delay = 41;
+ }
+ }
+
+ mc_latency_sclk = sclk_delay / sclk_eff;
+
+ if (info->IsDDR) {
+ if (info->RamWidth == 32) {
+ k1 = 40;
+ c = 3;
+ } else {
+ k1 = 20;
+ c = 1;
+ }
+ } else {
+ k1 = 40;
+ c = 3;
+ }
+ mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) /
+ info->mclk) + (4.0 / sclk_eff);
+
+ /*
+ HW cursor time assuming worst case of full size colour cursor.
+ */
+ cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk;
+ cur_latency_sclk = cur_size / sclk_eff;
+
+ /*
+ Find the total latency for the display data.
+ */
+ disp_latency_overhead = 8.0 / info->sclk;
+ mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk;
+ mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
+ disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
+
+ /*
+ Find the drain rate of the display buffer.
+ */
+ disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes);
+ if (info2)
+ disp_drain_rate2 = pix_clk2 / (16.0/info2->CurrentLayout.pixel_bytes);
+ else
+ disp_drain_rate2 = 0;
+
+ /*
+ Find the critical point of the display buffer.
+ */
+ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
+
+ /* ???? */
+ /*
+ temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
+ if (critical_point < temp) critical_point = temp;
+ */
+ if (info->DispPriority == 2) {
+ if (mode2) {
+ /*??some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
+ if (info->ChipFamily == CHIP_FAMILY_R300)
+ critical_point += 0x10;
+ else
+ critical_point = 0;
+ }
+ else
+ critical_point = 0;
+ }
+
+ /*
+ The critical point should never be above max_stop_req-4. Setting
+ GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
+ */
+ if (max_stop_req - critical_point < 4) critical_point = 0;
+
+ temp = info->SavedReg.grph_buffer_cntl;
+ temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
+ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+ temp &= ~(RADEON_GRPH_START_REQ_MASK);
+ if ((info->ChipFamily == CHIP_FAMILY_R350) &&
+ (stop_req > 0x15)) {
+ stop_req -= 0x10;
+ }
+ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+
+ temp |= RADEON_GRPH_BUFFER_SIZE;
+ temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
+ RADEON_GRPH_CRITICAL_AT_SOF |
+ RADEON_GRPH_STOP_CNTL);
+ /*
+ Write the result into the register.
+ */
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
+ (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+
+ RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n",
+ info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
+
+ if (mode2) {
+ stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16;
+
+ if (stop_req > max_stop_req) stop_req = max_stop_req;
+
+ temp = info->SavedReg.grph2_buffer_cntl;
+ temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
+ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+ temp &= ~(RADEON_GRPH_START_REQ_MASK);
+ if ((info->ChipFamily == CHIP_FAMILY_R350) &&
+ (stop_req > 0x15)) {
+ stop_req -= 0x10;
+ }
+ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+ temp |= RADEON_GRPH_BUFFER_SIZE;
+ temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
+ RADEON_GRPH_CRITICAL_AT_SOF |
+ RADEON_GRPH_STOP_CNTL);
+
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200))
+ critical_point2 = 0;
+ else {
+ read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
+ time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate);
+
+ critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority +
+ disp_latency) * disp_drain_rate2 + 0.5);
+
+ if (info->DispPriority == 2) {
+ if (info->ChipFamily == CHIP_FAMILY_R300)
+ critical_point2 += 0x10;
+ else
+ critical_point2 = 0;
+ }
+
+ if (max_stop_req - critical_point2 < 4) critical_point2 = 0;
+
+ }
+
+ OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
+ (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+
+ RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n",
+ info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL)));
+ }
+}
+
/* Define CRTC registers for requested video mode */
static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, RADEONInfoPtr info)
@@ -5486,6 +6121,16 @@ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
((pScrn->bitsPerPixel * 8) -1)) /
(pScrn->bitsPerPixel * 8));
save->crtc_pitch |= save->crtc_pitch << 16;
+
+ /* Some versions of BIOS setup CRTC_MORE_CNTL for a DFP, if we
+ have a CRT here, it should be cleared to avoild a blank screen.
+ */
+ if (info->DisplayType == MT_CRT)
+ save->crtc_more_cntl = (info->SavedReg.crtc_more_cntl &
+ ~(RADEON_CRTC_H_CUTOFF_ACTIVE_EN |
+ RADEON_CRTC_V_CUTOFF_ACTIVE_EN));
+ else
+ save->crtc_more_cntl = info->SavedReg.crtc_more_cntl;
save->surface_cntl = 0;
save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
@@ -5637,16 +6282,23 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->crtc2_offset = 0;
save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
-
+ /* this should be right */
+ if (info->MergedFB) {
+ save->crtc2_pitch = (((info->CRT2pScrn->displayWidth * pScrn->bitsPerPixel) +
+ ((pScrn->bitsPerPixel * 8) -1)) /
+ (pScrn->bitsPerPixel * 8));
+ save->crtc2_pitch |= save->crtc2_pitch << 16;
+ } else {
save->crtc2_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
((pScrn->bitsPerPixel * 8) -1)) /
(pScrn->bitsPerPixel * 8));
save->crtc2_pitch |= save->crtc2_pitch << 16;
+ }
save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
if ((info->DisplayType == MT_DFP && info->IsSecondary) ||
- info->CloneType == MT_DFP) {
+ info->MergeType == MT_DFP) {
save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8));
save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid;
save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid;
@@ -5674,16 +6326,8 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* FIXME: When there are two DFPs, the 2nd DFP is driven by the
* external TMDS transmitter. It may have a problem at
- * high dot clock for certain panels. Since we don't
- * know how to control the external TMDS transmitter, not
- * much we can do here.
+ * high dot clock for certain panels.
*/
-#if 0
- if (save->dot_clock_freq > 15000)
- save->tmds_pll_cntl = 0xA3F;
- else if(save->tmds_pll_cntl != 0xA3F)
- save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl;
-#endif
/* If BIOS has not turned it on, we'll keep it on so that we'll
* have a valid VGA screen even after X quits or VT is switched
@@ -5810,16 +6454,6 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
save->lvds_gen_cntl = orig->lvds_gen_cntl;
save->lvds_pll_cntl = orig->lvds_pll_cntl;
- /* This is needed for some panel at high resolution (>=1600x1200)
- */
- if ((save->dot_clock_freq > 15000) &&
- (info->ChipFamily != CHIP_FAMILY_R300) &&
- (info->ChipFamily != CHIP_FAMILY_R350) &&
- (info->ChipFamily != CHIP_FAMILY_RV350))
- save->tmds_pll_cntl = 0xA3F;
- else
- save->tmds_pll_cntl = orig->tmds_pll_cntl;
-
info->PanelOff = FALSE;
/* This option is used to force the ONLY DEVICE in XFConfig to use
* CRT port, instead of default DVI port.
@@ -5828,8 +6462,9 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
info->PanelOff = TRUE;
}
+ save->tmds_pll_cntl = orig->tmds_pll_cntl;
save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl;
- if (info->PanelOff && info->Clone) {
+ if (info->PanelOff && info->MergedFB) {
info->OverlayOnCRTC2 = TRUE;
if (info->DisplayType == MT_LCD) {
/* Turning off LVDS_ON seems to make panel white blooming.
@@ -5847,7 +6482,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
/* BIOS will use this setting to reset displays upon lid close/open.
* Here we let BIOS controls LCD, but the driver will control the external CRT.
*/
- if (info->Clone || pRADEONEnt->HasSecondary)
+ if (info->MergedFB || pRADEONEnt->HasSecondary)
save->bios_5_scratch = 0x01020201;
else
save->bios_5_scratch = orig->bios_5_scratch;
@@ -5856,13 +6491,28 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (info->DisplayType == MT_DFP) {
- /* This is needed for some panel at high resolution (>=1600x1200)
- */
- if ((save->dot_clock_freq > 15000) &&
- (info->ChipFamily != CHIP_FAMILY_R300) &&
- (info->ChipFamily != CHIP_FAMILY_R350) &&
- (info->ChipFamily != CHIP_FAMILY_RV350))
- save->tmds_pll_cntl = 0xA3F;
+ int i;
+ CARD32 tmp = orig->tmds_pll_cntl & 0xfffff;
+ for (i=0; i<4; i++) {
+ if (info->tmds_pll[i].freq == 0) break;
+ if (save->dot_clock_freq < info->tmds_pll[i].freq) {
+ tmp = info->tmds_pll[i].value ;
+ break;
+ }
+ }
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280)) {
+ if (tmp & 0xfff00000)
+ save->tmds_pll_cntl = tmp;
+ else
+ save->tmds_pll_cntl = (orig->tmds_pll_cntl & 0xfff00000) | tmp;
+ } else save->tmds_pll_cntl = tmp;
+
+ RADEONTRACE(("TMDS_PLL from %x to %x\n",
+ orig->tmds_pll_cntl,
+ save->tmds_pll_cntl));
save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
@@ -6070,6 +6720,23 @@ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode,
if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
return FALSE;
RADEONInitPLL2Registers(save, &info->pll, dot_clock);
+ } else if (info->MergedFB) {
+ RADEONInitCommonRegisters(save, info);
+ if (!RADEONInitCrtcRegisters(pScrn, save,
+ ((RADEONMergedDisplayModePtr)mode->Private)->CRT1, info))
+ return FALSE;
+ dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;
+ if (dot_clock) {
+ RADEONInitPLLRegisters(save, &info->pll, dot_clock);
+ } else {
+ save->ppll_ref_div = info->SavedReg.ppll_ref_div;
+ save->ppll_div_3 = info->SavedReg.ppll_div_3;
+ save->htotal_cntl = info->SavedReg.htotal_cntl;
+ }
+ RADEONInitCrtc2Registers(pScrn, save,
+ ((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
+ dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;
+ RADEONInitPLL2Registers(save, &info->pll, dot_clock);
} else {
RADEONInitCommonRegisters(save, info);
if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
@@ -6089,16 +6756,25 @@ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode,
save->htotal_cntl = info->SavedReg.htotal_cntl;
}
- if (info->Clone && info->CurCloneMode) {
- RADEONInitCrtc2Registers(pScrn, save, info->CurCloneMode, info);
- dot_clock = info->CurCloneMode->Clock / 1000.0;
- RADEONInitPLL2Registers(save, &info->pll, dot_clock);
- }
/* Not used for now: */
/* if (!info->PaletteSavedOnVT) RADEONInitPalette(save); */
}
- RADEONInitFPRegisters(pScrn, &info->SavedReg, save, mode, info);
+ /* make RMX work for mergedfb modes on the LCD */
+ if (info->MergedFB) {
+ if ((info->MergeType == MT_LCD) || (info->MergeType == MT_DFP)) {
+ /* I suppose crtc2 could drive the FP as well... */
+ RADEONInitFPRegisters(pScrn, &info->SavedReg, save,
+ ((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
+ }
+ else {
+ RADEONInitFPRegisters(pScrn, &info->SavedReg, save,
+ ((RADEONMergedDisplayModePtr)mode->Private)->CRT1, info);
+ }
+ }
+ else {
+ RADEONInitFPRegisters(pScrn, &info->SavedReg, save, mode, info);
+ }
RADEONTRACE(("RADEONInit returns %p\n", save));
return TRUE;
@@ -6117,6 +6793,10 @@ static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
RADEONUnblank(pScrn);
info->CurrentLayout.mode = mode;
+
+ if (info->DispPriority)
+ RADEONInitDispBandwidth(pScrn);
+
return TRUE;
}
@@ -6159,56 +6839,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
RADEONRestoreFBDevRegisters(pScrn, &info->ModeReg);
} else {
info->IsSwitching = TRUE;
- if (info->Clone && info->CloneModes) {
- DisplayModePtr clone_mode = info->CloneModes;
-
- /* Try to match a mode on primary head
- * FIXME: This may not be good if both heads don't have
- * exactly the same list of mode.
- */
- while (1) {
- if ((clone_mode->HDisplay == mode->HDisplay) &&
- (clone_mode->VDisplay == mode->VDisplay) &&
- (!info->PanelOff)) {
- info->CloneFrameX0 = (info->CurCloneMode->HDisplay +
- info->CloneFrameX0 -
- clone_mode->HDisplay - 1) / 2;
- info->CloneFrameY0 =
- (info->CurCloneMode->VDisplay + info->CloneFrameY0 -
- clone_mode->VDisplay - 1) / 2;
- info->CurCloneMode = clone_mode;
- break;
- }
-
- if (!clone_mode->next) {
- info->CurCloneMode = info->CloneModes;
- break;
- }
-
- clone_mode = clone_mode->next;
- }
- }
ret = RADEONModeInit(xf86Screens[scrnIndex], mode);
-
- if (info->CurCloneMode) {
- if (info->CloneFrameX0 + info->CurCloneMode->HDisplay >=
- pScrn->virtualX)
- info->CloneFrameX0 =
- pScrn->virtualX - info->CurCloneMode->HDisplay;
- else if (info->CloneFrameX0 < 0)
- info->CloneFrameX0 = 0;
-
- if (info->CloneFrameY0 + info->CurCloneMode->VDisplay >=
- pScrn->virtualY)
- info->CloneFrameY0 =
- pScrn->virtualY - info->CurCloneMode->VDisplay;
- else if (info->CloneFrameY0 < 0)
- info->CloneFrameY0 = 0;
-
- RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0,
- TRUE);
- }
-
info->IsSwitching = FALSE;
}
@@ -6224,6 +6855,13 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
}
#endif
+ /* Since RandR (indirectly) uses SwitchMode(), we need to
+ * update our Xinerama info here, too, in case of resizing
+ */
+ if(info->MergedFB) {
+ RADEONUpdateXineramaScreenInfo(pScrn);
+ }
+
return ret;
}
@@ -6310,7 +6948,9 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
if (info->accelOn) info->accel->Sync(pScrn);
- if (info->FBDev) {
+ if(info->MergedFB) {
+ RADEONAdjustFrameMerged(scrnIndex, x, y, flags);
+ } else if (info->FBDev) {
fbdevHWAdjustFrame(scrnIndex, x, y, flags);
} else {
RADEONDoAdjustFrame(pScrn, x, y, FALSE);
@@ -6363,9 +7003,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
#endif
pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
- if (info->CurCloneMode) {
- RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0, TRUE);
- }
return TRUE;
}
@@ -6447,9 +7084,44 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
void RADEONFreeScreen(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONTRACE(("RADEONFreeScreen\n"));
+ if(info->MergedFB) {
+ if(pScrn->modes) {
+ pScrn->currentMode = pScrn->modes;
+ do {
+ DisplayModePtr p = pScrn->currentMode->next;
+ if(pScrn->currentMode->Private)
+ xfree(pScrn->currentMode->Private);
+ xfree(pScrn->currentMode);
+ pScrn->currentMode = p;
+ } while(pScrn->currentMode != pScrn->modes);
+ }
+ pScrn->currentMode = info->CRT1CurrentMode;
+ pScrn->modes = info->CRT1Modes;
+ info->CRT1CurrentMode = NULL;
+ info->CRT1Modes = NULL;
+
+ if(info->CRT2pScrn) {
+ if(info->CRT2pScrn->modes) {
+ while(info->CRT2pScrn->modes)
+ xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes);
+ }
+ if(info->CRT2pScrn->monitor) {
+ if(info->CRT2pScrn->monitor->Modes) {
+ while(info->CRT2pScrn->monitor->Modes)
+ xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes);
+ }
+ if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC);
+ xfree(info->CRT2pScrn->monitor);
+ }
+ xfree(info->CRT2pScrn);
+ info->CRT2pScrn = NULL;
+ }
+ }
+
if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
vgaHWFreeHWRec(pScrn);
RADEONFreeRec(pScrn);
@@ -6487,7 +7159,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
if (info->IsSecondary)
OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
else {
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask1);
}
@@ -6500,7 +7172,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS,
~mask2);
else {
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL,
RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS,
~mask2);
@@ -6517,7 +7189,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS,
~mask2);
else {
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL,
RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS,
~mask2);
@@ -6532,7 +7204,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
if (info->IsSecondary)
OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
else {
- if (info->Clone)
+ if (info->MergedFB)
OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
OUTREGP(RADEON_CRTC_EXT_CNTL, mask1, ~mask1);
}
@@ -6549,7 +7221,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
}
}
} else {
- if ((info->Clone) && (info->CloneType == MT_DFP)) {
+ if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
if (info->ChipFamily >= CHIP_FAMILY_R200) {
@@ -6578,7 +7250,7 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
}
}
} else {
- if ((info->Clone) && (info->CloneType == MT_DFP)) {
+ if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
if (info->ChipFamily >= CHIP_FAMILY_R200) {
@@ -6612,3 +7284,185 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
if (info->CPStarted) DRIUnlock(pScrn->pScreen);
#endif
}
+
+static void
+RADEONGetMergedFBOptions(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ char *strptr;
+ char *default_hsync = "28-33";
+ char *default_vrefresh = "43-72";
+ Bool val;
+ Bool default_range = FALSE;
+ static const char *mybadparm = "\"%s\" is is not a valid parameter for option \"%s\"\n";
+
+ if (info->FBDev == TRUE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "MergedFB does not work with Option UseFBDev, MergedFB mode is disabled\n");
+ info->MergedFB = FALSE;
+ return;
+ }
+
+ /* collect MergedFB options */
+ info->MergedFB = TRUE;
+ info->UseRADEONXinerama = TRUE;
+ info->CRT2IsScrn0 = FALSE;
+ info->CRT2Position = radeonClone;
+ info->MergedFBXDPI = info->MergedFBYDPI = 0;
+
+ if (info->MergeType == MT_NONE) {
+ info->MergedFB = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Failed to detect secondary monitor, MergedFB/Clone mode disabled\n");
+ } else if (!pRADEONEnt->MonInfo2) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Failed to detect secondary monitor DDC, default HSync and VRefresh used\n");
+ default_range = TRUE;
+ }
+
+ if (xf86GetOptValBool(info->Options, OPTION_MERGEDFB, &val)) {
+ if (val) {
+ info->MergedFB = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "MergedFB mode forced on.\n");
+ } else {
+ info->MergedFB = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "MergedFB mode forced off.\n");
+ }
+ }
+
+ /* Do some MergedFB mode initialisation */
+ if(info->MergedFB) {
+ info->CRT2pScrn = xalloc(sizeof(ScrnInfoRec));
+ if(!info->CRT2pScrn) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to allocate memory for merged pScrn, MergedFB mode is disabled\n");
+ info->MergedFB = FALSE;
+ } else {
+ memcpy(info->CRT2pScrn, pScrn, sizeof(ScrnInfoRec));
+ }
+ }
+ if(info->MergedFB) {
+ strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2POS);
+ if(strptr) {
+ if((!strcmp(strptr,"LeftOf")) || (!strcmp(strptr,"leftof"))) {
+ info->CRT2Position = radeonLeftOf;
+ info->CRT2IsScrn0 = TRUE;
+ }
+ else if((!strcmp(strptr,"RightOf")) || (!strcmp(strptr,"rightof"))) {
+ info->CRT2Position = radeonRightOf;
+ info->CRT2IsScrn0 = FALSE;
+ }
+ else if((!strcmp(strptr,"Above")) || (!strcmp(strptr,"above"))) {
+ info->CRT2Position = radeonAbove;
+ info->CRT2IsScrn0 = FALSE;
+ }
+ else if((!strcmp(strptr,"Below")) || (!strcmp(strptr,"below"))) {
+ info->CRT2Position = radeonBelow;
+ info->CRT2IsScrn0 = TRUE;
+ }
+ else if((!strcmp(strptr,"Clone")) || (!strcmp(strptr,"clone"))) {
+ info->CRT2Position = radeonClone;
+ /*info->CRT2IsScrn0 = FALSE; */
+ info->CRT2IsScrn0 = TRUE;
+ }
+ else {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "\"%s\" is not a valid parameter for Option \"CRT2Position\"\n", strptr);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Valid parameters are \"RightOf\", \"LeftOf\", \"Above\", \"Below\", or \"Clone\"\n");
+ }
+ }
+ strptr = (char *)xf86GetOptValString(info->Options, OPTION_METAMODES);
+ if(strptr) {
+ info->MetaModes = xalloc(strlen(strptr) + 1);
+ if(info->MetaModes) memcpy(info->MetaModes, strptr, strlen(strptr) + 1);
+ }
+ strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2HSYNC);
+ if(strptr) {
+ info->CRT2HSync = xalloc(strlen(strptr) + 1);
+ if(info->CRT2HSync) memcpy(info->CRT2HSync, strptr, strlen(strptr) + 1);
+ }
+ strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2VREFRESH);
+ if(strptr) {
+ info->CRT2VRefresh = xalloc(strlen(strptr) + 1);
+ if(info->CRT2VRefresh) memcpy(info->CRT2VRefresh, strptr, strlen(strptr) + 1);
+ }
+
+ if(xf86GetOptValBool(info->Options, OPTION_NORADEONXINERAMA, &val)) {
+ if (val)
+ info->UseRADEONXinerama = FALSE;
+ }
+ if(info->UseRADEONXinerama) {
+ if(xf86GetOptValBool(info->Options, OPTION_CRT2ISSCRN0, &val)) {
+ if(val) info->CRT2IsScrn0 = TRUE;
+ else info->CRT2IsScrn0 = FALSE;
+ }
+ }
+ strptr = (char *)xf86GetOptValString(info->Options, OPTION_MERGEDDPI);
+ if(strptr) {
+ int val1 = 0, val2 = 0;
+ sscanf(strptr, "%d %d", &val1, &val2);
+ if(val1 && val2) {
+ info->MergedFBXDPI = val1;
+ info->MergedFBYDPI = val2;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, mybadparm, strptr, "MergedDPI");
+ }
+ }
+ }
+
+ if(info->MergedFB) {
+ /* fill in monitor */
+ info->CRT2pScrn->monitor = xalloc(sizeof(MonRec));
+ if(info->CRT2pScrn->monitor) {
+ DisplayModePtr tempm = NULL, currentm = NULL, newm = NULL;
+ memcpy(info->CRT2pScrn->monitor, pScrn->monitor, sizeof(MonRec));
+ info->CRT2pScrn->monitor->DDC = NULL;
+ info->CRT2pScrn->monitor->Modes = NULL;
+ info->CRT2pScrn->monitor->id = "CRT2 Monitor";
+ tempm = pScrn->monitor->Modes;
+ while(tempm) {
+ if(!(newm = xalloc(sizeof(DisplayModeRec)))) break;
+ memcpy(newm, tempm, sizeof(DisplayModeRec));
+ if(!(newm->name = xalloc(strlen(tempm->name) + 1))) {
+ xfree(newm);
+ break;
+ }
+ strcpy(newm->name, tempm->name);
+ if(!info->CRT2pScrn->monitor->Modes)
+ info->CRT2pScrn->monitor->Modes = newm;
+ if(currentm) {
+ currentm->next = newm;
+ newm->prev = currentm;
+ }
+ currentm = newm;
+ tempm = tempm->next;
+ }
+
+ /* xf86SetDDCproperties(info->CRT2pScrn, pRADEONEnt->MonInfo2); */
+ info->CRT2pScrn->monitor->DDC = pRADEONEnt->MonInfo2;
+ if (default_range) {
+ RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, default_hsync, MAX_HSYNC);
+ RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, default_vrefresh, MAX_VREFRESH);
+ }
+ if(info->CRT2HSync) {
+ info->CRT2pScrn->monitor->nHsync =
+ RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, info->CRT2HSync, MAX_HSYNC);
+ }
+ if(info->CRT2VRefresh) {
+ info->CRT2pScrn->monitor->nVrefresh =
+ RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, info->CRT2VRefresh, MAX_VREFRESH);
+ }
+
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to allocate memory for CRT2 monitor, MergedFB mode disabled.\n");
+ if(info->CRT2pScrn) xfree(info->CRT2pScrn);
+ info->CRT2pScrn = NULL;
+ info->MergedFB = FALSE;
+ }
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 10:58:10 +0000