R300/R500: clean up magic numbers in render code

1 files changed, 127 insertions, 44 deletions

diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 1d95600..b00c013 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -976,37 +976,110 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 
     RADEON_SWITCH_TO_3D();
 
-    /* setup the vertex shader */
+    /* setup the VAP */
 
     if (has_tcl) {
 	BEGIN_ACCEL(28);
-	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
-	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
-	OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456);
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+	OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
+				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
+				      (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
     } else {
 	BEGIN_ACCEL(10);
-	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 1<<8);
-	OUT_ACCEL_REG(R300_VAP_CNTL, 0x14045a);
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+	OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
+				      (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
     }
 
-    OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300);
-    OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
+    OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+    OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
 
     if (has_tcl) {
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
+		       (0 << R300_DST_VEC_LOC_0_SHIFT) |
+		       R300_SIGNED_0 |
+		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
+		       (10 << R300_DST_VEC_LOC_1_SHIFT) |
+		       R300_SIGNED_1));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
+		       (11 << R300_DST_VEC_LOC_2_SHIFT) |
+		       R300_LAST_VEC_2 |
+		       R300_SIGNED_2));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_1_SHIFT)));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_2_SHIFT)));
     } else {
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x46014001);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6701);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0x3b083b08);
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0x3b08);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
+		       (0 << R300_DST_VEC_LOC_0_SHIFT) |
+		       R300_SIGNED_0 |
+		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
+		       (6 << R300_DST_VEC_LOC_1_SHIFT) |
+		       R300_SIGNED_1));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
+		       (7 << R300_DST_VEC_LOC_2_SHIFT) |
+		       R300_LAST_VEC_2 |
+		       R300_SIGNED_2));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+			<< R300_WRITE_ENA_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+			<< R300_WRITE_ENA_1_SHIFT)));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+			<< R300_WRITE_ENA_2_SHIFT)));
     }
 
+    /* setup the vertex shader */
     if (has_tcl) {
-	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
-	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+		      ((0 << R300_PVS_FIRST_INST_SHIFT) |
+		       (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+		       (1 << R300_PVS_LAST_INST_SHIFT)));
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+		      (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
@@ -1016,33 +1089,41 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
 	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
-	
-	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
-	
+
+	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+
 	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
 	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
 	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
 	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
-	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
+	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
     }
-    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
-    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2);
+    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
+    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
+		  ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+		   (2 << R300_TEX_1_COMP_CNT_SHIFT)));
 
     FINISH_ACCEL();
 
+    /* setup pixel shader */
     if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
-      /* setup pixel shader */
       BEGIN_ACCEL(16);
-      OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
+      OUT_ACCEL_REG(R300_RS_COUNT,
+		    ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+		     R300_RS_COUNT_HIRES_EN));
       OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
-      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0);
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
       OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
-      OUT_ACCEL_REG(R300_US_CONFIG, 0x8);
-      OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
-      OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040);
-      OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0);
-      OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0);
-      OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0);
+      OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
+      OUT_ACCEL_REG(R300_US_CODE_OFFSET,
+		    (R300_ALU_CODE_OFFSET(0) |
+		     R300_ALU_CODE_SIZE(1) |
+		     R300_TEX_CODE_OFFSET(0) |
+		     R300_TEX_CODE_SIZE(1)));
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0);
       OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
       OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
       OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
@@ -1052,19 +1133,21 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
       FINISH_ACCEL();
     } else {
       BEGIN_ACCEL(23);
-      OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
+      OUT_ACCEL_REG(R300_RS_COUNT,
+		    ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+		     R300_RS_COUNT_HIRES_EN));
       OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 		    (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 
-      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0x0);
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
       OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
-      OUT_ACCEL_REG(R300_US_CONFIG, 0x2);
-      OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
-      OUT_ACCEL_REG(R500_US_FC_CTRL, 0x0);
-      OUT_ACCEL_REG(R500_US_CODE_ADDR, 0x10000);
-      OUT_ACCEL_REG(R500_US_CODE_RANGE, 0x10000);
-      OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0x0);
-      OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0x0);
+      OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
+      OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+      OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
+      OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
+      OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
       // 7807
       OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | 
 		    R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK);
@@ -1112,7 +1195,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 
     blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
     OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
-    OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0x0);
+    OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
 
 #if 0
     /* IN operator: Multiply src by mask components or mask alpha.
@@ -1320,7 +1403,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 	    xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
 
     if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
     }