diff options
| author | Alex Deucher <alex@botch2.(none)> | 2007-09-20 23:49:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.(none)> | 2007-09-20 23:49:57 -0400 |
| commit | c72a365386e19f9257db041d44b09ad499cc9f6a (patch) | |
| tree | 85c21c996d0ccd627178952b68d51b8219e9844d /src/radeon_output.c | |
| parent | 5e4d98470b6412a686883c554e7eb7badbe78c4d (diff) | |
RADEON: fix up dvo support (still no external chip init)
Diffstat (limited to 'src/radeon_output.c')
| -rw-r--r-- | src/radeon_output.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/src/radeon_output.c b/src/radeon_output.c index f9a21bb..8b7ae08 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -766,7 +766,7 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary) { ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); if (pScrn->rgbBits == 8) @@ -776,26 +776,23 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); + save->fp2_gen_cntl &= ~(RADEON_FP2_ON | + RADEON_FP2_DVO_EN | + RADEON_FP2_DVO_RATE_SEL_SDR); if (IsPrimary) { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_EN | - RADEON_FP2_DVO_RATE_SEL_SDR); - if (mode->Flags & RADEON_USE_RMX) - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; + save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; + if (mode->Flags & RADEON_USE_RMX) + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; } else { - save->fp2_gen_cntl &= ~(RADEON_FP2_SRC_SEL_CRTC2 | - RADEON_FP2_DVO_RATE_SEL_SDR); - } + save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; + } } else { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); + save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; } else { - save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR); save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; } } |