RADEON: more tv out fixes and clean up

4 files changed, 52 insertions, 53 deletions

diff --git a/src/radeon.h b/src/radeon.h
index a778cb8..bf60ab6 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -330,6 +330,7 @@ typedef struct {
     CARD32 	      tv_data_delay_b;
     CARD32 	      tv_dac_cntl;
     CARD32 	      tv_pll_cntl;
+    CARD32 	      tv_pll_cntl1;
     CARD32	      tv_pll_fine_cntl;
     CARD32 	      tv_modulator_cntl1;
     CARD32 	      tv_modulator_cntl2;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index c822937..57bb0bb 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4403,15 +4403,6 @@ static void RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore
     hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
     vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
 
-    OUTREG(RADEON_TV_MASTER_CNTL, (RADEON_TV_ASYNC_RST
-				   | RADEON_CRT_ASYNC_RST
-				   | RADEON_RESTART_PHASE_FIX
-				   | RADEON_CRT_FIFO_CE_EN
-				   | RADEON_TV_FIFO_CE_EN
-				   | RADEON_TV_ON));
-
-    /*OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl | RADEON_TV_ON);*/
-
     for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) {
 	tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]);
 	RADEONWriteTVFIFO(pScrn, hTable, tmp);
@@ -4511,12 +4502,9 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 
     ErrorF("Entering Restore TV\n");
 
-    OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl | RADEON_TV_ON);
-
     OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
 				   | RADEON_TV_ASYNC_RST
 				   | RADEON_CRT_ASYNC_RST
-				   | RADEON_RESTART_PHASE_FIX
 				   | RADEON_TV_FIFO_ASYNC_RST));
 
     /* Temporarily turn the TV DAC off */
@@ -4534,8 +4522,7 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 
     OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
 				   | RADEON_TV_ASYNC_RST
-				   | RADEON_CRT_ASYNC_RST
-				   | RADEON_RESTART_PHASE_FIX));
+				   | RADEON_CRT_ASYNC_RST));
 
     ErrorF("Restore TV Restarts\n");
     RADEONRestoreTVRestarts(pScrn, restore);
@@ -4545,8 +4532,7 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
   
 
     OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
-				   | RADEON_TV_ASYNC_RST
-				   | RADEON_RESTART_PHASE_FIX));
+				   | RADEON_TV_ASYNC_RST));
 
     ErrorF("Restore TV standard\n");
     RADEONRestoreTVOutputStd(pScrn, restore);
@@ -5305,6 +5291,7 @@ static void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
     save->tv_y_saw_tooth_cntl = INREG(RADEON_TV_Y_SAW_TOOTH_CNTL);
 
     save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL);
+    save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1);
 
     ErrorF("Save TV timing tables\n");
 
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 4e4d874..9eae40d 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3141,6 +3141,8 @@
 #       define RADEON_RGB_SRC_SEL_RMX		  (1 <<  8)
 #       define RADEON_RGB_SRC_SEL_CRTC2		  (2 <<  8)
 #       define RADEON_RGB_CONVERT_BY_PASS	  (1 << 10)
+#       define RADEON_UVRAM_READ_MARGIN_SHIFT	  16
+#       define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT	  20
 #	define RADEON_TVOUT_SCALE_EN 		  (1 << 26)
 #define RADEON_TV_SYNC_CNTL                          0x0808
 #       define RADEON_SYNC_OE                     (1 <<  0)
@@ -3211,6 +3213,9 @@
 #	define RADEON_SLEW_RATE_LIMIT		 (1 << 23)
 #       define RADEON_CY_FILT_BLEND_SHIFT        28
 #define RADEON_TV_MODULATOR_CNTL2                    0x0874
+#       define RADEON_TV_U_BURST_LEVEL_MASK     0x1ff
+#       define RADEON_TV_V_BURST_LEVEL_MASK     0x1ff
+#       define RADEON_TV_V_BURST_LEVEL_SHIFT    16
 #define RADEON_TV_CRC_CNTL                           0x0890
 #define RADEON_TV_UV_ADR                             0x08ac
 #	define RADEON_MAX_UV_ADR_MASK		 0x000000ff
@@ -3242,6 +3247,10 @@
 #       define RADEON_TVPLL_RESET                (1 <<  1)
 #       define RADEON_TVPLL_SLEEP                (1 <<  3)
 #       define RADEON_TVPLL_REFCLK_SEL           (1 <<  4)
+#       define RADEON_TVPCP_SHIFT                8
+#       define RADEON_TVPCP_MASK                 (7 << 8)
+#       define RADEON_TVPVG_SHIFT                11
+#       define RADEON_TVPVG_MASK                 (7 << 11)
 #       define RADEON_TVPDC_SHIFT                14
 #       define RADEON_TVPDC_MASK                 (3 << 14)
 #       define RADEON_TVPLL_TEST_DIS             (1 << 31)
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 73bf34d..1f61250 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -205,8 +205,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];
@@ -257,7 +256,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
      */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-	radeon_output->tvStd == TV_STD_PAL_M||
+	radeon_output->tvStd == TV_STD_PAL_M ||
 	radeon_output->tvStd == TV_STD_PAL_60)
 	vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(NTSC_TV_LINES_PER_FRAME);
     else
@@ -280,8 +279,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
     /* Compute H_INC from hSize */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-	radeon_output->tvStd == TV_STD_PAL_M ||
-	radeon_output->tvStd == TV_STD_PAL_60)
+	radeon_output->tvStd == TV_STD_PAL_M)
 	hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) /
 			(radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
     else
@@ -314,8 +312,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-	radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+	radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];
@@ -332,10 +329,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
     save->tv_linear_gain_settings = (0x100 << RADEON_UV_GAIN_SHIFT) |
 	                            (0x100 << RADEON_Y_GAIN_SHIFT);
 
-    save->tv_master_cntl = (RADEON_RESTART_PHASE_FIX
-			    | RADEON_VIN_ASYNC_RST
-			    | RADEON_AUD_ASYNC_RST
-			    | RADEON_DVS_ASYNC_RST
+    save->tv_master_cntl = (RADEON_VIN_ASYNC_RST
 			    | RADEON_CRT_FIFO_CE_EN
 			    | RADEON_TV_FIFO_CE_EN
 			    | RADEON_TV_ON);
@@ -343,24 +337,32 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
     if (!IS_R300_VARIANT)
 	save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
 
+    if (radeon_output->tvStd == TV_STD_NTSC ||
+	radeon_output->tvStd == TV_STD_NTSC_J)
+	save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
+
     save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT
 	                       | RADEON_SYNC_TIP_LEVEL
 	                       | RADEON_YFLT_EN
 	                       | RADEON_UVFLT_EN
-	                       | (0x3b << RADEON_BLANK_LEVEL_SHIFT)
-	                       | (0x6 << RADEON_CY_FILT_BLEND_SHIFT);
+	                       | (2 << RADEON_CY_FILT_BLEND_SHIFT);
 
     if (radeon_output->tvStd == TV_STD_NTSC ||
-	radeon_output->tvStd == TV_STD_NTSC_J ||
-	radeon_output->tvStd == TV_STD_PAL_M ||
-	radeon_output->tvStd == TV_STD_PAL_60 ||
-	radeon_output->tvStd == TV_STD_SCART_PAL) {
-	save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT);
-	save->tv_modulator_cntl2 = 0x00000191;
+	radeon_output->tvStd == TV_STD_NTSC_J) {
+	save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT)
+	                            | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+	save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
+	    ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+    } else if (radeon_output->tvStd == TV_STD_SCART_PAL) {
+	save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
+	save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
+	    ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
     } else {
 	save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN
-	                            | (0x3b << RADEON_SET_UP_LEVEL_SHIFT);
-	save->tv_modulator_cntl2 = 0x003e01b2;
+	                            | (0x3b << RADEON_SET_UP_LEVEL_SHIFT)
+	                            | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+	save->tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
+	    ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
     }
 
     save->pll_test_cntl = 0;
@@ -370,8 +372,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
 				 | RADEON_CMP_BLU_EN
 				 | RADEON_DAC_DITHER_EN);
 
-    save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN | RADEON_TVOUT_SCALE_EN
-			 | (0x0b << 16) | (0x07 << 20));
+    save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
+			 | RADEON_TVOUT_SCALE_EN
+			 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
+			 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT));
 
     if (IsPrimary) {
 	if (radeon_output->Flags & RADEON_USE_RMX)
@@ -445,9 +449,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
     save->tv_dac_cntl = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | (8 << 16) | (6 << 20);
 
     if (radeon_output->tvStd == TV_STD_NTSC ||
-        radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_NTSC_J)
 	save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
     else
 	save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
@@ -468,9 +470,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
 #endif
 
     if (radeon_output->tvStd == TV_STD_NTSC ||
-        radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_NTSC_J)
 	save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) |
 	    (((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
 	    ((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
@@ -483,6 +483,12 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
 	    (((PAL_TV_PLL_N >> 8) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
 	    ((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
 
+    save->tv_pll_cntl1 =  (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
+			   ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
+			   ((1 & RADEON_TVPDC_MASK)<< RADEON_TVPDC_SHIFT) |
+			   RADEON_TVCLK_SRC_SEL_TVPLL |
+			   RADEON_TVPLL_TEST_DIS);
+
     save->tv_upsamp_and_gain_cntl = RADEON_YUPSAMP_EN | RADEON_UVUPSAMP_EN;
 
     save->tv_uv_adr = 0xc8;
@@ -595,8 +601,7 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];
@@ -628,8 +633,7 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];
@@ -682,8 +686,7 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];
@@ -715,8 +718,7 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
     /* FIXME: need to revisit this when we add more modes */
     if (radeon_output->tvStd == TV_STD_NTSC ||
 	radeon_output->tvStd == TV_STD_NTSC_J ||
-        radeon_output->tvStd == TV_STD_PAL_M ||
-        radeon_output->tvStd == TV_STD_PAL_60)
+        radeon_output->tvStd == TV_STD_PAL_M)
 	constPtr = &availableTVModes[0];
     else
 	constPtr = &availableTVModes[1];