rs690: initial rs690 rotate

suffers same problem as r500 with clipping

3 files changed, 56 insertions, 34 deletions

diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index a626bbd..82825b7 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -57,7 +57,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
     info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
 
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
 	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
@@ -134,11 +134,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
 	OUT_ACCEL_REG(R300_SC_SCISSOR0, 0x0);
 	OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x3ffffff);
-	if (IS_AVIVO_VARIANT) {
-		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x0);
+	if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
+		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
 		OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
 	} else {
-		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
+		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x0);
 		OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
 	}
 	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index ce50dfd..6e22bb5 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -533,11 +533,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
 
 #ifdef RENDER
     if (info->RenderAccel) {
-	if ((info->ChipFamily >= CHIP_FAMILY_RS690) ||
+	if ((info->ChipFamily >= CHIP_FAMILY_R600) ||
 	    (info->ChipFamily == CHIP_FAMILY_RS400))
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
 			       "unsupported on XPRESS, R500 and newer cards.\n");
-	else if (IS_R300_VARIANT || info->ChipFamily < CHIP_FAMILY_RS690) {
+	else if (IS_R300_VARIANT || info->ChipFamily <= CHIP_FAMILY_RS690) {
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
 			       "enabled for R300 type cards.\n");
 		info->exa->CheckComposite = R300CheckComposite;
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 2213a32..f8f6600 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -937,6 +937,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     CARD32 txenable, colorpitch;
     CARD32 blendcntl;
     int pixel_shift;
+    int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
     ACCEL_PREAMBLE();
 
     TRACE;
@@ -976,40 +977,61 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     RADEON_SWITCH_TO_3D();
 
     /* setup the vertex shader */
-    BEGIN_ACCEL(26);
-    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
-    OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
-    OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456);
+
+    if (has_tcl) {
+	BEGIN_ACCEL(28);
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
+	OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456);
+    } else {
+	BEGIN_ACCEL(10);
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 1<<8);
+	OUT_ACCEL_REG(R300_VAP_CNTL, 0x14045a);
+    }
+
     OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300);
     OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
-    OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001);
-    OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01);
-    OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
-    OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688);
-    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
-    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
-    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
-
-    OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
+
+
+    if (has_tcl) {
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688);
+    } else {
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x46014001);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6701);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0x3b083b08);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0x3b08);
+    }
+
+    if (has_tcl) {
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+	
+	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
+	
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
+    }
     OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
     OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2);
 
-    OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
-    OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
-    OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
-    OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
-    OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
     FINISH_ACCEL();
 
-    if (IS_R300_VARIANT) {
+    if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
       /* setup pixel shader */
       BEGIN_ACCEL(16);
       OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
@@ -1030,7 +1052,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
       OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
       FINISH_ACCEL();
     } else {
-      BEGIN_ACCEL(22);
+      BEGIN_ACCEL(23);
       OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
       OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 		    (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));