diff options
127 files changed, 1222 insertions, 2128 deletions
diff --git a/man/ati.man b/man/ati.man index fa46bfc..abd7da3 100644 --- a/man/ati.man +++ b/man/ati.man @@ -1,4 +1,4 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.man,v 1.2 2001/01/27 18:20:46 dawes Exp $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.man,v 1.2 2001/01/27 18:20:46 dawes Exp $ .\" shorthand for double quote that works everywhere. .ds q \N'34' .TH ATI __drivermansuffix__ __vendorversion__ @@ -14,17 +14,17 @@ ati \- ATI video driver .fi .SH DESCRIPTION .B ati -is an __xservername__ driver for ATI video cards. +is an XFree86 driver for ATI video cards. THIS MAN PAGE NEEDS TO BE FILLED IN. .SH SUPPORTED HARDWARE The .B ati driver supports... .SH CONFIGURATION DETAILS -Please refer to __xconfigfile__(__filemansuffix__) for general configuration +Please refer to XF86Config(__filemansuffix__) for general configuration details. This section only covers configuration details specific to this driver. .SH "SEE ALSO" -__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) .SH AUTHORS Authors include: ... diff --git a/man/r128.man b/man/r128.man index 2c2c872..0bb990a 100644 --- a/man/r128.man +++ b/man/r128.man @@ -1,4 +1,4 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man,v 1.3 2001/06/01 02:10:05 dawes Exp $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man,v 1.4 2002/06/04 23:04:50 dawes Exp $ .\" shorthand for double quote that works everywhere. .ds q \N'34' .TH R128 __drivermansuffix__ __vendorversion__ @@ -14,7 +14,7 @@ r128 \- ATI Rage 128 video driver .fi .SH DESCRIPTION .B r128 -is an __xservername__ driver for ATI Rage 128 based video cards. It contains +is an XFree86 driver for ATI Rage 128 based video cards. It contains full support for 8, 15, 16 and 24 bit pixel depths, hardware acceleration of drawing primitives, hardware cursor, video modes up to 1800x1440 @ 70Hz, doublescan modes (e.g., 320x200 and 320x240), gamma @@ -26,7 +26,7 @@ The driver supports all ATI Rage 128 based video cards including the Rage Fury AGP 32MB, the XPERT 128 AGP 16MB and the XPERT 99 AGP 8MB. .SH CONFIGURATION DETAILS -Please refer to __xconfigfile__(__filemansuffix__) for general configuration +Please refer to XF86Config(__filemansuffix__) for general configuration details. This section only covers configuration details specific to this driver. .PP @@ -125,7 +125,7 @@ Enable or disable viewing offscreen cache memory. A development debug option. Default: off. .SH "SEE ALSO" -__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) .SH AUTHORS .nf Rickard E. (Rik) Faith \fIfaith@precisioninsight.com\fP diff --git a/man/radeon.man b/man/radeon.man index c09ac46..6eeec44 100644 --- a/man/radeon.man +++ b/man/radeon.man @@ -1,21 +1,21 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.0 2003/01/31 23:04:50 $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.0 2003/01/31 23:04:50 .ds q \N'34' .TH RADEON __drivermansuffix__ __vendorversion__ .SH NAME radeon \- ATI RADEON video driver .SH SYNOPSIS -.nf +.nf .B "Section \*qDevice\*q" .BI " Identifier \*q" devname \*q .B " Driver \*qradeon\*q" \ \ ... .B EndSection -.fi +.fi .SH DESCRIPTION .B radeon -is a __xservername__ driver for ATI RADEON based video cards. It contains -full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup, -flat panel, hardware 2D acceleration, hardware 3D acceleration +is a XFree86 driver for ATI RADEON based video cards. It contains +full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup, +flat panel, hardware 2D acceleration, hardware 3D acceleration (except R300 and IGP series cards), hardware cursor, XV extension, Xinerama extension. .SH SUPPORTED HARDWARE The @@ -32,7 +32,7 @@ Radeon 7000(VE), M6 Radeon IGP320(M) (2D only) .TP 12 .B RV200 -Radeon 7500, M7, FireGL 7800 +Radeon 7500, M7 .TP 12 .B RS200 Radeon IGP330(M)/IGP340(M) (2D only) @@ -44,85 +44,79 @@ Radeon Mobility 7000 IGP (2D only) Radeon 8500, 9100, FireGL 8800/8700 .TP 12 .B RV250 -Radeon 9000PRO/9000, M9 +Radeon 9000, M9 .TP 12 .B RS300 -Radeon 9100 IGP (2D only) +Radeon 9000 IGP (2D only) .TP 12 .B RV280 -Radeon 9200PRO/9200/9200SE, M9+ +Radeon 9200, M9+ .TP 12 .B R300 -Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1 (2D only) +Radeon 9700PRO/9700/9500PRO/9500, FireGL X1/Z1 (2D only) .TP 12 .B R350 -Radeon 9800PRO/9800SE/9800, FireGL X2 (2D only) -.TP 12 -.B R360 -Radeon 9800XT (2d only) +Radeon 9800PRO (2D only) .TP 12 .B RV350 -Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 (2D only) -.TP 12 -.B RV360 -Radeon 9600XT (2d only) +Radeon 9600PRO/9600, M10 (2D only) .SH CONFIGURATION DETAILS -Please refer to __xconfigfile__(__filemansuffix__) for general configuration +Please refer to XF86Config(__filemansuffix__) for general configuration details. This section only covers configuration details specific to this driver. -.PP +.PP The driver auto\-detects all device information necessary to initialize the card. However, if you have problems with auto\-detection, you can specify: -.PP +.PP .RS 4 VideoRam \- in kilobytes -.br +.br MemBase \- physical address of the linear framebuffer -.br +.br IOBase \- physical address of the MMIO registers -.br +.br ChipID \- PCI DEVICE ID .RE -.PP +.PP In addition, the following driver .B Options are supported: -.TP +.TP .BI "Option \*qSWcursor\*q \*q" boolean \*q Selects software cursor. The default is .B off. -.TP +.TP .BI "Option \*qNoAccel\*q \*q" boolean \*q -Enables or disables all hardware acceleration. +Enables or disables all hardware acceleration. .br The default is to .B enable hardware acceleration. -.TP +.TP .BI "Option \*qDac6Bit\*q \*q" boolean \*q Enables or disables the use of 6 bits per color component when in 8 bpp mode (emulates VGA mode). By default, all 8 bits per color component -are used. +are used. .br The default is .B off. -.TP +.TP .BI "Option \*qVideoKey\*q \*q" integer \*q This overrides the default pixel value for the YUV video overlay key. .br The default value is .B 0x1E. -.TP +.TP .BI "Option \*qUseFBDev\*q \*q" boolean \*q Enable or disable use of an OS\-specific framebuffer device interface (which is not supported on all OSs). See fbdevhw(__drivermansuffix__) -for further information. +for further information. .br The default is .B off. -.TP +.TP .BI "Option \*qAGPMode\*q \*q" integer \*q Set AGP data transfer rate. (used only when DRI is enabled) @@ -134,7 +128,7 @@ Set AGP data transfer rate. 4 \-\- x4 .br others \-\- invalid -.TP +.TP .BI "Option \*qAGPFastWrite\*q \*q" boolean \*q Enable AGP fast write. .br @@ -142,66 +136,34 @@ Enable AGP fast write. .br The default is .B off. -.TP -.BI "Option \*qBusType\*q \*q" string \*q -Used to replace previous ForcePCIMode option. -Should only be used when driver's bus detection is incorrect -or you want to force a AGP card to PCI mode. Should NEVER force -a PCI card to AGP bus. -.br -PCI \-\- PCI bus -.br -AGP \-\- AGP bus -.br -PCIE \-\- PCI Express (falls back to PCI at present) +.TP +.BI "Option \*qForcePCIMode\*q \*q" boolean \*q +Force to use PCI GART for DRI acceleration. .br (used only when DRI is enabled) .br The default is -.B auto detect. -.TP -.BI "Option \*qForcePCIMode\*q \*q" boolean \*q -Force to use PCI GART for DRI acceleration. -This option is deprecated in favor of the -.BI BusType -option above and will be removed in the next release. +.B off. .TP .BI "Option \*qDDCMode\*q \*q" boolean \*q Force to use the modes queried from the connected monitor. .br The default is .B off. -.TP -.BI "Option \*qDisplayPriority\*q \*q" string \*q -.br -Used to prevent flickering or tearing problem caused by display buffer underflow. -.br -AUTO \-\- Driver calculated (default). -.br -BIOS \-\- Remain unchanged from BIOS setting. - Use this if the calculation is not correct - for your card. -.br -HIGH \-\- Force to the highest priority. - Use this if you have problem with above options. - This may affect performence slightly. -.br -The default value is -.B AUTO. -.TP +.TP .BI "Option \*qMonitorLayout\*q \*q" string \*q -.br +.br This option is used to overwrite the detected monitor types. This is only required when driver makes a false detection. The possible monitor types are: -.br +.br NONE \-\- Not connected -.br +.br CRT \-\- Analog CRT monitor -.br +.br TMDS \-\- Desktop flat panel -.br -LVDS \-\- Laptop flat panel +.br +LVDS \-\- Lapto flat panel .br This option can be used in following format: .br @@ -210,28 +172,28 @@ Option "MonitorLayout" "[type on primary], [type on secondary]" For example, Option "MonitorLayout" "CRT, TMDS" Primary/Secondary head for dual\-head cards: -.br +.br (when only one port is used, it will be treated as the primary regardless) -.br +.br .B Primary head: -.br +.br DVI port on DVI+VGA cards -.br +.br LCD output on laptops -.br +.br Internal TMDS prot on DVI+DVI cards -.br +.br .B Secondary head: -.br +.br VGA port on DVI+VGA cards -.br +.br VGA port on laptops -.br +.br External TMDS port on DVI+DVI cards The default value is .B undefined. -.TP +.TP .BI "Option \*qCloneMode\*q \*q" "string" \*q Set the first mode for the secondary head. It can be different from the modes used for the primary head. If you don't @@ -242,76 +204,52 @@ For example, Option "CloneMode" "1024x768" .br The default value is .B undefined. -.TP +.TP .BI "Option \*qCloneHSync\*q \*q" "string" \*q -Set the horizontal sync range for the secondary monitor. +Set the horizontal sync range for the secondary monitor. It is not required if a DDC\-capable monitor is connected. .br For example, Option "CloneHSync" "30.0-86.0" .br The default value is .B undefined. -.TP +.TP .BI "Option \*qCloneVRefresh\*q \*q" "string" \*q -Set the vertical refresh range for the secondary monitor. +Set the vertical refresh range for the secondary monitor. It is not required if a DDC\-capable monitor is connected. .br For example, Option "CloneVRefresh" "50.0-120.0" .br The default value is .B undefined. -.TP +.TP .BI "Option \*qOverlayOnCRTC2\*q \*q" boolean \*q Force hardware overlay to clone head. .br The default value is .B off. -.TP +.TP .BI "Option \*qIgnoreEDID\*q \*q" boolean \*q Do not use EDID data for mode validation, but DDC is still used -for monitor detection. This is different from NoDDC option. +for monitor detection. This is different from NoDDC option. .br The default value is .B off. -.TP -.BI "Option \*qPanelSize\*q \*q" "string" \*q -Should only be used when driver cannot detect the correct panel size. -Apply to both desktop (TMDS) and laptop (LVDS) digital panels. -When a valid panel size is specified, the timings collected from -DDC and BIOS will not be used. If you have a panel with timings -different from that of a standard VESA mode, you have to provide -this information through the Modeline. -.br -For example, Option "PanelSize" "1400x1050" -.br -The default value is -.B none. -.TP +.TP .BI "Option \*qPanelOff\*q \*q" boolean \*q Disable panel output. Only used when clone is enabled. .br The default value is .B off. -.TP +.TP .BI "Option \*qEnablePageFlip\*q \*q" boolean \*q Enable page flipping for 3D acceleration. This will increase performance but not work correctly in some rare cases, hence the default is .B off. -.TP -.BI "Option \*qForceMinDotClock\*q \*q" frequency \*q -Override minimum dot clock. Some Radeon BIOSes report a minimum dot -clock unsuitable (too high) for use with television sets even when they -actually can produce lower dot clocks. If this is the case you can -override the value here. -.B Note that using this option may damage your hardware. -You have been warned. The -.B frequency -parameter may be specified as a float value with standard suffixes like -"k", "kHz", "M", "MHz". .SH SEE ALSO -__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) .SH AUTHORS -.nf +.nf Authors include: ... @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c,v 1.23 2003/04/25 14:37:35 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h,v 1.9 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiaccel.c b/src/atiaccel.c index 3c358cf..626cb34 100644 --- a/src/atiaccel.c +++ b/src/atiaccel.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c,v 1.13 2003/04/24 21:19:22 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiaccel.h b/src/atiaccel.h index e9faa33..74cbdec 100644 --- a/src/atiaccel.h +++ b/src/atiaccel.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h,v 1.5 2003/04/23 21:51:27 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiadapter.c b/src/atiadapter.c index 15f91bb..897788b 100644 --- a/src/atiadapter.c +++ b/src/atiadapter.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c,v 1.17 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiadapter.h b/src/atiadapter.h index 5cfb79c..8db366e 100644 --- a/src/atiadapter.h +++ b/src/atiadapter.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h,v 1.10 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiadjust.c b/src/atiadjust.c index 097c21d..3db016d 100644 --- a/src/atiadjust.c +++ b/src/atiadjust.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c,v 1.15 2003/04/23 21:51:27 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiadjust.h b/src/atiadjust.h index b5cddf0..0ac15ae 100644 --- a/src/atiadjust.h +++ b/src/atiadjust.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h,v 1.8 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiaudio.c b/src/atiaudio.c index a154098..ada8330 100644 --- a/src/atiaudio.c +++ b/src/atiaudio.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c,v 1.1 2003/07/24 22:08:27 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiaudio.h b/src/atiaudio.h index f2eb94c..19080d2 100644 --- a/src/atiaudio.h +++ b/src/atiaudio.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h,v 1.1 2003/07/24 22:08:27 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atibank.c b/src/atibank.c index cd94824..82d591a 100644 --- a/src/atibank.c +++ b/src/atibank.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c,v 1.12 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atibank.h b/src/atibank.h index 071dc22..43a91ac 100644 --- a/src/atibank.h +++ b/src/atibank.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h,v 1.8 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atibus.c b/src/atibus.c index 9eb099c..c06c696 100644 --- a/src/atibus.c +++ b/src/atibus.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c,v 1.18 2003/01/22 21:44:10 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atibus.h b/src/atibus.h index 44dcc72..c5f35e0 100644 --- a/src/atibus.h +++ b/src/atibus.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h,v 1.11 2003/01/01 19:16:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atichip.c b/src/atichip.c index 4d4861b..f1fa25e 100644 --- a/src/atichip.c +++ b/src/atichip.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c,v 1.38tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c,v 1.35 2003/07/02 17:31:28 martin Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -101,8 +101,6 @@ const char *ATIChipNames[] = "ATI Radeon 9700/9500", "ATI Radeon 9600", "ATI Radeon 9800", - "ATI Radeon 9800XT", - "ATI unknown Radeon", "ATI Rage HDTV" }; @@ -675,11 +673,14 @@ ATIChipID case NewChipID('Q', 'X'): return ATI_CHIP_RV200; + case NewChipID('I', 'd'): + case NewChipID('I', 'e'): case NewChipID('I', 'f'): case NewChipID('I', 'g'): return ATI_CHIP_RV250; case NewChipID('L', 'd'): + case NewChipID('L', 'e'): case NewChipID('L', 'f'): case NewChipID('L', 'g'): return ATI_CHIP_RADEONMOBILITY9; @@ -690,12 +691,14 @@ ATIChipID case NewChipID('Y', '\''): case NewChipID('Y', 'a'): - case NewChipID('Y', 'b'): - case NewChipID('Y', 'd'): + case NewChipID('I', 'b'): + case NewChipID('I', 'c'): return ATI_CHIP_RV280; - case NewChipID('\\', 'a'): - case NewChipID('\\', 'c'): + case NewChipID('Y', 'h'): + case NewChipID('Y', 'i'): + case NewChipID('Y', 'j'): + case NewChipID('Y', 'k'): return ATI_CHIP_RADEONMOBILITY9PLUS; case NewChipID('A', 'D'): @@ -708,40 +711,24 @@ ATIChipID case NewChipID('N', 'G'): return ATI_CHIP_R300; - case NewChipID('A', 'H'): - case NewChipID('A', 'I'): - case NewChipID('A', 'J'): case NewChipID('A', 'K'): case NewChipID('N', 'H'): - case NewChipID('N', 'I'): case NewChipID('N', 'K'): return ATI_CHIP_R350; + case NewChipID('N', 'P'): case NewChipID('A', 'P'): - case NewChipID('A', 'Q'): case NewChipID('A', 'R'): - case NewChipID('A', 'S'): - case NewChipID('A', 'T'): - case NewChipID('A', 'V'): - case NewChipID('N', 'P'): - case NewChipID('N', 'Q'): - case NewChipID('N', 'R'): - case NewChipID('N', 'S'): - case NewChipID('N', 'T'): - case NewChipID('N', 'V'): return ATI_CHIP_RV350; - case NewChipID('N', 'J'): - return ATI_CHIP_R360; - case NewChipID('H', 'D'): return ATI_CHIP_HDTV; default: /* - * Treat anything else as an unknown Radeon. Please keep the above - * up-to-date however, as it serves as a central chip list. + * I'd say it's a Rage128 or a Radeon here, except that I don't + * support them. */ - return ATI_CHIP_Radeon; + return ATI_CHIP_Mach64; } } diff --git a/src/atichip.h b/src/atichip.h index e47947d..96d56ba 100644 --- a/src/atichip.h +++ b/src/atichip.h @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h,v 1.26tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h,v 1.24 2003/07/02 17:31:29 martin Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -77,7 +77,7 @@ typedef enum ATI_CHIP_264LTPRO, /* Mach64 */ ATI_CHIP_264XL, /* Mach64 */ ATI_CHIP_MOBILITY, /* Mach64 */ - ATI_CHIP_Mach64, /* Last among Mach64's */ + ATI_CHIP_Mach64, /* Mach64 */ ATI_CHIP_RAGE128GL, /* Rage128 */ ATI_CHIP_RAGE128VR, /* Rage128 */ ATI_CHIP_RAGE128PROGL, /* Rage128 */ @@ -85,7 +85,7 @@ typedef enum ATI_CHIP_RAGE128PROULTRA, /* Rage128 */ ATI_CHIP_RAGE128MOBILITY3, /* Rage128 */ ATI_CHIP_RAGE128MOBILITY4, /* Rage128 */ - ATI_CHIP_Rage128, /* Last among Rage128's */ + ATI_CHIP_Rage128, /* Rage128 */ ATI_CHIP_RADEON, /* Radeon */ ATI_CHIP_RADEONVE, /* Radeon VE */ ATI_CHIP_RADEONMOBILITY6, /* Radeon M6 */ @@ -103,8 +103,6 @@ typedef enum ATI_CHIP_R300, /* R300 */ ATI_CHIP_RV350, /* RV350 */ ATI_CHIP_R350, /* R350 */ - ATI_CHIP_R360, /* R360 */ - ATI_CHIP_Radeon, /* Last among Radeon's */ ATI_CHIP_HDTV /* HDTV */ } ATIChipType; diff --git a/src/aticlock.c b/src/aticlock.c index 89a4180..e1201cb 100644 --- a/src/aticlock.c +++ b/src/aticlock.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c,v 1.21 2003/04/23 21:51:27 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticlock.h b/src/aticlock.h index 20e646d..641ba69 100644 --- a/src/aticlock.h +++ b/src/aticlock.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h,v 1.8 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticonfig.c b/src/aticonfig.c index cee9e18..3cad3e2 100644 --- a/src/aticonfig.c +++ b/src/aticonfig.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c,v 1.15tsi Exp $*/ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c,v 1.14 2003/04/30 21:43:31 tsi Exp $*/ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -34,7 +34,6 @@ */ typedef enum { - ATI_OPTION_BIOS_DISPLAY, /* Allow BIOS interference */ ATI_OPTION_CRT_SCREEN, /* Legacy negation of "PanelDisplay" */ ATI_OPTION_DEVEL, /* Intentionally undocumented */ ATI_OPTION_BLEND, /* Force horizontal blending of small modes */ @@ -57,13 +56,6 @@ ATIProcessOptions OptionInfoPtr PublicOption = xnfalloc(ATIPublicOptionSize); OptionInfoRec PrivateOption[] = { - { /* ON: Let BIOS change display(s) */ - ATI_OPTION_BIOS_DISPLAY, /* OFF: Don't */ - "biosdisplay", - OPTV_BOOLEAN, - {0, }, - FALSE - }, { /* Negation of "PanelDisplay" public option */ ATI_OPTION_CRT_SCREEN, "crtscreen", @@ -71,13 +63,6 @@ ATIProcessOptions {0, }, FALSE }, - { /* ON: Ease exploration of loose ends */ - ATI_OPTION_DEVEL, /* OFF: Fit for public consumption */ - "tsi", - OPTV_BOOLEAN, - {0, }, - FALSE - }, { /* ON: Horizontally blend most modes */ ATI_OPTION_BLEND, /* OFF: Use pixel replication more often */ "lcdblend", @@ -92,6 +77,13 @@ ATIProcessOptions {0, }, FALSE }, + { /* ON: Ease exploration of loose ends */ + ATI_OPTION_DEVEL, /* OFF: Fit for public consumption */ + "tsi", + OPTV_BOOLEAN, + {0, }, + FALSE + }, { -1, NULL, @@ -104,7 +96,6 @@ ATIProcessOptions (void)memcpy(PublicOption, ATIPublicOptions, ATIPublicOptionSize); # define Accel PublicOption[ATI_OPTION_ACCEL].value.bool -# define BIOSDisplay PrivateOption[ATI_OPTION_BIOS_DISPLAY].value.bool # define Blend PrivateOption[ATI_OPTION_BLEND].value.bool # define CRTDisplay PublicOption[ATI_OPTION_CRT_DISPLAY].value.bool # define CRTScreen PrivateOption[ATI_OPTION_CRT_SCREEN].value.bool @@ -185,7 +176,6 @@ ATIProcessOptions /* Move option values into driver private structure */ pATI->OptionAccel = Accel; - pATI->OptionBIOSDisplay = BIOSDisplay; pATI->OptionBlend = Blend; pATI->OptionCRTDisplay = CRTDisplay; pATI->OptionCSync = CSync; diff --git a/src/aticonfig.h b/src/aticonfig.h index 242ecef..bf9c24b 100644 --- a/src/aticonfig.h +++ b/src/aticonfig.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h,v 1.5 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticonsole.c b/src/aticonsole.c index 80062d4..b025cdd 100644 --- a/src/aticonsole.c +++ b/src/aticonsole.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c,v 1.22 2003/11/13 18:42:47 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c,v 1.21 2003/07/24 22:08:27 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -336,8 +336,7 @@ ATIFreeScreen ScrnInfoPtr pScreenInfo = xf86Screens[iScreen]; ATIPtr pATI = ATIPTR(pScreenInfo); - if (pATI->Closeable || (serverGeneration > 1)) - ATII2CFreeScreen(iScreen); + ATII2CFreeScreen(iScreen); if (pATI->Closeable) (void)(*pScreen->CloseScreen)(iScreen, pScreen); diff --git a/src/aticonsole.h b/src/aticonsole.h index da71c65..8157d83 100644 --- a/src/aticonsole.h +++ b/src/aticonsole.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h,v 1.9 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticrtc.h b/src/aticrtc.h index ba2a7a1..9f6ec38 100644 --- a/src/aticrtc.h +++ b/src/aticrtc.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h,v 1.8 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticursor.c b/src/aticursor.c index 9846f22..a4837e4 100644 --- a/src/aticursor.c +++ b/src/aticursor.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c,v 1.4 2003/04/23 21:51:27 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/aticursor.h b/src/aticursor.h index 71d0a9a..9f8790d 100644 --- a/src/aticursor.h +++ b/src/aticursor.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h,v 1.3 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidac.c b/src/atidac.c index cf59556..1d3e943 100644 --- a/src/atidac.c +++ b/src/atidac.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c,v 1.18 2003/02/25 17:58:13 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidac.h b/src/atidac.h index 097858e..fc3b758 100644 --- a/src/atidac.h +++ b/src/atidac.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h,v 1.15 2003/01/01 19:16:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidecoder.c b/src/atidecoder.c index 60d3f9d..aee3741 100644 --- a/src/atidecoder.c +++ b/src/atidecoder.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidecoder.h b/src/atidecoder.h index 0c3cc5c..e88b89f 100644 --- a/src/atidecoder.h +++ b/src/atidecoder.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidga.c b/src/atidga.c index 81da7c9..9273f03 100644 --- a/src/atidga.c +++ b/src/atidga.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c,v 1.10 2003/04/23 21:51:27 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidga.h b/src/atidga.h index 1a93879..96664d9 100644 --- a/src/atidga.h +++ b/src/atidga.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h,v 1.7 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atidsp.c b/src/atidsp.c index bbab3e5..4cc2a05 100644 --- a/src/atidsp.c +++ b/src/atidsp.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c,v 1.21 2003/09/24 02:43:18 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c,v 1.20 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -74,7 +74,7 @@ ATIDSPPreInit pATI->XCLKFeedbackDivider = ATIMach64GetPLLReg(PLL_MCLK_FB_DIV); xf86DrvMsgVerb(iScreen, X_INFO, 2, - "Engine XCLK %.3f MHz; Refresh rate code %ld.\n", + "Engine XCLK %.3f MHz; Refresh rate code %d.\n", ATIDivide(pATI->XCLKFeedbackDivider * pATI->ReferenceNumerator, pATI->XCLKReferenceDivider * pATI->ClockDescriptor.MaxM * pATI->ReferenceDenominator, 1 - pATI->XCLKPostDivider, 0) / diff --git a/src/atidsp.h b/src/atidsp.h index 91438cc..d6881cf 100644 --- a/src/atidsp.h +++ b/src/atidsp.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h,v 1.10 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atii2c.c b/src/atii2c.c index 331bd70..b884e59 100644 --- a/src/atii2c.c +++ b/src/atii2c.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c,v 1.3 2003/11/10 18:41:20 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c,v 1.2 2003/08/29 21:07:57 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -113,7 +113,7 @@ /* - * ATII2CAddress -- + * ATII2CAddress -- * * This function puts a Start bit and an 8-bit address on the I2C bus. */ diff --git a/src/atii2c.h b/src/atii2c.h index d33ba23..ddc0d97 100644 --- a/src/atii2c.h +++ b/src/atii2c.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiident.c b/src/atiident.c index 91dd114..1fb9dbb 100644 --- a/src/atiident.c +++ b/src/atiident.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c,v 1.11 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiident.h b/src/atiident.h index 1c5969a..74677c5 100644 --- a/src/atiident.h +++ b/src/atiident.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h,v 1.10 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiio.h b/src/atiio.h index 9405033..f6f871b 100644 --- a/src/atiio.h +++ b/src/atiio.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h,v 1.14 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiload.c b/src/atiload.c index e00f216..a7eebd1 100644 --- a/src/atiload.c +++ b/src/atiload.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c,v 1.15 2003/08/29 21:07:57 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiload.h b/src/atiload.h index a506f34..a695579 100644 --- a/src/atiload.h +++ b/src/atiload.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h,v 1.6 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atilock.c b/src/atilock.c index a6d5cda..b07744d 100644 --- a/src/atilock.c +++ b/src/atilock.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c,v 1.20tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c,v 1.19 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -143,7 +143,7 @@ ATIUnlock /* * Prevent BIOS initiated display switches on dual-CRT controllers. */ - if (!pATI->OptionBIOSDisplay && (pATI->Chip != ATI_CHIP_264XL)) + if (pATI->Chip != ATI_CHIP_264XL) { pATI->LockData.scratch_reg3 = inr(SCRATCH_REG3); outr(SCRATCH_REG3, @@ -566,7 +566,7 @@ ATILock if ((pATI->LCDPanelID >= 0) && (pATI->Chip != ATI_CHIP_264LT)) { outr(LCD_INDEX, pATI->LockData.lcd_index); - if (!pATI->OptionBIOSDisplay && (pATI->Chip != ATI_CHIP_264XL)) + if (pATI->Chip != ATI_CHIP_264XL) outr(SCRATCH_REG3, pATI->LockData.scratch_reg3); } if (pATI->Chip >= ATI_CHIP_264VTB) diff --git a/src/atilock.h b/src/atilock.h index 70c6393..9b94943 100644 --- a/src/atilock.h +++ b/src/atilock.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h,v 1.5 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64.c b/src/atimach64.c index f90f6f9..89ee7c9 100644 --- a/src/atimach64.c +++ b/src/atimach64.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c,v 1.52 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64.h b/src/atimach64.h index 34cea4a..dd2e9a9 100644 --- a/src/atimach64.h +++ b/src/atimach64.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h,v 1.17 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64accel.c b/src/atimach64accel.c index 6f2dba7..1202918 100644 --- a/src/atimach64accel.c +++ b/src/atimach64accel.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c,v 1.1 2003/04/23 21:51:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64accel.h b/src/atimach64accel.h index ff24b17..88f90a0 100644 --- a/src/atimach64accel.h +++ b/src/atimach64accel.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h,v 1.1 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64cursor.c b/src/atimach64cursor.c index 9d8816b..8cd76db 100644 --- a/src/atimach64cursor.c +++ b/src/atimach64cursor.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c,v 1.1 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64cursor.h b/src/atimach64cursor.h index b861f15..6439f13 100644 --- a/src/atimach64cursor.h +++ b/src/atimach64cursor.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h,v 1.1 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64i2c.c b/src/atimach64i2c.c index 10df61f..4cb565f 100644 --- a/src/atimach64i2c.c +++ b/src/atimach64i2c.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64i2c.h b/src/atimach64i2c.h index aa05af9..9930952 100644 --- a/src/atimach64i2c.h +++ b/src/atimach64i2c.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64io.c b/src/atimach64io.c index 5628ce7..b4fafd9 100644 --- a/src/atimach64io.c +++ b/src/atimach64io.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c,v 1.6 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64io.h b/src/atimach64io.h index a1c07b8..e4db52a 100644 --- a/src/atimach64io.h +++ b/src/atimach64io.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h,v 1.15 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimach64xv.c b/src/atimach64xv.c index 2923134..d45e306 100644 --- a/src/atimach64xv.c +++ b/src/atimach64xv.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c,v 1.7 2003/11/10 18:22:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c,v 1.6 2003/07/19 15:26:54 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -1438,7 +1438,7 @@ ATIMach64XVInitialiseAdaptor pAdaptor->PutImage = ATIMach64PutImage; pAdaptor->QueryImageAttributes = ATIMach64QueryImageAttributes; - REGION_NULL(pScreen, &pATI->VideoClip); + REGION_INIT(pScreen, &pATI->VideoClip, NullBox, 0); pATI->ActiveSurface = FALSE; if (ATIMach64XVAtomGeneration != serverGeneration) diff --git a/src/atimach64xv.h b/src/atimach64xv.h index 9204942..8d5c07c 100644 --- a/src/atimach64xv.h +++ b/src/atimach64xv.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h,v 1.1 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimisc.c b/src/atimisc.c index 8c8ae06..a84eac4 100644 --- a/src/atimisc.c +++ b/src/atimisc.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c,v 1.8tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c,v 1.7 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -35,7 +35,7 @@ static XF86ModuleVersionInfo ATIVersionRec = MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, - XORG_VERSION_CURRENT, + XF86_VERSION_CURRENT, ATI_VERSION_MAJOR, ATI_VERSION_MINOR, ATI_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, @@ -62,38 +62,8 @@ ATISetup if (!Inited) { /* Ensure main driver module is loaded, but not as a submodule */ - if (!xf86ServerIsOnlyDetecting()) - { - if (!LoaderSymbol(ATI_NAME)) - xf86LoadOneModule(ATI_DRIVER_NAME, Options); - - /* ati & atimisc module versions must match */ - do - { - XF86ModuleData *pModuleData = LoaderSymbol("atiModuleData"); - - if (pModuleData) - { - XF86ModuleVersionInfo *pModuleInfo = pModuleData->vers; - - if ((pModuleInfo->majorversion == ATI_VERSION_MAJOR) && - (pModuleInfo->minorversion == ATI_VERSION_MINOR) && - (pModuleInfo->patchlevel == ATI_VERSION_PATCH)) - break; - } - - xf86Msg(X_ERROR, - "\"ati\" and \"atimisc\" module versions must" - " match.\n"); - - if (ErrorMajor) - *ErrorMajor = (int)LDR_MISMATCH; - if (ErrorMinor) - *ErrorMinor = (int)LDR_MISMATCH; - - return NULL; - } while (0); - } + if (!xf86ServerIsOnlyDetecting() && !LoaderSymbol(ATI_NAME)) + xf86LoadOneModule(ATI_DRIVER_NAME, Options); /* * Tell loader about symbols from other modules that this module might diff --git a/src/atimode.c b/src/atimode.c index a723de9..02cf319 100644 --- a/src/atimode.c +++ b/src/atimode.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c,v 1.18 2004/01/05 16:42:03 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c,v 1.17 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -125,6 +125,7 @@ ATISwap seq4 = GetReg(SEQX, 0x04U); gra1 = GetReg(GRAX, 0x01U); gra3 = GetReg(GRAX, 0x03U); + gra4 = GetReg(GRAX, 0x04U); gra5 = GetReg(GRAX, 0x05U); gra6 = GetReg(GRAX, 0x06U); gra8 = GetReg(GRAX, 0x08U); @@ -364,7 +365,7 @@ ATIModeSave int Index; - /* Get back to bank 0 */ + /* Get bank to bank 0 */ (*pATIHW->SetBank)(pATI, 0); #endif /* AVOID_CPIO */ diff --git a/src/atimode.h b/src/atimode.h index 2cbc1db..63cb765 100644 --- a/src/atimode.h +++ b/src/atimode.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h,v 1.5 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimodule.c b/src/atimodule.c index a4393c9..ed6b621 100644 --- a/src/atimodule.c +++ b/src/atimodule.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c,v 1.16 2003/05/28 14:08:03 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -77,7 +77,7 @@ static XF86ModuleVersionInfo ATIVersionRec = MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, - XORG_VERSION_CURRENT, + XF86_VERSION_CURRENT, ATI_VERSION_MAJOR, ATI_VERSION_MINOR, ATI_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, diff --git a/src/atimodule.h b/src/atimodule.h index 1a203ae..833e421 100644 --- a/src/atimodule.h +++ b/src/atimodule.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h,v 1.9 2003/01/01 19:16:32 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atimono.h b/src/atimono.h index f050ceb..6325cbe 100644 --- a/src/atimono.h +++ b/src/atimono.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h,v 1.7 2003/01/01 19:16:33 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atioption.c b/src/atioption.c index 81b6d3b..6b84128 100644 --- a/src/atioption.c +++ b/src/atioption.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c,v 1.22 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atioption.h b/src/atioption.h index 53e2be4..2e629b8 100644 --- a/src/atioption.h +++ b/src/atioption.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h,v 1.12 2003/04/23 21:51:29 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atipreinit.c b/src/atipreinit.c index a3523da..71aa049 100644 --- a/src/atipreinit.c +++ b/src/atipreinit.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c,v 1.74 2003/12/22 17:48:09 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c,v 1.69 2003/08/23 17:10:42 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -1463,7 +1463,7 @@ ATIPreInit if (pATI->CPIO_VGAWonder) xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, - "VGA Wonder registers at I/O port 0x%04lX.\n", + "VGA Wonder registers at I/O port 0x%04X.\n", pATI->CPIO_VGAWonder); if (pATI->Coprocessor != ATI_CHIP_NONE) @@ -1549,8 +1549,8 @@ ATIPreInit { xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, "Driver does not support weight %d%d%d for depth %d.\n", - (int)pScreenInfo->weight.red, (int)pScreenInfo->weight.green, - (int)pScreenInfo->weight.blue, pScreenInfo->depth); + pScreenInfo->weight.red, pScreenInfo->weight.green, + pScreenInfo->weight.blue, pScreenInfo->depth); ATILock(pATI); ATIPrintNoiseIfRequested(pATI, BIOS, BIOSSize); ATIUnmapApertures(pScreenInfo->scrnIndex, pATI); @@ -1710,7 +1710,7 @@ ATIPreInit } else { - unsigned HDisplay, VDisplay; + int HDisplay, VDisplay; CARD8 ClockMask, PostMask; /* @@ -1749,24 +1749,21 @@ ATIPreInit if (!(pATIHW->crtc_gen_cntl & CRTC_EXT_DISP_EN)) { - unsigned HBlankStart, HSyncStart, HSyncEnd, HBlankEnd, HTotal; - unsigned VBlankStart, VSyncStart, VSyncEnd, VBlankEnd, VTotal; - pATIHW->clock = (inb(R_GENMO) & 0x0CU) >> 2; + pATIHW->crt[0] = GetReg(CRTX(pATI->CPIO_VGABase), 0x00U); pATIHW->crt[2] = GetReg(CRTX(pATI->CPIO_VGABase), 0x02U); pATIHW->crt[3] = GetReg(CRTX(pATI->CPIO_VGABase), 0x03U); + pATIHW->crt[4] = GetReg(CRTX(pATI->CPIO_VGABase), 0x04U); pATIHW->crt[5] = GetReg(CRTX(pATI->CPIO_VGABase), 0x05U); + pATIHW->crt[6] = GetReg(CRTX(pATI->CPIO_VGABase), 0x06U); pATIHW->crt[7] = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U); pATIHW->crt[9] = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U); + pATIHW->crt[16] = GetReg(CRTX(pATI->CPIO_VGABase), 0x10U); + pATIHW->crt[17] = GetReg(CRTX(pATI->CPIO_VGABase), 0x11U); pATIHW->crt[21] = GetReg(CRTX(pATI->CPIO_VGABase), 0x15U); pATIHW->crt[22] = GetReg(CRTX(pATI->CPIO_VGABase), 0x16U); - pATIHW->crtc_h_total_disp = inr(CRTC_H_TOTAL_DISP); - pATIHW->crtc_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); - pATIHW->crtc_v_total_disp = inr(CRTC_V_TOTAL_DISP); - pATIHW->crtc_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); - /* Switch to shadow registers */ if (pATI->Chip == ATI_CHIP_264LT) outr(LCD_GEN_CTRL, pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); @@ -1776,26 +1773,31 @@ ATIPreInit ATIMach64PutLCDReg(LCD_GEN_CNTL, pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); + pATIHW->shadow_vga[0] = + GetReg(CRTX(pATI->CPIO_VGABase), 0x00U); pATIHW->shadow_vga[2] = GetReg(CRTX(pATI->CPIO_VGABase), 0x02U); pATIHW->shadow_vga[3] = GetReg(CRTX(pATI->CPIO_VGABase), 0x03U); + pATIHW->shadow_vga[4] = + GetReg(CRTX(pATI->CPIO_VGABase), 0x04U); pATIHW->shadow_vga[5] = GetReg(CRTX(pATI->CPIO_VGABase), 0x05U); + pATIHW->shadow_vga[6] = + GetReg(CRTX(pATI->CPIO_VGABase), 0x06U); pATIHW->shadow_vga[7] = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U); pATIHW->shadow_vga[9] = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U); + pATIHW->shadow_vga[16] = + GetReg(CRTX(pATI->CPIO_VGABase), 0x10U); + pATIHW->shadow_vga[17] = + GetReg(CRTX(pATI->CPIO_VGABase), 0x11U); pATIHW->shadow_vga[21] = GetReg(CRTX(pATI->CPIO_VGABase), 0x15U); pATIHW->shadow_vga[22] = GetReg(CRTX(pATI->CPIO_VGABase), 0x16U); - pATIHW->shadow_h_total_disp = inr(CRTC_H_TOTAL_DISP); - pATIHW->shadow_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); - pATIHW->shadow_v_total_disp = inr(CRTC_V_TOTAL_DISP); - pATIHW->shadow_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); - /* * HSyncStart and HSyncEnd should equal their shadow * counterparts. Otherwise, due to a chip bug, the panel might @@ -1807,10 +1809,8 @@ ATIPreInit * * Note that this hardware bug does not affect the CRT output. */ - if (((pATIHW->crtc_h_sync_strt_wid ^ - pATIHW->shadow_h_sync_strt_wid) & - (CRTC_H_SYNC_STRT | CRTC_H_SYNC_STRT_HI | - CRTC_H_SYNC_WID))) + if ((pATIHW->crt[4] != pATIHW->shadow_vga[4]) || + ((pATIHW->crt[5] ^ pATIHW->shadow_vga[5]) & 0x1FU)) { xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_NOTICE, 0, "Invalid horizontal sync pulse timing detected in mode" @@ -1824,109 +1824,65 @@ ATIPreInit /* Merge in shadow registers as appropriate */ if (pATIHW->lcd_gen_ctrl & SHADOW_EN) { + pATIHW->crt[0] = pATIHW->shadow_vga[0]; pATIHW->crt[2] = pATIHW->shadow_vga[2]; pATIHW->crt[3] = pATIHW->shadow_vga[3]; + pATIHW->crt[4] = pATIHW->shadow_vga[4]; pATIHW->crt[5] = pATIHW->shadow_vga[5]; - /* XXX Does this apply to VGA? If so, what about the LT? */ - if ((pATI->Chip < ATI_CHIP_264LTPRO) || - !(pATIHW->config_panel & DONT_SHADOW_HEND)) - { - pATIHW->crtc_h_total_disp &= ~CRTC_H_DISP; - pATIHW->crtc_h_total_disp |= - pATIHW->shadow_h_total_disp & CRTC_H_DISP; - } - - pATIHW->crtc_h_total_disp &= ~CRTC_H_TOTAL; - pATIHW->crtc_h_total_disp |= - pATIHW->shadow_h_total_disp & CRTC_H_TOTAL; - pATIHW->crtc_h_sync_strt_wid = - pATIHW->shadow_h_sync_strt_wid; - - /* XXX Does this apply to VGA? */ - if (pATIHW->lcd_gen_ctrl & USE_SHADOWED_VEND) - { - pATIHW->crtc_v_total_disp &= ~CRTC_V_DISP; - pATIHW->crtc_v_total_disp |= - pATIHW->shadow_v_total_disp & CRTC_V_DISP; - } - if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) { - pATIHW->crt[7] = pATIHW->shadow_vga[7]; - pATIHW->crt[9] = pATIHW->shadow_vga[9]; + pATIHW->crt[6] = pATIHW->shadow_vga[6]; + pATIHW->crt[7] &= ~0x29U; + pATIHW->crt[7] |= pATIHW->shadow_vga[7] & 0x29U; + pATIHW->crt[9] &= ~0x20U; + pATIHW->crt[9] |= pATIHW->shadow_vga[9] & 0x20U; pATIHW->crt[21] = pATIHW->shadow_vga[21]; pATIHW->crt[22] = pATIHW->shadow_vga[22]; - - pATIHW->crtc_v_total_disp &= ~CRTC_V_TOTAL; - pATIHW->crtc_v_total_disp |= - pATIHW->shadow_v_total_disp & CRTC_V_TOTAL; } } if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) - pATIHW->crtc_v_sync_strt_wid = - pATIHW->shadow_v_sync_strt_wid; + { + pATIHW->crt[7] &= ~0x84U; + pATIHW->crt[7] |= pATIHW->shadow_vga[7] & 0x84U; + pATIHW->crt[16] = pATIHW->shadow_vga[16]; + pATIHW->crt[17] &= ~0x0FU; + pATIHW->crt[17] |= pATIHW->shadow_vga[17] & 0x0FU; + } - /* - * Decipher input timing. This is complicated by the fact that - * the full width of all timing parameters, except for the - * blanking pulses, is only available through the accelerator - * registers, not the VGA ones. Blanking pulse boundaries must - * then be interpolated. - * - * Note that, in VGA mode, the accelerator's sync width fields - * are actually end positions, not widths. - */ - HDisplay = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_DISP); - HSyncStart = - (GetBits(pATIHW->crtc_h_sync_strt_wid, - CRTC_H_SYNC_STRT_HI) * - (MaxBits(CRTC_H_SYNC_STRT) + 1)) | - GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_STRT); - HSyncEnd = (HSyncStart & ~MaxBits(CRTC_H_SYNC_WID)) | - GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_WID); - if (HSyncStart >= HSyncEnd) - HSyncEnd += MaxBits(CRTC_H_SYNC_WID) + 1; - HTotal = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_TOTAL); - - HBlankStart = (HDisplay & ~0xFFU) | pATIHW->crt[2]; - if (HDisplay > HBlankStart) - HBlankStart += 0x0100U; - HBlankEnd = (HSyncEnd & ~0x3FU) | - ((pATIHW->crt[5] >> 2) & 0x20U) | - (pATIHW->crt[3] & 0x1FU); - if (HSyncEnd > (HBlankEnd + 1)) - HBlankEnd += 0x40U; - - VDisplay = GetBits(pATIHW->crtc_v_total_disp, CRTC_V_DISP); - VSyncStart = - GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_STRT); - VSyncEnd = (VSyncStart & ~MaxBits(CRTC_V_SYNC_WID)) | - GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_WID); - if (VSyncStart > VSyncEnd) - VSyncEnd += MaxBits(CRTC_V_SYNC_WID) + 1; - VTotal = GetBits(pATIHW->crtc_v_total_disp, CRTC_V_TOTAL); - - VBlankStart = (VDisplay & ~0x03FFU) | - ((pATIHW->crt[9] << 4) & 0x0200U) | - ((pATIHW->crt[7] << 5) & 0x0100U) | pATIHW->crt[21]; - if (VDisplay > VBlankStart) - VBlankStart += 0x0400U; - VBlankEnd = (VSyncEnd & ~0x00FFU) | pATIHW->crt[22]; - if (VSyncEnd > (VBlankEnd + 1)) - VBlankEnd += 0x0100U; - - pATI->LCDHBlankWidth = HBlankEnd - HBlankStart; - pATI->LCDHSyncStart = HSyncStart - HBlankStart - 1; - pATI->LCDHSyncWidth = HSyncEnd - HSyncStart; - - pATI->LCDVBlankWidth = VBlankEnd - VBlankStart; - pATI->LCDVSyncStart = VSyncStart - VBlankStart - 1; - pATI->LCDVSyncWidth = VSyncEnd - VSyncStart; - - HDisplay = HTotal + 5 - pATI->LCDHBlankWidth; - VDisplay = VTotal + 2 - pATI->LCDVBlankWidth; + pATI->LCDHSyncWidth = + (pATIHW->crt[5] - pATIHW->crt[4]) & 0x1FU; + pATI->LCDHBlankWidth = (((pATIHW->crt[3] & 0x1FU) | + ((pATIHW->crt[5] >> 2) & 0x20U)) - + pATIHW->crt[2]) & 0x3FU; + pATI->LCDVSyncWidth = + (pATIHW->crt[17] - pATIHW->crt[16]) & 0x0FU; + pATI->LCDVBlankWidth = + ((pATIHW->crt[22] - pATIHW->crt[21]) & 0xFFU) + 1; + + pATI->LCDHSyncStart = + ((pATIHW->crt[4] - pATIHW->crt[2]) & 0xFFU) + 1; + pATI->LCDVSyncStart = (((((pATIHW->crt[7] << 2) & 0x0200U) | + ((pATIHW->crt[7] << 6) & 0x0100U) | + pATIHW->crt[16]) - + (((pATIHW->crt[9] << 4) & 0x0200U) | + ((pATIHW->crt[7] << 5) & 0x0100U) | + pATIHW->crt[21])) & 0xFFU) + 1; + + HDisplay = pATI->LCDHSyncStart + pATI->LCDHSyncWidth - + pATI->LCDHBlankWidth; + if (HDisplay > 0) + pATI->LCDHBlankWidth += (HDisplay + 0x3FU) & ~0x3FU; + VDisplay = pATI->LCDVSyncStart + pATI->LCDVSyncWidth - + pATI->LCDVBlankWidth; + if (VDisplay > 0) + pATI->LCDVBlankWidth += (VDisplay + 0xFFU) & ~0xFFU; + + HDisplay = pATIHW->crt[0] + 5 - pATI->LCDHBlankWidth; + VDisplay = (((pATIHW->crt[7] << 4) & 0x0200U) | + ((pATIHW->crt[7] << 8) & 0x0100U) | + pATIHW->crt[6]) + 3 - pATI->LCDVBlankWidth; } else @@ -1997,8 +1953,13 @@ ATIPreInit pATIHW->crtc_h_total_disp &= ~CRTC_H_TOTAL; pATIHW->crtc_h_total_disp |= pATIHW->shadow_h_total_disp & CRTC_H_TOTAL; - pATIHW->crtc_h_sync_strt_wid = - pATIHW->shadow_h_sync_strt_wid; + pATIHW->crtc_h_sync_strt_wid &= + ~(CRTC_H_SYNC_STRT | CRTC_H_SYNC_STRT_HI | + CRTC_H_SYNC_WID); + pATIHW->crtc_h_sync_strt_wid |= + pATIHW->shadow_h_sync_strt_wid & + (CRTC_H_SYNC_STRT | CRTC_H_SYNC_STRT_HI | + CRTC_H_SYNC_WID); if (pATIHW->lcd_gen_ctrl & USE_SHADOWED_VEND) { @@ -2016,10 +1977,14 @@ ATIPreInit } if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) - pATIHW->crtc_v_sync_strt_wid = - pATIHW->shadow_v_sync_strt_wid; + { + pATIHW->crtc_v_sync_strt_wid &= + ~(CRTC_V_SYNC_STRT | CRTC_V_SYNC_WID); + pATIHW->crtc_v_sync_strt_wid |= + pATIHW->shadow_v_sync_strt_wid & + (CRTC_V_SYNC_STRT | CRTC_V_SYNC_WID); + } - /* Decipher input timing */ HDisplay = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_DISP) + GetBits(pATIHW->ovr_wid_left_right, OVR_WID_LEFT) + GetBits(pATIHW->ovr_wid_left_right, OVR_WID_RIGHT); @@ -2172,7 +2137,7 @@ ATIPreInit (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) pATI->LCDHorizontal = HDisplay; } - else if (pATI->LCDHorizontal != (int)HDisplay) + else if (pATI->LCDHorizontal != HDisplay) { if ((pATIHW->horz_stretching & (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) != @@ -2189,7 +2154,7 @@ ATIPreInit !(pATIHW->ext_vert_stretch & AUTO_VERT_RATIO)) pATI->LCDVertical = VDisplay; } - else if (pATI->LCDVertical != (int)VDisplay) + else if (pATI->LCDVertical != VDisplay) { if (!(pATIHW->vert_stretching & VERT_STRETCH_EN) || !(pATIHW->ext_vert_stretch & AUTO_VERT_RATIO)) @@ -2217,12 +2182,10 @@ ATIPreInit /* If the mode on entry wasn't stretched, adjust timings */ if (!(pATIHW->horz_stretching & HORZ_STRETCH_EN) && - (pATI->LCDHorizontal > (int)HDisplay)) + ((HDisplay = pATI->LCDHorizontal - HDisplay) > 0)) { - HDisplay = pATI->LCDHorizontal - HDisplay; - if (pATI->LCDHSyncStart >= HDisplay) - pATI->LCDHSyncStart -= HDisplay; - else + pATI->LCDHSyncStart -= HDisplay; + if (pATI->LCDHSyncStart < 0) pATI->LCDHSyncStart = 0; pATI->LCDHBlankWidth -= HDisplay; HDisplay = pATI->LCDHSyncStart + pATI->LCDHSyncWidth; @@ -2231,12 +2194,10 @@ ATIPreInit } if (!(pATIHW->vert_stretching & VERT_STRETCH_EN) && - (pATI->LCDVertical > (int)VDisplay)) + ((VDisplay = pATI->LCDVertical - VDisplay) > 0)) { - VDisplay = pATI->LCDVertical - VDisplay; - if (pATI->LCDVSyncStart >= VDisplay) - pATI->LCDVSyncStart -= VDisplay; - else + pATI->LCDVSyncStart -= VDisplay; + if (pATI->LCDVSyncStart < 0) pATI->LCDVSyncStart = 0; pATI->LCDVBlankWidth -= VDisplay; VDisplay = pATI->LCDVSyncStart + pATI->LCDVSyncWidth; @@ -2457,7 +2418,7 @@ ATIPreInit { xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, "Unable to register %d MB linear aperture at" - " 0x%08lX.\n", pATI->LinearSize >> 10, + " 0x%08X.\n", pATI->LinearSize >> 10, pATI->LinearBase); pATI->LinearSize = 0; @@ -2506,7 +2467,7 @@ ATIPreInit pATI->CursorBase = pATI->LinearBase + pATI->CursorOffset; xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, - "Storing hardware cursor image at 0x%08lX.\n", + "Storing hardware cursor image at 0x%08X.\n", pATI->CursorBase); } @@ -2561,7 +2522,7 @@ ATIPreInit (AcceleratorVideoRAM + PageSize) & ~PageSize; xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, - "Using %d MB linear aperture at 0x%08lX.\n", + "Using %d MB linear aperture at 0x%08X.\n", pATI->LinearSize >> 20, pATI->LinearBase); /* Only mmap what is needed */ @@ -2654,14 +2615,14 @@ ATIPreInit if (pATI->Block0Base) { xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, - "Using Block 0 MMIO aperture at 0x%08lX.\n", pATI->Block0Base); + "Using Block 0 MMIO aperture at 0x%08X.\n", pATI->Block0Base); /* Set Block1 MMIO address if supported */ if (pATI->Chip >= ATI_CHIP_264VT) { pATI->Block1Base = pATI->Block0Base - 0x00000400U; xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, - "Using Block 1 MMIO aperture at 0x%08lX.\n", + "Using Block 1 MMIO aperture at 0x%08X.\n", pATI->Block1Base); } } @@ -3279,7 +3240,8 @@ ATIPreInit pATI->pitchInc = pATI->XModifier * (64 * 8); } - if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0)) + if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0) && + (ModeType == M_T_BUILTIN)) { /* * Given LCD modes are more tightly controlled than CRT modes, allow @@ -3288,56 +3250,53 @@ ATIPreInit */ Strategy |= LOOKUP_OPTIONAL_TOLERANCES; - if (ModeType == M_T_BUILTIN) - { - /* - * Add a mode to the end of the monitor's list for the panel's - * native resolution. - */ - pMode = (DisplayModePtr)xnfcalloc(1, SizeOf(DisplayModeRec)); - pMode->name = "Native panel mode"; - pMode->type = M_T_BUILTIN; - pMode->Clock = pATI->LCDClock; - pMode->HDisplay = pATI->LCDHorizontal; - pMode->VDisplay = pATI->LCDVertical; - - /* - * These timings are bogus, but enough to survive sync tolerance - * checks. - */ - pMode->HSyncStart = pMode->HDisplay; - pMode->HSyncEnd = pMode->HSyncStart + minPitch; - pMode->HTotal = pMode->HSyncEnd + minPitch; - pMode->VSyncStart = pMode->VDisplay; - pMode->VSyncEnd = pMode->VSyncStart + 1; - pMode->VTotal = pMode->VSyncEnd + 1; - - pMode->CrtcHDisplay = pMode->HDisplay; - pMode->CrtcHBlankStart = pMode->HDisplay; - pMode->CrtcHSyncStart = pMode->HSyncStart; - pMode->CrtcHSyncEnd = pMode->HSyncEnd; - pMode->CrtcHBlankEnd = pMode->HTotal; - pMode->CrtcHTotal = pMode->HTotal; - - pMode->CrtcVDisplay = pMode->VDisplay; - pMode->CrtcVBlankStart = pMode->VDisplay; - pMode->CrtcVSyncStart = pMode->VSyncStart; - pMode->CrtcVSyncEnd = pMode->VSyncEnd; - pMode->CrtcVBlankEnd = pMode->VTotal; - pMode->CrtcVTotal = pMode->VTotal; - - if (!pScreenInfo->monitor->Modes) - { - pScreenInfo->monitor->Modes = pMode; - } - else - { - pScreenInfo->monitor->Last->next = pMode; - pMode->prev = pScreenInfo->monitor->Last; - } + /* + * Add a mode to the end of the monitor's list for the panel's native + * resolution. + */ + pMode = (DisplayModePtr)xnfcalloc(1, SizeOf(DisplayModeRec)); + pMode->name = "Native panel mode"; + pMode->type = M_T_BUILTIN; + pMode->Clock = pATI->LCDClock; + pMode->HDisplay = pATI->LCDHorizontal; + pMode->VDisplay = pATI->LCDVertical; - pScreenInfo->monitor->Last = pMode; + /* + * These timings are bogus, but enough to survive sync tolerance + * checks. + */ + pMode->HSyncStart = pMode->HDisplay; + pMode->HSyncEnd = pMode->HSyncStart + minPitch; + pMode->HTotal = pMode->HSyncEnd + minPitch; + pMode->VSyncStart = pMode->VDisplay; + pMode->VSyncEnd = pMode->VSyncStart + 1; + pMode->VTotal = pMode->VSyncEnd + 1; + + pMode->CrtcHDisplay = pMode->HDisplay; + pMode->CrtcHBlankStart = pMode->HDisplay; + pMode->CrtcHSyncStart = pMode->HSyncStart; + pMode->CrtcHSyncEnd = pMode->HSyncEnd; + pMode->CrtcHBlankEnd = pMode->HTotal; + pMode->CrtcHTotal = pMode->HTotal; + + pMode->CrtcVDisplay = pMode->VDisplay; + pMode->CrtcVBlankStart = pMode->VDisplay; + pMode->CrtcVSyncStart = pMode->VSyncStart; + pMode->CrtcVSyncEnd = pMode->VSyncEnd; + pMode->CrtcVBlankEnd = pMode->VTotal; + pMode->CrtcVTotal = pMode->VTotal; + + if (!pScreenInfo->monitor->Modes) + { + pScreenInfo->monitor->Modes = pMode; } + else + { + pScreenInfo->monitor->Last->next = pMode; + pMode->prev = pScreenInfo->monitor->Last; + } + + pScreenInfo->monitor->Last = pMode; /* * Defeat Xconfigurator brain damage. Ignore all HorizSync and @@ -3346,7 +3305,7 @@ ATIPreInit */ if (pScreenInfo->monitor->nHsync > 0) { - double hsync = (double)pATI->LCDClock / + double hsync = (double)pMode->Clock / (pATI->LCDHorizontal + pATI->LCDHBlankWidth); for (i = 0; ; i++) @@ -3374,7 +3333,7 @@ ATIPreInit if (pScreenInfo->monitor->nVrefresh > 0) { - double vrefresh = ((double)pATI->LCDClock * 1000.0) / + double vrefresh = ((double)pMode->Clock * 1000.0) / ((pATI->LCDHorizontal + pATI->LCDHBlankWidth) * (pATI->LCDVertical + pATI->LCDVBlankWidth)); @@ -3460,7 +3419,7 @@ ATIPreInit else if ((pMode->HDisplay & ~pATI->AdjustMask) / pScreenInfo->xInc) xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, "Mode \"%s\" cannot scroll to bottom right corner of virtual" - " resolution.\n Horizontal dimension not a multiple of %ld.\n", + " resolution.\n Horizontal dimension not a multiple of %d.\n", pMode->name, ~pATI->AdjustMask + 1); } while ((pMode = pMode->next) != pScreenInfo->modes); diff --git a/src/atipreinit.h b/src/atipreinit.h index f418a61..5404c2c 100644 --- a/src/atipreinit.h +++ b/src/atipreinit.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h,v 1.6 2003/01/01 19:16:33 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiprint.c b/src/atiprint.c index 31d7307..6b7f20d 100644 --- a/src/atiprint.c +++ b/src/atiprint.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c,v 1.28 2003/11/07 13:45:26 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c,v 1.26 2003/04/23 21:51:30 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -184,7 +184,7 @@ ATIMach64PrintRegisters (IOValue & CRTC_EXT_DISP_EN)) *crtc = ATI_CRTC_MACH64; - xf86ErrorFVerb(4, " %08lX", (unsigned long)IOValue); + xf86ErrorFVerb(4, " %08X", IOValue); } } @@ -223,7 +223,7 @@ ATIMach64PrintRegisters (IOValue & CRTC_EXT_DISP_EN)) *crtc = ATI_CRTC_MACH64; - xf86ErrorFVerb(4, " %08lX", (unsigned long)IOValue); + xf86ErrorFVerb(4, " %08X", IOValue); } } @@ -685,8 +685,7 @@ ATIPrintRegisters { if (!(Index & 15)) xf86ErrorFVerb(4, "\n 0x%02X: ", Index); - xf86ErrorFVerb(4, " 0x%08lX", - (unsigned long)pciReadLong(pPCI->tag, Index)); + xf86ErrorFVerb(4, " 0x%08X", pciReadLong(pPCI->tag, Index)); } } @@ -696,7 +695,7 @@ ATIPrintRegisters if (pATI->pBank) xf86ErrorFVerb(4, "\n Banked aperture at 0x%0lX.", - (unsigned long)pATI->pBank); + pATI->pBank); else xf86ErrorFVerb(4, "\n No banked aperture."); @@ -713,18 +712,18 @@ ATIPrintRegisters #endif /* AVOID_CPIO */ { - xf86ErrorFVerb(4, "\n Linear aperture at %p.\n", pATI->pMemory); + xf86ErrorFVerb(4, "\n Linear aperture at 0x%0lX.\n", pATI->pMemory); } if (pATI->pBlock[0]) { - xf86ErrorFVerb(4, " Block 0 aperture at %p.\n", pATI->pBlock[0]); + xf86ErrorFVerb(4, " Block 0 aperture at 0x%0lX.\n", pATI->pBlock[0]); if (inr(CONFIG_CHIP_ID) == pATI->config_chip_id) xf86ErrorFVerb(4, " MMIO registers are correctly mapped.\n"); else xf86ErrorFVerb(4, " MMIO mapping is in error!\n"); if (pATI->pBlock[1]) - xf86ErrorFVerb(4, " Block 1 aperture at %p.\n", + xf86ErrorFVerb(4, " Block 1 aperture at 0x%0lX.\n", pATI->pBlock[1]); } else @@ -733,7 +732,7 @@ ATIPrintRegisters } if (pATI->pCursorImage) - xf86ErrorFVerb(4, " Hardware cursor image aperture at %p.\n", + xf86ErrorFVerb(4, " Hardware cursor image aperture at 0x%0lX.\n", pATI->pCursorImage); else xf86ErrorFVerb(4, " No hardware cursor image aperture.\n"); diff --git a/src/atiprint.h b/src/atiprint.h index 1aca516..d44cbdf 100644 --- a/src/atiprint.h +++ b/src/atiprint.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h,v 1.10 2003/01/01 19:16:33 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atipriv.h b/src/atipriv.h index 723bf9a..69341ba 100644 --- a/src/atipriv.h +++ b/src/atipriv.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h,v 1.5 2003/01/01 19:16:33 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiprobe.c b/src/atiprobe.c index ec86179..5e2c31b 100644 --- a/src/atiprobe.c +++ b/src/atiprobe.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c,v 1.62tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c,v 1.58 2003/07/02 17:31:29 martin Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -206,7 +206,7 @@ ATICheckSparseIOBases /* User might wish to override this decision */ xf86Msg(X_WARNING, - ATI_NAME ": Sparse I/O base 0x%04lX not probed.\n", IOBase); + ATI_NAME ": Sparse I/O base 0x%04X not probed.\n", IOBase); return Allowed; } } @@ -214,8 +214,6 @@ ATICheckSparseIOBases return DoProbe; } -#ifndef AVOID_NON_PCI - /* * ATIClaimSparseIOBases -- * @@ -238,8 +236,6 @@ ATIClaimSparseIOBases ProbeFlags[FirstPort] = ProbeFlag; } -#endif /* AVOID_NON_PCI */ - /* * ATIVGAProbe -- * @@ -314,7 +310,7 @@ ATIVGAWonderProbe case 0: xf86Msg(X_WARNING, ATI_NAME ": Expected VGA Wonder capability could not be" - " detected at I/O port 0x%04lX because it would conflict with" + " detected at I/O port 0x%04X because it would conflict with" " a non-video PCI/AGP device.\n", pATI->CPIO_VGAWonder); pATI->CPIO_VGAWonder = 0; break; @@ -322,7 +318,7 @@ ATIVGAWonderProbe case Detected8514A: xf86Msg(X_WARNING, ATI_NAME ": Expected VGA Wonder capability could not be" - " detected at I/O port 0x%04lX because it would conflict with" + " detected at I/O port 0x%04X because it would conflict with" " a %s %s.\n", pATI->CPIO_VGAWonder, ATIBusNames[p8514->BusType], ATIAdapterNames[p8514->Adapter]); pATI->CPIO_VGAWonder = 0; @@ -331,7 +327,7 @@ ATIVGAWonderProbe case DetectedMach64: xf86Msg(X_WARNING, ATI_NAME ": Expected VGA Wonder capability could not be" - " detected at I/O port 0x%04lX because it would conflict with" + " detected at I/O port 0x%04X because it would conflict with" " a Mach64.\n", pATI->CPIO_VGAWonder); pATI->CPIO_VGAWonder = 0; break; @@ -371,14 +367,14 @@ ATIVGAWonderProbe (IOValue6 == 0)) { xf86MsgVerb(X_INFO, 3, - ATI_NAME ": VGA Wonder at I/O port 0x%04lX detected.\n", + ATI_NAME ": VGA Wonder at I/O port 0x%04X detected.\n", pATI->CPIO_VGAWonder); } else { xf86Msg(X_WARNING, ATI_NAME ": Expected VGA Wonder capability at I/O port" - " 0x%04lX was not detected.\n", pATI->CPIO_VGAWonder); + " 0x%04X was not detected.\n", pATI->CPIO_VGAWonder); pATI->CPIO_VGAWonder = 0; } break; @@ -807,8 +803,9 @@ ATIAssignVGA outb(VGA_DAC_MASK, 0xA5U); if (inb(IBM_DAC_MASK) == 0xA5U) pATI->VGAAdapter = ATI_ADAPTER_VGA; - outb(VGA_DAC_MASK, OldDACMask); } + + outb(VGA_DAC_MASK, OldDACMask); } break; @@ -828,9 +825,10 @@ ATIAssignVGA outb(VGA_DAC_MASK, 0xA5U); if (inb(IBM_DAC_MASK) == 0xA5U) pATI->VGAAdapter = ATI_ADAPTER_VGA; - outb(VGA_DAC_MASK, OldDACMask); } + outb(VGA_DAC_MASK, OldDACMask); + if (ClockSel & DISABPASSTHRU) outw(CLOCK_SEL, ClockSel); } @@ -856,9 +854,10 @@ ATIAssignVGA outb(VGA_DAC_MASK, 0xA5U); if (inb(IBM_DAC_MASK) == 0xA5U) pATI->VGAAdapter = ATI_ADAPTER_MACH32; - outb(VGA_DAC_MASK, OldDACMask); } + outb(VGA_DAC_MASK, OldDACMask); + if (ClockSel & DISABPASSTHRU) outw(CLOCK_SEL, ClockSel); if (MiscOptions & (DISABLE_VGA | DISABLE_DAC)) @@ -880,9 +879,10 @@ ATIAssignVGA outb(VGA_DAC_MASK, 0xA5U); if (in8(M64_DAC_MASK) == 0xA5U) pATI->VGAAdapter = ATI_ADAPTER_MACH64; - outb(VGA_DAC_MASK, OldDACMask); } + outb(VGA_DAC_MASK, OldDACMask); + if (!(DACCntl & DAC_VGA_ADR_EN)) outr(DAC_CNTL, DACCntl); } @@ -927,8 +927,6 @@ ATIAssignVGA xf86MsgVerb(X_INFO, 3, ATI_NAME ": VGA assigned to this adapter.\n"); } -#ifndef AVOID_NON_PCI - /* * ATIClaimVGA -- * @@ -957,8 +955,6 @@ ATIClaimVGA ATIClaimSparseIOBases(ProbeFlags, pATI->CPIO_VGAWonder, 2, Detected); } -#endif /* AVOID_NON_PCI */ - /* * ATIFindVGA -- * @@ -1221,8 +1217,6 @@ ATIProbe xfree(PCIPorts); -#ifndef AVOID_NON_PCI - /* * A note on probe strategy. I/O and memory response by certain PCI * devices has been disabled by the common layer at this point, @@ -1306,7 +1300,7 @@ ATIProbe 4, fChipsets[ATI_CHIPSET_MACH64]) != DoProbe) { xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared Mach64 at PIO base 0x%04lX not" + ATI_NAME ": Unshared Mach64 at PIO base 0x%04X not" " probed.\n", Mach64SparseIOBases[i]); continue; @@ -1316,7 +1310,7 @@ ATIProbe if (!pATI) { xf86MsgVerb(X_INFO, 4, - ATI_NAME ": Unshared Mach64 at PIO base 0x%04lX not" + ATI_NAME ": Unshared Mach64 at PIO base 0x%04X not" " detected.\n", Mach64SparseIOBases[i]); continue; } @@ -1334,9 +1328,6 @@ ATIProbe ATIClaimSparseIOBases(ProbeFlags, Mach64SparseIOBases[i], 4, DetectedMach64); } - -#endif /* AVOID_NON_PCI */ - } #endif /* AVOID_CPIO */ @@ -1379,7 +1370,7 @@ ATIProbe "Unshared PCI sparse I/O Mach64 in slot %d:%d:%d", pVideo->bus, pVideo->device, pVideo->func); xf86MsgVerb(X_INFO, 3, - ATI_NAME ": %s detected through Block 0 at 0x%08lX.\n", + ATI_NAME ": %s detected through Block 0 at 0x%08X.\n", Identifier, pATI->Block0Base); AddAdapter(pATI); pATI->PCIInfo = pVideo; @@ -1502,8 +1493,6 @@ ATIProbe pVideo->bus, pVideo->device, pVideo->func); break; -#ifndef AVOID_NON_PCI - case Detected8514A: if ((p8514->BusType >= ATI_BUS_PCI) && !p8514->PCIInfo) p8514->PCIInfo = pVideo; @@ -1525,8 +1514,6 @@ ATIProbe pVideo->bus, pVideo->device, pVideo->func); break; -#endif /* AVOID_NON_PCI */ - default: /* Must be DoProbe */ if (!xf86CheckPciSlot(pVideo->bus, pVideo->device, @@ -1600,8 +1587,6 @@ ATIProbe pVideo->bus, pVideo->device, pVideo->func); break; -#ifndef AVOID_NON_PCI - case Detected8514A: xf86Msg(X_WARNING, ATI_NAME ": PCI Mach64 in slot %d:%d:%d will not" @@ -1619,14 +1604,12 @@ ATIProbe ATI_NAME ": PCI Mach64 in slot %d:%d:%d will" " not be enabled\n because it conflicts with" " another %s Mach64 at sparse I/O base" - " 0x%04lX.\n", + " 0x%04X.\n", pVideo->bus, pVideo->device, pVideo->func, ATIBusNames[pATI->BusType], Mach64SparseIOBases[j]); break; -#endif /* AVOID_NON_PCI */ - default: /* Must be DoProbe */ if (!xf86CheckPciSlot(pVideo->bus, pVideo->device, @@ -1656,7 +1639,7 @@ ATIProbe "Shared PCI Mach64 in slot %d:%d:%d", pVideo->bus, pVideo->device, pVideo->func); xf86MsgVerb(X_INFO, 3, - ATI_NAME ": %s with sparse PIO base 0x%04lX" + ATI_NAME ": %s with sparse PIO base 0x%04X" " detected.\n", Identifier, Mach64SparseIOBases[j]); AddAdapter(pATI); @@ -1706,7 +1689,7 @@ ATIProbe sprintf(Identifier, "Shared PCI Mach64 in slot %d:%d:%d", pVideo->bus, pVideo->device, pVideo->func); xf86MsgVerb(X_INFO, 3, - ATI_NAME ": %s with Block 0 base 0x%08lX detected.\n", + ATI_NAME ": %s with Block 0 base 0x%08X detected.\n", Identifier, pATI->Block0Base); AddAdapter(pATI); pATI->SharedAccelerator = TRUE; @@ -1741,12 +1724,42 @@ ATIProbe Chip = ATIChipID(pVideo->chipType, pVideo->chipRev); if (Chip > ATI_CHIP_Mach64) { - if (Chip <= ATI_CHIP_Rage128) - DoRage128 = TRUE; - else if (Chip <= ATI_CHIP_Radeon) - DoRadeon = TRUE; + switch (Chip) + { + case ATI_CHIP_RAGE128GL: + case ATI_CHIP_RAGE128VR: + case ATI_CHIP_RAGE128PROULTRA: + case ATI_CHIP_RAGE128PROGL: + case ATI_CHIP_RAGE128PROVR: + case ATI_CHIP_RAGE128MOBILITY3: + case ATI_CHIP_RAGE128MOBILITY4: + DoRage128 = TRUE; + continue; - continue; + case ATI_CHIP_RADEON: + case ATI_CHIP_RADEONVE: + case ATI_CHIP_RADEONMOBILITY6: + case ATI_CHIP_RS100: + case ATI_CHIP_RS200: + case ATI_CHIP_RS250: + case ATI_CHIP_RADEONMOBILITY7: + case ATI_CHIP_R200: + case ATI_CHIP_RV200: + case ATI_CHIP_RV250: + case ATI_CHIP_RADEONMOBILITY9: + case ATI_CHIP_RS300: + case ATI_CHIP_RV280: + case ATI_CHIP_RADEONMOBILITY9PLUS: + case ATI_CHIP_R300: + case ATI_CHIP_RV350: + case ATI_CHIP_R350: + DoRadeon = TRUE; + continue; + + case ATI_CHIP_HDTV: + default: + continue; + } } if (!nATIGDev) diff --git a/src/atiprobe.h b/src/atiprobe.h index 20f4f66..6f3d855 100644 --- a/src/atiprobe.h +++ b/src/atiprobe.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h,v 1.8 2003/01/01 19:16:33 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiregs.h b/src/atiregs.h index fd80e74..943dbad 100644 --- a/src/atiregs.h +++ b/src/atiregs.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h,v 1.24 2003/04/23 21:51:30 tsi Exp $ */ /* - * Copyright 1994 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1994 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atirgb514.c b/src/atirgb514.c index e0e215e..bedb794 100644 --- a/src/atirgb514.c +++ b/src/atirgb514.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c,v 1.4 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atirgb514.h b/src/atirgb514.h index 9cc9b8b..71f44d2 100644 --- a/src/atirgb514.h +++ b/src/atirgb514.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h,v 1.3 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiscreen.c b/src/atiscreen.c index 822600d..daf5a8c 100644 --- a/src/atiscreen.c +++ b/src/atiscreen.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c,v 1.30 2003/04/23 21:51:30 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiscreen.h b/src/atiscreen.h index 05954ec..7397042 100644 --- a/src/atiscreen.h +++ b/src/atiscreen.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h,v 1.6 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atistruct.h b/src/atistruct.h index a80c8b4..8b98931 100644 --- a/src/atistruct.h +++ b/src/atistruct.h @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h,v 1.41tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h,v 1.39 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -318,8 +318,8 @@ typedef struct _ATIRec * LCD panel data. */ int LCDPanelID, LCDClock, LCDHorizontal, LCDVertical; - unsigned LCDHSyncStart, LCDHSyncWidth, LCDHBlankWidth; - unsigned LCDVSyncStart, LCDVSyncWidth, LCDVBlankWidth; + int LCDHSyncStart, LCDHSyncWidth, LCDHBlankWidth; + int LCDVSyncStart, LCDVSyncWidth, LCDVBlankWidth; int LCDVBlendFIFOSize; /* @@ -406,25 +406,24 @@ typedef struct _ATIRec /* * Driver options. */ - CARD8 OptionAccel:1; /* Use hardware draw engine */ - CARD8 OptionBIOSDisplay:1; /* Allow BIOS interference */ - CARD8 OptionBlend:1; /* Force horizontal blending */ - CARD8 OptionCRTDisplay:1; /* Display on both CRT and digital panel */ - CARD8 OptionCSync:1; /* Use composite sync */ - CARD8 OptionDevel:1; /* Intentionally undocumented */ + CARD8 OptionAccel; /* Use hardware draw engine */ + CARD8 OptionBlend; /* Force horizontal blending */ + CARD8 OptionCRTDisplay; /* Display on both CRT and digital panel */ + CARD8 OptionCSync; /* Use composite sync */ + CARD8 OptionDevel; /* Intentionally undocumented */ #ifndef AVOID_CPIO - CARD8 OptionLinear:1; /* Use linear fb aperture when available */ + CARD8 OptionLinear; /* Use linear fb aperture when available */ #endif /* AVOID_CPIO */ - CARD8 OptionMMIOCache:1; /* Cache MMIO writes */ - CARD8 OptionTestMMIOCache:1;/* Test MMIO cache integrity */ - CARD8 OptionPanelDisplay:1; /* Prefer digital panel over CRT */ - CARD8 OptionProbeClocks:1; /* Force probe for fixed clocks */ - CARD8 OptionShadowFB:1; /* Use shadow frame buffer */ - CARD8 OptionLCDSync:1; /* Temporary */ + CARD8 OptionMMIOCache; /* Cache MMIO writes */ + CARD8 OptionTestMMIOCache; /* Test MMIO cache integrity */ + CARD8 OptionPanelDisplay; /* Prefer CRT over digital panel */ + CARD8 OptionProbeClocks; /* Force probe for fixed clocks */ + CARD8 OptionShadowFB; /* Use shadow frame buffer */ + CARD8 OptionLCDSync; /* Temporary */ /* * State flags. diff --git a/src/atituner.c b/src/atituner.c index 9e5eb12..55dc7c2 100644 --- a/src/atituner.c +++ b/src/atituner.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atituner.h b/src/atituner.h index 2b40d30..0c3c67f 100644 --- a/src/atituner.h +++ b/src/atituner.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h,v 1.1 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiutil.c b/src/atiutil.c index 3ea2e8e..e7bb412 100644 --- a/src/atiutil.c +++ b/src/atiutil.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c,v 1.8 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiutil.h b/src/atiutil.h index 038102d..f43295d 100644 --- a/src/atiutil.h +++ b/src/atiutil.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h,v 1.8 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/ativalid.c b/src/ativalid.c index e3ada17..7c79888 100644 --- a/src/ativalid.c +++ b/src/ativalid.c @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c,v 1.17 2003/10/30 17:36:58 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c,v 1.16 2003/04/23 21:51:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -34,7 +34,7 @@ * * This checks for hardware-related limits on mode timings. */ -ModeStatus +int ATIValidMode ( int iScreen, diff --git a/src/ativalid.h b/src/ativalid.h index bc16169..055ed50 100644 --- a/src/ativalid.h +++ b/src/ativalid.h @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h,v 1.9 2003/10/30 17:36:58 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h,v 1.8 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -28,7 +28,6 @@ #include "xf86str.h" -extern ModeStatus ATIValidMode FunctionPrototype((int, DisplayModePtr, Bool, - int)); +extern int ATIValidMode FunctionPrototype((int, DisplayModePtr, Bool, int)); #endif /* ___ATIVALID_H___ */ diff --git a/src/ativersion.h b/src/ativersion.h index ae2929c..e41618d 100644 --- a/src/ativersion.h +++ b/src/ativersion.h @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h,v 1.65tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h,v 1.62 2003/07/24 22:08:28 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -39,7 +39,7 @@ #define ATI_VERSION_MAJOR 6 #define ATI_VERSION_MINOR 5 -#define ATI_VERSION_PATCH 6 +#define ATI_VERSION_PATCH 3 #ifndef ATI_VERSION_EXTRA #define ATI_VERSION_EXTRA "" diff --git a/src/ativga.c b/src/ativga.c index 2ac97cd..62edf02 100644 --- a/src/ativga.c +++ b/src/ativga.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c,v 1.20 2003/04/23 21:51:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/ativga.h b/src/ativga.h index 0f82294..ff65b35 100644 --- a/src/ativga.h +++ b/src/ativga.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h,v 1.10 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/ativgaio.c b/src/ativgaio.c index 5e7d731..def54e2 100644 --- a/src/ativgaio.c +++ b/src/ativgaio.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c,v 1.4 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/ativgaio.h b/src/ativgaio.h index d3ce372..e08ecff 100644 --- a/src/ativgaio.h +++ b/src/ativgaio.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h,v 1.5 2003/01/01 19:16:34 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atividmem.c b/src/atividmem.c index 048b13a..1b86659 100644 --- a/src/atividmem.c +++ b/src/atividmem.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c,v 1.15 2003/04/23 21:51:31 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atividmem.h b/src/atividmem.h index 9c326c6..7e4c26c 100644 --- a/src/atividmem.h +++ b/src/atividmem.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h,v 1.9 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiwonder.c b/src/atiwonder.c index 7fb5fdb..404aeaf 100644 --- a/src/atiwonder.c +++ b/src/atiwonder.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c,v 1.14 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiwonder.h b/src/atiwonder.h index a3a1a34..34f19cf 100644 --- a/src/atiwonder.h +++ b/src/atiwonder.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h,v 1.9 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiwonderio.c b/src/atiwonderio.c index 53e0e8e..064e49e 100644 --- a/src/atiwonderio.c +++ b/src/atiwonderio.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c,v 1.4 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atiwonderio.h b/src/atiwonderio.h index c483dd7..dd0fa58 100644 --- a/src/atiwonderio.h +++ b/src/atiwonderio.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h,v 1.4 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atixv.c b/src/atixv.c index 10dce23..417373a 100644 --- a/src/atixv.c +++ b/src/atixv.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c,v 1.5 2003/04/25 04:09:54 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/atixv.h b/src/atixv.h index 50c4b3d..56f8da8 100644 --- a/src/atixv.h +++ b/src/atixv.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h,v 1.4 2003/04/23 21:51:31 tsi Exp $ */ /* - * Copyright 2001 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.26 2003/11/06 18:37:58 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.24 2002/12/16 16:19:10 dawes Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -172,8 +172,8 @@ typedef struct { typedef struct { CARD16 reference_freq; CARD16 reference_div; - unsigned min_pll_freq; - unsigned max_pll_freq; + CARD32 min_pll_freq; + CARD32 max_pll_freq; CARD16 xclk; } R128PLLRec, *R128PLLPtr; @@ -491,7 +491,7 @@ do { \ !info->CCEInUse , __FUNCTION__ ); \ } \ if ( !info->CCEInUse ) { \ - R128CCEWaitForIdle(pScrn); \ + R128CCEWaitForIdle(pScrn); \ BEGIN_RING( 6 ); \ OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \ OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \ @@ -523,9 +523,9 @@ do { \ xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ "ADVANCE_RING() used: %d+%d=%d/%d\n", \ info->indirectBuffer->used - info->indirectStart, \ - __count * (int)sizeof(CARD32), \ + __count * sizeof(CARD32), \ info->indirectBuffer->used - info->indirectStart + \ - __count * (int)sizeof(CARD32), \ + __count * sizeof(CARD32), \ info->indirectBuffer->total - info->indirectStart ); \ } \ info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ diff --git a/src/r128_accel.c b/src/r128_accel.c index 44bc2d4..9329ad2 100644 --- a/src/r128_accel.c +++ b/src/r128_accel.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.17 2003/10/03 20:11:11 herrb Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.16 2002/11/15 03:01:35 dawes Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -82,6 +82,7 @@ /* Driver data structures */ #include "r128.h" #include "r128_reg.h" +#include "r128_sarea.h" #ifdef XF86DRI #include "r128_sarea.h" #define _XF86DRI_SERVER_ @@ -1100,7 +1101,7 @@ static void R128CCESetupForSolidFill(ScrnInfoPtr pScrn, OUT_RING_REG( R128_DP_BRUSH_FRGD_CLR, color ); OUT_RING_REG( R128_DP_WRITE_MASK, planemask ); - OUT_RING_REG( R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT | + OUT_RING_REG( R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT | R128_DST_Y_TOP_TO_BOTTOM)); ADVANCE_RING(); } @@ -1575,7 +1576,7 @@ drmBufPtr R128CCEGetBuffer( ScrnInfoPtr pScrn ) xf86DrvMsg( pScrn->scrnIndex, X_ERROR, "GetBuffer timed out, resetting engine...\n"); R128EngineReset( pScrn ); - /* R128EngineRestore( pScrn ); FIXME ??? */ + /* R128EngineRestore( pScrn ); FIXME ??? */ /* Always restart the engine when doing CCE 2D acceleration */ R128CCE_RESET( pScrn, info ); @@ -1655,7 +1656,7 @@ static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) a->PolyFillRectSolidFlags = 0; a->SetupForSolidFill = R128CCESetupForSolidFill; a->SubsequentSolidFillRect = R128CCESubsequentSolidFillRect; - + /* Screen-to-screen Copy */ /* Transparency uses the wrong colors for 24 bpp mode -- the transparent part is diff --git a/src/r128_cursor.c b/src/r128_cursor.c index 7527c33..5a2ac4f 100644 --- a/src/r128_cursor.c +++ b/src/r128_cursor.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.5tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.6 2003/02/13 20:28:40 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and diff --git a/src/r128_dga.c b/src/r128_dga.c index c6d9133..6c0013a 100644 --- a/src/r128_dga.c +++ b/src/r128_dga.c @@ -65,7 +65,7 @@ SECOND_PASS: pitch = secondPitch; if (!(newmodes = xrealloc(modes, (*num + 1) * sizeof(DGAModeRec)))) - break; + break; modes = newmodes; currentMode = modes + *num; @@ -74,7 +74,7 @@ SECOND_PASS: currentMode->flags = DGA_CONCURRENT_ACCESS; if (pixmap) - currentMode->flags |= DGA_PIXMAP_AVAILABLE; + currentMode->flags |= DGA_PIXMAP_AVAILABLE; if (info->accel) { if (info->accel->SetupForSolidFill && @@ -91,7 +91,7 @@ SECOND_PASS: if (pMode->Flags & V_DBLSCAN) currentMode->flags |= DGA_DOUBLESCAN; if (pMode->Flags & V_INTERLACE) - currentMode->flags |= DGA_INTERLACED; + currentMode->flags |= DGA_INTERLACED; currentMode->byteOrder = pScrn->imageByteOrder; currentMode->depth = depth; @@ -240,16 +240,16 @@ R128_SetMode( pScrn->SwitchMode(indx, pScrn->currentMode, 0); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { R128CCE_STOP(pScrn, info); - } + } #endif if (info->accelOn) R128EngineInit(pScrn); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { R128CCE_START(pScrn, info); - } + } #endif pScrn->AdjustFrame(indx, 0, 0, 0); info->DGAactive = FALSE; @@ -272,16 +272,16 @@ R128_SetMode( pScrn->SwitchMode(indx, pMode->mode, 0); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { R128CCE_STOP(pScrn, info); - } + } #endif if (info->accelOn) R128EngineInit(pScrn); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { R128CCE_START(pScrn, info); - } + } #endif } diff --git a/src/r128_dri.c b/src/r128_dri.c index e185a27..48765b1 100644 --- a/src/r128_dri.c +++ b/src/r128_dri.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.31 2003/09/28 20:15:53 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.29 2003/07/09 01:45:22 dawes Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -152,7 +152,7 @@ static Bool R128InitVisualConfigs(ScreenPtr pScreen) pConfigs[i].accumBlueSize = 0; pConfigs[i].accumAlphaSize = 0; } - if (db) + if (db) pConfigs[i].doubleBuffer = TRUE; else pConfigs[i].doubleBuffer = FALSE; @@ -363,9 +363,9 @@ static void R128DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx) int nbox, nboxSave; int depth; - /* FIXME: Use accel when CCE 2D code is written + /* FIXME: Use accel when CCE 2D code is written * EA: What is this code kept for? Radeon doesn't have it and - * has a comment: "There's no need for the 2d driver to be clearing + * has a comment: "There's no need for the 2d driver to be clearing * buffers for the 3d client. It knows how to do that on its own." */ if (info->directRenderingEnabled) @@ -489,7 +489,7 @@ static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen) return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] %d kB allocated with handle 0x%08lx\n", + "[agp] %d kB allocated with handle 0x%08x\n", info->agpSize*1024, info->agpMemHandle); if (drmAgpBind(info->drmFD, info->agpMemHandle, info->agpOffset) < 0) { @@ -618,7 +618,7 @@ static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen) return FALSE; } agpBase = drmAgpBase(info->drmFD); - OUTREG(R128_AGP_BASE, agpBase); + OUTREG(R128_AGP_BASE, agpBase); OUTREG(R128_AGP_CNTL, cntl); /* Disable Rage 128's PCIGART registers */ @@ -649,7 +649,7 @@ static Bool R128DRIPciInit(R128InfoPtr info, ScreenPtr pScreen) return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] %d kB allocated with handle 0x%08lx\n", + "[pci] %d kB allocated with handle 0x%08x\n", info->agpSize*1024, info->pciMemHandle); /* Initialize the CCE ring buffer data */ @@ -1178,9 +1178,9 @@ Bool R128DRIScreenInit(ScreenPtr pScreen) { void *scratch_ptr; int scratch_int; - + DRIGetDeviceInfo(pScreen, &info->fbHandle, - &scratch_int, &scratch_int, + &scratch_int, &scratch_int, &scratch_int, &scratch_int, &scratch_ptr); } @@ -1329,10 +1329,10 @@ void R128DRICloseScreen(ScreenPtr pScreen) drmUnmap(info->ring, info->ringMapSize); info->ring = NULL; } - if (info->agpMemHandle != DRM_AGP_NO_HANDLE) { + if (info->agpMemHandle!=DRM_AGP_NO_HANDLE) { drmAgpUnbind(info->drmFD, info->agpMemHandle); drmAgpFree(info->drmFD, info->agpMemHandle); - info->agpMemHandle = DRM_AGP_NO_HANDLE; + info->agpMemHandle = 0; drmAgpRelease(info->drmFD); } if (info->pciMemHandle) { @@ -1479,7 +1479,7 @@ static void R128DRITransitionTo2d(ScreenPtr pScreen) } else { xf86DrvMsg(pScreen->myNum, X_WARNING, "[dri] R128DRITransitionTo2d: " - "kernel failed to unflip buffers.\n"); + "kernel failed to unflip buffers.\n"); } info->have3DWindows = 0; diff --git a/src/r128_dri.h b/src/r128_dri.h index 64345d3..1339a45 100644 --- a/src/r128_dri.h +++ b/src/r128_dri.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.h,v 1.6 2001/03/21 17:02:21 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.h,v 1.7 2002/10/30 12:52:12 alanh Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and diff --git a/src/r128_dripriv.h b/src/r128_dripriv.h index 043e7bd..7f84987 100644 --- a/src/r128_dripriv.h +++ b/src/r128_dripriv.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dripriv.h,v 1.2 2000/11/09 03:24:35 martin Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dripriv.h,v 1.3 2000/11/18 19:37:11 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and diff --git a/src/r128_driver.c b/src/r128_driver.c index cd8b995..d1fbd56 100644 --- a/src/r128_driver.c +++ b/src/r128_driver.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.88 2004/01/29 02:51:17 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.79 2003/08/23 15:02:54 dawes Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -500,9 +500,7 @@ static void R128Unblank(ScrnInfoPtr pScrn) if(info->isDFP) OUTREGP(R128_FP_GEN_CNTL, 0, ~R128_FP_BLANK_DIS); else - OUTREGP(R128_CRTC_EXT_CNTL, 0, ~(R128_CRTC_DISPLAY_DIS | - R128_CRTC_VSYNC_DIS | - R128_CRTC_HSYNC_DIS)); + OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS); } /* Compute log base 2 of val. */ @@ -639,7 +637,7 @@ static Bool R128GetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->HasPanelRegs = FALSE; xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Can't determine panel dimensions, and none specified. \ - Disabling programming of FP registers.\n"); + Disabling programming of FP registers.\n"); } return TRUE; @@ -856,7 +854,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) pScrn->memPhysBase = info->LinearAddr; if (dev->MemBase) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Linear address override, using 0x%08lx instead of 0x%08lx\n", + "Linear address override, using 0x%08x instead of 0x%08x\n", dev->MemBase, info->LinearAddr); info->LinearAddr = dev->MemBase; @@ -874,7 +872,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) info->MMIOAddr = info->PciInfo->memBase[2] & 0xffffff00; if (dev->IOBase) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "MMIO address override, using 0x%08lx instead of 0x%08lx\n", + "MMIO address override, using 0x%08x instead of 0x%08x\n", dev->IOBase, info->MMIOAddr); info->MMIOAddr = dev->IOBase; @@ -891,7 +889,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; if (dev->BiosBase) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS address override, using 0x%08lx instead of 0x%08lx\n", + "BIOS address override, using 0x%08x instead of 0x%08x\n", dev->BiosBase, info->BIOSAddr); info->BIOSAddr = dev->BiosBase; @@ -916,8 +914,8 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) switch (info->Chipset) { /* R128 Pro and Pro2 can have DFP, we will deal with it. No support for dual-head/xinerama yet. - M3 can also have DFP, no support for now */ - case PCI_CHIP_RAGE128TF: + M3 can also have DFP, no support for now */ + case PCI_CHIP_RAGE128TF: case PCI_CHIP_RAGE128TL: case PCI_CHIP_RAGE128TR: /* FIXME: RAGE128 TS/TT/TU are assumed to be PRO2 as all 6 chips came @@ -925,9 +923,9 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) * This requires confirmation however to be fully correct. * Mike A. Harris <mharris@redhat.com> */ - case PCI_CHIP_RAGE128TS: + case PCI_CHIP_RAGE128TS: case PCI_CHIP_RAGE128TT: - case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE; + case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE; /* FIXME: RAGE128 P[ABCEGHIJKLMNOQSTUVWX] are assumed to have DFP * capability, as the comment at the top suggests. * This requires confirmation however to be fully correct. @@ -1232,7 +1230,7 @@ R128I2CPutBits(I2CBusPtr b, int Clock, int data) unsigned long val; unsigned char *R128MMIO = info->MMIO; - val = INREG(info->DDCReg) + val = INREG(info->DDCReg) & ~(CARD32)(R128_GPIO_MONID_EN_0 | R128_GPIO_MONID_EN_3); val |= (Clock ? 0:R128_GPIO_MONID_EN_3); val |= (data ? 0:R128_GPIO_MONID_EN_0); @@ -1247,7 +1245,7 @@ R128I2cInit(ScrnInfoPtr pScrn) if ( xf86LoadSubModule(pScrn, "i2c") ) xf86LoaderReqSymLists(i2cSymbols,NULL); else{ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to load i2c module\n"); return FALSE; } @@ -1278,11 +1276,11 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn) unsigned char *R128MMIO = info->MMIO; if(!R128I2cInit(pScrn)){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "I2C initialization failed!\n"); } - OUTREG(info->DDCReg, (INREG(info->DDCReg) + OUTREG(info->DDCReg, (INREG(info->DDCReg) | R128_GPIO_MONID_MASK_0 | R128_GPIO_MONID_MASK_3)); OUTREG(info->DDCReg, INREG(info->DDCReg) @@ -1290,7 +1288,7 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn) MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus); if(!MonInfo) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No DFP detected\n"); return FALSE; } @@ -1308,19 +1306,19 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn) info->HOverPlus = ddc->det_mon[i].section.d_timings.h_sync_off; - info->HSyncWidth = + info->HSyncWidth = ddc->det_mon[i].section.d_timings.h_sync_width; info->HBlank = ddc->det_mon[i].section.d_timings.h_blanking; info->VOverPlus = ddc->det_mon[i].section.d_timings.v_sync_off; - info->VSyncWidth = + info->VSyncWidth = ddc->det_mon[i].section.d_timings.v_sync_width; info->VBlank = ddc->det_mon[i].section.d_timings.v_blanking; - } + } } - return TRUE; + return TRUE; } @@ -1335,63 +1333,63 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag) if(ddc->det_mon[i].type == DS_RANGES) { pScrn->monitor->nHsync = 1; - pScrn->monitor->hsync[0].lo = + pScrn->monitor->hsync[0].lo = ddc->det_mon[i].section.ranges.min_h; - pScrn->monitor->hsync[0].hi = + pScrn->monitor->hsync[0].hi = ddc->det_mon[i].section.ranges.max_h; return; } } /*if no sync ranges detected in detailed timing table, let's try to derive them from supported VESA modes - Are we doing too much here!!!? + Are we doing too much here!!!? **/ i = 0; if(ddc->timings1.t1 & 0x02) /*800x600@56*/ { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 35.2; i++; - } + } if(ddc->timings1.t1 & 0x04) /*640x480@75*/ { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 37.5; i++; - } + } if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t1 & 0x01)) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 37.9; i++; - } + } if(ddc->timings1.t2 & 0x40) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 46.9; i++; } if((ddc->timings1.t2 & 0x80) || (ddc->timings1.t2 & 0x08)) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 48.1; i++; - } + } if(ddc->timings1.t2 & 0x04) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 56.5; i++; - } + } if(ddc->timings1.t2 & 0x02) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 60.0; i++; - } + } if(ddc->timings1.t2 & 0x01) { - pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].lo = pScrn->monitor->hsync[i].hi = 64.0; i++; } @@ -1404,42 +1402,42 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag) if(ddc->det_mon[i].type == DS_RANGES) { pScrn->monitor->nVrefresh = 1; - pScrn->monitor->vrefresh[0].lo = + pScrn->monitor->vrefresh[0].lo = ddc->det_mon[i].section.ranges.min_v; - pScrn->monitor->vrefresh[0].hi = + pScrn->monitor->vrefresh[0].hi = ddc->det_mon[i].section.ranges.max_v; return; } } i = 0; if(ddc->timings1.t1 & 0x02) /*800x600@56*/ - { - pScrn->monitor->vrefresh[i].lo = + { + pScrn->monitor->vrefresh[i].lo = pScrn->monitor->vrefresh[i].hi = 56; i++; } if((ddc->timings1.t1 & 0x01) || (ddc->timings1.t2 & 0x08)) - { - pScrn->monitor->vrefresh[i].lo = + { + pScrn->monitor->vrefresh[i].lo = pScrn->monitor->vrefresh[i].hi = 60; i++; } if(ddc->timings1.t2 & 0x04) - { - pScrn->monitor->vrefresh[i].lo = + { + pScrn->monitor->vrefresh[i].lo = pScrn->monitor->vrefresh[i].hi = 70; i++; } if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t2 & 0x80)) - { - pScrn->monitor->vrefresh[i].lo = + { + pScrn->monitor->vrefresh[i].lo = pScrn->monitor->vrefresh[i].hi = 72; i++; } if((ddc->timings1.t1 & 0x04) || (ddc->timings1.t2 & 0x40) || (ddc->timings1.t2 & 0x02) || (ddc->timings1.t2 & 0x01)) - { - pScrn->monitor->vrefresh[i].lo = + { + pScrn->monitor->vrefresh[i].lo = pScrn->monitor->vrefresh[i].hi = 75; i++; } @@ -1447,13 +1445,13 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag) } } -/*********** +/*********** xfree's xf86ValidateModes routine deosn't work well with DFPs - here is our own validation routine. All modes between - 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted. - NOTE: RageProII doesn't support rmx, can only work with the + here is our own validation routine. All modes between + 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted. + NOTE: RageProII doesn't support rmx, can only work with the standard modes the monitor can support (scale). -************/ +************/ static int R128ValidateFPModes(ScrnInfoPtr pScrn) { @@ -1488,15 +1486,15 @@ static int R128ValidateFPModes(ScrnInfoPtr pScrn) if (sscanf(pScrn->display->modes[i], "%dx%d", &width, &height) == 2) { - if(width < 640 || width > info->PanelXRes || + if(width < 640 || width > info->PanelXRes || height < 480 || height > info->PanelYRes) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode %s is out of range.\n" "Valid mode should be between 640x480-%dx%d\n", pScrn->display->modes[i], info->PanelXRes, info->PanelYRes); continue; - } + } new = xnfcalloc(1, sizeof(DisplayModeRec)); new->prev = last; @@ -1526,8 +1524,8 @@ static int R128ValidateFPModes(ScrnInfoPtr pScrn) } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Mode name %s is invalid\n", pScrn->display->modes[i]); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode name %s is invalid\n", pScrn->display->modes[i]); continue; } } @@ -1578,16 +1576,16 @@ static Bool R128PreInitModes(ScrnInfoPtr pScrn) info->isDFP = FALSE; info->BIOSDisplay = R128_BIOS_DISPLAY_CRT; } else if(!info->isPro2) { - /* RageProII doesn't support rmx, we can't use native-mode + /* RageProII doesn't support rmx, we can't use native-mode stretching for other non-native modes. It will rely on whatever VESA modes monitor can support. */ modesFound = R128ValidateFPModes(pScrn); if(modesFound < 1) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid mode found for this DFP/LCD\n"); R128UnmapMem(pScrn); return FALSE; - + } } R128UnmapMem(pScrn); @@ -1639,9 +1637,9 @@ static Bool R128PreInitModes(ScrnInfoPtr pScrn) LOOKUP_BEST_REFRESH); if (modesFound < 1 && info->FBDev) { - fbdevHWUseBuildinMode(pScrn); - pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8); - modesFound = 1; + fbdevHWUseBuildinMode(pScrn); + pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8); + modesFound = 1; } if (modesFound == -1) return FALSE; @@ -2402,7 +2400,7 @@ Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) int width, height; xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using hardware cursor (scanline %ld)\n", + "Using hardware cursor (scanline %d)\n", info->cursor_start / pScrn->displayWidth); if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0)) { @@ -2874,23 +2872,25 @@ static Bool R128InitCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save, int hsync_wid; int hsync_fudge; int vsync_wid; + int bytpp; int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 }; int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 }; switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ + case 4: format = 1; bytpp = 0; break; + case 8: format = 2; bytpp = 1; break; + case 15: format = 3; bytpp = 2; break; /* 555 */ + case 16: format = 4; bytpp = 2; break; /* 565 */ + case 24: format = 5; bytpp = 3; break; /* RGB */ + case 32: format = 6; bytpp = 4; break; /* xRGB */ default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel); return FALSE; } + R128TRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp)); switch (info->BIOSDisplay) { case R128_BIOS_DISPLAY_FP: @@ -3016,7 +3016,7 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, R128_FP_CRTC_DONT_SHADOW_VPAR); save->fp_panel_cntl = orig->fp_panel_cntl & (CARD32)~R128_FP_DIGON; save->lvds_gen_cntl = orig->lvds_gen_cntl & - (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON); + (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON); return; } @@ -3034,9 +3034,9 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, R128_HORZ_STRETCH_RESERVED))); save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN; save->fp_horz_stretch &= ~R128_AUTO_HORZ_RATIO; - if (xres == info->PanelXRes) + if (xres == info->PanelXRes) save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); - else + else save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); save->fp_vert_stretch = @@ -3045,9 +3045,9 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, (orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE | R128_VERT_STRETCH_RESERVED))); save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN; - if (yres == info->PanelYRes) + if (yres == info->PanelYRes) save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); - else + else save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); save->fp_gen_cntl = (orig->fp_gen_cntl & @@ -3056,7 +3056,7 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, R128_FP_CRTC_HORZ_DIV2_EN | R128_FP_CRTC_HOR_CRT_DIV2_DIS | R128_FP_USE_SHADOW_EN)); - + save->fp_panel_cntl = orig->fp_panel_cntl; save->lvds_gen_cntl = orig->lvds_gen_cntl; save->tmds_crc = orig->tmds_crc; @@ -3066,28 +3066,28 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, want to use the dual CRTC capabilities of the R128 to allow both the flat panel and external CRT to either simultaneously display the same image or display two different images. */ - + if(!info->isDFP){ if (info->BIOSDisplay == R128_BIOS_DISPLAY_FP_CRT) { - save->crtc_ext_cntl |= R128_CRTC_CRT_ON; + save->crtc_ext_cntl |= R128_CRTC_CRT_ON; } else { - save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON; - save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2; - save->crtc2_gen_cntl = 0; + save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON; + save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2; + save->crtc2_gen_cntl = 0; } } /* WARNING: Be careful about turning on the flat panel */ if(info->isDFP){ save->fp_gen_cntl = orig->fp_gen_cntl; - + save->fp_gen_cntl &= ~(R128_FP_CRTC_USE_SHADOW_VEND | R128_FP_CRTC_USE_SHADOW_ROWCUR | R128_FP_CRTC_HORZ_DIV2_EN | R128_FP_CRTC_HOR_CRT_DIV2_DIS | R128_FP_CRT_SYNC_SEL | R128_FP_USE_SHADOW_EN); - + save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON); save->fp_gen_cntl |= (R128_FP_FPON | R128_FP_TDMS_EN | R128_FP_CRTC_DONT_SHADOW_VPAR | R128_FP_CRTC_DONT_SHADOW_HEND); @@ -3157,7 +3157,7 @@ static void R128InitPLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save, /* Define DDA registers for requested video mode. */ static Bool R128InitDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save, - R128PLLPtr pll, R128InfoPtr info, + R128PLLPtr pll, R128InfoPtr info, DisplayModePtr mode) { int DisplayFifoWidth = 128; @@ -3298,7 +3298,7 @@ static Bool R128Init(ScrnInfoPtr pScrn, DisplayModePtr mode, R128SavePtr save) if(dot_clock > 0){ R128InitPLLRegisters(pScrn, save, &info->pll, dot_clock); if (!R128InitDDARegisters(pScrn, save, &info->pll, info, mode)) - return FALSE; + return FALSE; } else{ save->ppll_ref_div = info->SavedReg.ppll_ref_div; @@ -3353,8 +3353,8 @@ Bool R128SwitchMode(int scrnIndex, DisplayModePtr mode, int flags) } /* Used to disallow modes that are not supported by the hardware. */ -ModeStatus R128ValidMode(int scrnIndex, DisplayModePtr mode, - Bool verbose, int flags) +int R128ValidMode(int scrnIndex, DisplayModePtr mode, + Bool verbose, int flag) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; R128InfoPtr info = R128PTR(pScrn); @@ -3381,47 +3381,46 @@ ModeStatus R128ValidMode(int scrnIndex, DisplayModePtr mode, if (mode->CrtcHDisplay == R128_BIOS16(j) && mode->CrtcVDisplay == R128_BIOS16(j+2)) { - if ((flags & MODECHECK_FINAL) == MODECHECK_FINAL) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Modifying mode according to VBIOS: %ix%i [pclk %.1f MHz] for FP to: ", - mode->CrtcHDisplay,mode->CrtcVDisplay, - (float)mode->Clock/1000); - - /* Assume we are using expanded mode */ - if (R128_BIOS16(j+5)) j = R128_BIOS16(j+5); - else j += 9; - - mode->Clock = (CARD32)R128_BIOS16(j) * 10; - - mode->HDisplay = mode->CrtcHDisplay = - ((R128_BIOS16(j+10) & 0x01ff)+1)*8; - mode->HSyncStart = mode->CrtcHSyncStart = - ((R128_BIOS16(j+12) & 0x01ff)+1)*8; - mode->HSyncEnd = mode->CrtcHSyncEnd = - mode->CrtcHSyncStart + (R128_BIOS8(j+14) & 0x1f); - mode->HTotal = mode->CrtcHTotal = - ((R128_BIOS16(j+8) & 0x01ff)+1)*8; - - mode->VDisplay = mode->CrtcVDisplay = - (R128_BIOS16(j+17) & 0x07ff)+1; - mode->VSyncStart = mode->CrtcVSyncStart = - (R128_BIOS16(j+19) & 0x07ff)+1; - mode->VSyncEnd = mode->CrtcVSyncEnd = - mode->CrtcVSyncStart + ((R128_BIOS16(j+19) >> 11) & 0x1f); - mode->VTotal = mode->CrtcVTotal = - (R128_BIOS16(j+15) & 0x07ff)+1; - xf86ErrorF("%ix%i [pclk %.1f MHz]\n", - mode->CrtcHDisplay,mode->CrtcVDisplay, - (float)mode->Clock/1000); - } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Modifying mode according to VBIOS: %ix%i [pclk %.1f MHz] for FP to: ", + mode->CrtcHDisplay,mode->CrtcVDisplay, + (float)mode->Clock/1000); + + /* Assume we are using expanded mode */ + if (R128_BIOS16(j+5)) j = R128_BIOS16(j+5); + else j += 9; + + mode->Clock = (CARD32)R128_BIOS16(j) * 10; + + mode->HDisplay = mode->CrtcHDisplay = + ((R128_BIOS16(j+10) & 0x01ff)+1)*8; + mode->HSyncStart = mode->CrtcHSyncStart = + ((R128_BIOS16(j+12) & 0x01ff)+1)*8; + mode->HSyncEnd = mode->CrtcHSyncEnd = + mode->CrtcHSyncStart + (R128_BIOS8(j+14) & 0x1f); + mode->HTotal = mode->CrtcHTotal = + ((R128_BIOS16(j+8) & 0x01ff)+1)*8; + + mode->VDisplay = mode->CrtcVDisplay = + (R128_BIOS16(j+17) & 0x07ff)+1; + mode->VSyncStart = mode->CrtcVSyncStart = + (R128_BIOS16(j+19) & 0x07ff)+1; + mode->VSyncEnd = mode->CrtcVSyncEnd = + mode->CrtcVSyncStart + ((R128_BIOS16(j+19) >> 11) & 0x1f); + mode->VTotal = mode->CrtcVTotal = + (R128_BIOS16(j+15) & 0x07ff)+1; + xf86ErrorF("%ix%i [pclk %.1f MHz]\n", + mode->CrtcHDisplay,mode->CrtcVDisplay, + (float)mode->Clock/1000); + return MODE_OK; } } - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 5, + xf86DrvMsgVerb(5,pScrn->scrnIndex, X_INFO, "Mode rejected for FP %ix%i [pclk: %.1f] " "(not listed in VBIOS)\n", mode->CrtcHDisplay, mode->CrtcVDisplay, - (float)mode->Clock / 1000); + mode->Clock / 1000); return MODE_NOMODE; } @@ -3665,7 +3664,7 @@ static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on) lvds_gen_cntl |= R128_LVDS_DISPLAY_DIS; OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl); usleep(10); - lvds_gen_cntl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON + lvds_gen_cntl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON | R128_LVDS_DIGON); } diff --git a/src/r128_misc.c b/src/r128_misc.c index dd77061..8841f34 100644 --- a/src/r128_misc.c +++ b/src/r128_misc.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c,v 1.5 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -38,7 +38,7 @@ static XF86ModuleVersionInfo R128VersionRec = MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, - XORG_VERSION_CURRENT, + XF86_VERSION_CURRENT, R128_VERSION_MAJOR, R128_VERSION_MINOR, R128_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, diff --git a/src/r128_probe.c b/src/r128_probe.c index d017b35..a5cd42f 100644 --- a/src/r128_probe.c +++ b/src/r128_probe.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c,v 1.17 2003/02/07 20:41:15 martin Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c,v 1.18 2003/02/09 15:33:17 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and diff --git a/src/r128_probe.h b/src/r128_probe.h index 247a8f5..094a9b6 100644 --- a/src/r128_probe.h +++ b/src/r128_probe.h @@ -69,7 +69,7 @@ extern void R128LeaveVT FunctionPrototype((int, int)); extern void R128FreeScreen FunctionPrototype((int, int)); -extern ModeStatus R128ValidMode +extern int R128ValidMode FunctionPrototype((int, DisplayModePtr, Bool, int)); diff --git a/src/r128_sarea.h b/src/r128_sarea.h index beb8cfe..6ffdb41 100644 --- a/src/r128_sarea.h +++ b/src/r128_sarea.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_sarea.h,v 1.8 2003/09/28 20:15:54 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_sarea.h,v 1.7 2002/02/16 21:26:35 herrb Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -158,10 +158,12 @@ typedef struct { unsigned int vertsize; unsigned int vc_format; +#ifdef XF86DRI /* The current cliprects, or a subset thereof. */ XF86DRIClipRectRec boxes[R128_NR_SAREA_CLIPRECTS]; unsigned int nbox; +#endif /* Counters for throttling of rendering clients. */ diff --git a/src/r128_version.h b/src/r128_version.h index 846b01a..589d8d4 100644 --- a/src/r128_version.h +++ b/src/r128_version.h @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h,v 1.6 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/r128_video.c b/src/r128_video.c index 7ef31af..b5a22af 100644 --- a/src/r128_video.c +++ b/src/r128_video.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c,v 1.30 2003/11/10 18:22:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c,v 1.28 2003/04/23 21:51:31 tsi Exp $ */ #include "r128.h" #include "r128_reg.h" @@ -65,7 +65,7 @@ static void R128ECP(ScrnInfoPtr pScrn, R128PortPrivPtr pPriv) R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; int dot_clock = info->ModeReg.dot_clock_freq; - + if (dot_clock < 12500) pPriv->ecp_div = 0; else if (dot_clock < 25000) pPriv->ecp_div = 1; else pPriv->ecp_div = 2; @@ -245,7 +245,7 @@ R128SetupImageVideo(ScreenPtr pScreen) info->adaptor = adapt; pPriv = (R128PortPrivPtr)(adapt->pPortPrivates[0].ptr); - REGION_NULL(pScreen, &(pPriv->clip)); + REGION_INIT(pScreen, &(pPriv->clip), NullBox, 0); R128ResetVideo(pScrn); @@ -430,7 +430,7 @@ R128DMA( return FALSE; } - /* Copy parts of the block into buffers and fire them */ + /* Copy parts of the block into buffers and fire them */ dstpassbytes = hpass*dstPitch; dstPitch /= 8; @@ -449,7 +449,7 @@ R128DMA( } else { int count = hpass; while(count--) { - memcpy(buf, src, w); + memcpy(buf, src, w); src += srcPitch; buf += w; } @@ -770,7 +770,7 @@ R128PutImage( R128InfoPtr info = R128PTR(pScrn); R128PortPrivPtr pPriv = (R128PortPrivPtr)data; INT32 xa, xb, ya, yb; - int new_size, offset, s1offset, s2offset, s3offset; + int pitch, new_size, offset, s1offset, s2offset, s3offset; int srcPitch, srcPitch2, dstPitch; int d1line, d2line, d3line, d1offset, d2offset, d3offset; int top, left, npixels, nlines, bpp; @@ -826,6 +826,7 @@ R128PutImage( dstBox.y2 -= pScrn->frameY0; bpp = pScrn->bitsPerPixel >> 3; + pitch = bpp * pScrn->displayWidth; switch(id) { case FOURCC_YV12: diff --git a/src/radeon.h b/src/radeon.h index fd91e3d..bff12e4 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.43 2003/11/06 18:38:00 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.40 2003/07/02 17:31:29 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -72,8 +72,8 @@ #define RADEON_MMIOSIZE 0x80000 #define RADEON_VBIOS_SIZE 0x00010000 -#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX - * Need to comfirm this is not used +#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX + * Need to comfirm this is not used * for something else. */ @@ -94,6 +94,20 @@ do { \ #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) typedef struct { + /* All values in XCLKS */ + int ML; /* Memory Read Latency */ + int MB; /* Memory Burst Length */ + int Trcd; /* RAS to CAS delay */ + int Trp; /* RAS percentage */ + int Twr; /* Write Recovery */ + int CL; /* CAS Latency */ + int Tr2w; /* Read to Write Delay */ + int Rloop; /* Loop Latency */ + int Rloop_fudge; /* Add to ML to get Rloop */ + char *name; +} RADEONRAMRec, *RADEONRAMPtr; + +typedef struct { /* Common registers */ CARD32 ovr_clr; CARD32 ovr_wid_left_right; @@ -130,7 +144,6 @@ typedef struct { CARD32 crtc_pitch; CARD32 disp_merge_cntl; CARD32 grph_buffer_cntl; - CARD32 crtc_more_cntl; /* CRTC2 registers */ CARD32 crtc2_gen_cntl; @@ -171,8 +184,8 @@ typedef struct { int post_div; /* PLL registers */ - unsigned ppll_ref_div; - unsigned ppll_div_3; + CARD32 ppll_ref_div; + CARD32 ppll_div_3; CARD32 htotal_cntl; /* Computed values for PLL2 */ @@ -248,16 +261,10 @@ typedef enum { CHIP_FAMILY_RV280, CHIP_FAMILY_R300, CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_LAST + CHIP_FAMILY_RV350 } RADEONChipFamily; typedef struct { - CARD32 freq; - CARD32 value; -}RADEONTMDSPll; - -typedef struct { EntityInfoPtr pEnt; pciVideoPtr PciInfo; PCITAG PciTag; @@ -284,8 +291,8 @@ typedef struct { RADEONDDCType DDCType; RADEONConnectorType ConnectorType; Bool HasCRTC2; /* All cards except original Radeon */ - Bool IsMobility; /* Mobile chips for laptops */ - Bool IsIGP; /* IGP chips */ + Bool IsMobility; /* Mobile chips for laptops */ + Bool IsIGP; /* IGP chips */ Bool IsSecondary; /* Second Screen */ Bool IsSwitching; /* Flag for switching mode */ Bool Clone; /* Force second head to clone primary*/ @@ -298,7 +305,7 @@ typedef struct { Bool OverlayOnCRTC2; Bool PanelOff; /* Force panel (LCD/DFP) off */ int FPBIOSstart; /* Start of the flat panel info */ - Bool ddc_mode; /* Validate mode by matching exactly + Bool ddc_mode; /* Validate mode by matching exactly * the modes supported in DDC data */ Bool R300CGWorkaround; @@ -318,6 +325,7 @@ typedef struct { int FeedbackDivider; int PostDivider; Bool UseBiosDividers; + /* EDID data using DDC interface */ Bool ddc_bios; Bool ddc1; @@ -326,12 +334,7 @@ typedef struct { CARD32 DDCReg; RADEONPLLRec pll; - RADEONTMDSPll tmds_pll[4]; - int RamWidth; - float sclk; /* in MHz */ - float mclk; /* in MHz */ - Bool IsDDR; - int DispPriority; + RADEONRAMPtr ram; RADEONSaveRec SavedReg; /* Original (text) mode */ RADEONSaveRec ModeReg; /* Current mode */ @@ -675,7 +678,7 @@ do { \ "ADVANCE_RING() start: %d used: %d count: %d\n", \ info->indirectStart, \ info->indirectBuffer->used, \ - __count * (int)sizeof(CARD32)); \ + __count * sizeof(CARD32)); \ } \ info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ } while (0) diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 52955d4..8556cc2 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.36 2003/11/10 18:41:22 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.34 2003/07/02 17:31:29 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -295,10 +295,8 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN); #endif - /* Restore SURFACE_CNTL - only the first head contains valid data -ReneR */ - if (!info->IsSecondary) { - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); - } + /* Restore SURFACE_CNTL */ + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); RADEONWaitForFifo(pScrn, 1); OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX @@ -337,7 +335,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) #endif { OUTREG(RADEON_MC_FB_LOCATION, 0xffff0000); - OUTREG(RADEON_MC_AGP_LOCATION, 0xfffff000); + OUTREG(RADEON_MC_AGP_LOCATION, 0xfffff000); } #endif @@ -421,7 +419,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) stop.flush = 1; stop.idle = 1; - ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop, + ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop, sizeof(drmRadeonCPStop)); if (ret == 0) { @@ -431,10 +429,10 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) } stop.flush = 0; - + i = 0; do { - ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop, + ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop, sizeof(drmRadeonCPStop)); } while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY); @@ -501,7 +499,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) buf->used = 0; if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " GetBuffer returning %d %p\n", + " GetBuffer returning %d %08x\n", buf->idx, buf->address); } return buf; diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c index 0e30de6..843fd6b 100644 --- a/src/radeon_accelfuncs.c +++ b/src/radeon_accelfuncs.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.7tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.7 2003/04/06 20:07:33 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -1305,6 +1305,12 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) | HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY); if (xf86IsEntityShared(info->pEnt->index)) { + DevUnion *pPriv; + RADEONEntPtr pRADEONEnt; + + pPriv = xf86GetEntityPrivate(info->pEnt->index, gRADEONEntityIndex); + pRADEONEnt = pPriv->ptr; + /* If there are more than one devices sharing this entity, we * have to assign this call back, otherwise the XAA will be * disabled diff --git a/src/radeon_common.h b/src/radeon_common.h index 924c7ff..31e2a0b 100644 --- a/src/radeon_common.h +++ b/src/radeon_common.h @@ -31,8 +31,7 @@ * Converted to common header format: * Jens Owen <jens@tungstengraphics.com> * - * $XdotOrg: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.1.4.2 2003/12/06 13:24:24 kaleb Exp $ - * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.8tsi Exp $ + * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $ * */ @@ -72,7 +71,6 @@ #define DRM_RADEON_IRQ_EMIT 0x16 #define DRM_RADEON_IRQ_WAIT 0x17 #define DRM_RADEON_CP_RESUME 0x18 -#define DRM_RADEON_SETPARAM 0x19 #define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39 @@ -161,7 +159,7 @@ typedef struct { } drmRadeonTexImage; typedef struct { - unsigned int offset; + int offset; int pitch; int format; int width; /* Texture image coordinates */ @@ -172,7 +170,7 @@ typedef struct { #define RADEON_MAX_TEXTURE_UNITS 3 -/* Layout matches drm_radeon_state_t in linux drm_radeon.h. +/* Layout matches drm_radeon_state_t in linux drm_radeon.h. */ typedef struct { struct { @@ -235,7 +233,7 @@ typedef struct { unsigned int pp_border_color; } texture[RADEON_MAX_TEXTURE_UNITS]; struct { - unsigned int se_zbias_factor; + unsigned int se_zbias_factor; unsigned int se_zbias_constant; } zbias; unsigned int dirty; @@ -377,23 +375,23 @@ typedef struct { typedef union { int i; - struct { + struct { unsigned char cmd_type, pad0, pad1, pad2; } header; - struct { + struct { unsigned char cmd_type, packet_id, pad0, pad1; } packet; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } scalars; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } vectors; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; + struct { + unsigned char cmd_type, flags, pad0, pad1; } wait; } drmRadeonCmdHeader; @@ -433,7 +431,7 @@ typedef struct drm_radeon_mem_free { typedef struct drm_radeon_mem_init_heap { int region; int size; - int start; + int start; } drmRadeonMemInitHeap; /* 1.6: Userspace can request & wait on irq's: @@ -447,16 +445,4 @@ typedef struct drm_radeon_irq_wait { } drmRadeonIrqWait; -/* 1.10: Clients tell the DRM where they think the framebuffer is located in - * the card's address space, via a new generic ioctl to set parameters - */ - -typedef struct drm_radeon_set_param { - unsigned int param; - long long value; -} drmRadeonSetParam; - -#define RADEON_SETPARAM_FB_LOCATION 1 - - #endif diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index fe54cd9..ff15cef 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -103,16 +103,16 @@ static void RADEONSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg) if (info->cursor_argb) return; #endif - + fg |= 0xff000000; bg |= 0xff000000; - + /* Don't recolour the image if we don't have to. */ if (fg == info->cursor_fg && bg == info->cursor_bg) return; CURSOR_SWAPPING_START(); - + /* Note: We assume that the pixels are either fully opaque or fully * transparent, so we won't premultiply them, and we can just * check for non-zero pixel values; those are either fg or bg @@ -285,7 +285,7 @@ static void RADEONLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image) *d++ = mono_cursor_color[chunk & 3]; } CURSOR_SWAPPING_END(); - + info->cursor_bg = mono_cursor_color[2]; info->cursor_fg = mono_cursor_color[3]; @@ -362,7 +362,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs) if (!image) return; /* XXX can't happen */ - + if (!info->IsSecondary) { save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); save1 |= (CARD32) (2 << 20); @@ -378,7 +378,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs) #ifdef ARGB_CURSOR info->cursor_argb = TRUE; #endif - + CURSOR_SWAPPING_START(); w = pCurs->bits->width; @@ -413,7 +413,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs) } #endif - + /* Initialize hardware cursor support. */ Bool RADEONCursorInit(ScreenPtr pScreen) @@ -434,7 +434,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) cursor->Flags = (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | HARDWARE_CURSOR_AND_SOURCE_WITH_MASK #if X_BYTE_ORDER == X_BIG_ENDIAN - /* this is a lie -- + /* this is a lie -- * HARDWARE_CURSOR_BIT_ORDER_MSBFIRST * actually inverts the bit order, so * this switches to LSBFIRST @@ -472,7 +472,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) "Hardware cursor disabled" " due to insufficient offscreen memory\n"); } else { - info->cursor_start = RADEON_ALIGN((fbarea->box.x1 + + info->cursor_start = RADEON_ALIGN((fbarea->box.x1 + fbarea->box.y1 * width) * info->CurrentLayout.pixel_bytes, 256); diff --git a/src/radeon_dga.c b/src/radeon_dga.c index f5121dc..a0fe938 100644 --- a/src/radeon_dga.c +++ b/src/radeon_dga.c @@ -97,7 +97,7 @@ SECOND_PASS: pitch = secondPitch; if (!(newmodes = xrealloc(modes, (*num + 1) * sizeof(DGAModeRec)))) - break; + break; modes = newmodes; currentMode = modes + *num; @@ -106,7 +106,7 @@ SECOND_PASS: currentMode->flags = DGA_CONCURRENT_ACCESS; if (pixmap) - currentMode->flags |= DGA_PIXMAP_AVAILABLE; + currentMode->flags |= DGA_PIXMAP_AVAILABLE; if (info->accel) { if (info->accel->SetupForSolidFill && @@ -123,7 +123,7 @@ SECOND_PASS: if (pMode->Flags & V_DBLSCAN) currentMode->flags |= DGA_DOUBLESCAN; if (pMode->Flags & V_INTERLACE) - currentMode->flags |= DGA_INTERLACED; + currentMode->flags |= DGA_INTERLACED; currentMode->byteOrder = pScrn->imageByteOrder; currentMode->depth = depth; @@ -264,16 +264,16 @@ static Bool RADEON_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode) RADEONSwitchMode(indx, pScrn->currentMode, 0); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { RADEONCP_STOP(pScrn, info); - } + } #endif if (info->accelOn) RADEONEngineInit(pScrn); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { RADEONCP_START(pScrn, info); - } + } #endif RADEONAdjustFrame(indx, 0, 0, 0); info->DGAactive = FALSE; @@ -297,16 +297,16 @@ static Bool RADEON_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode) RADEONSwitchMode(indx, pMode->mode, 0); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { RADEONCP_STOP(pScrn, info); - } + } #endif if (info->accelOn) RADEONEngineInit(pScrn); #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (info->directRenderingEnabled) { RADEONCP_START(pScrn, info); - } + } #endif } diff --git a/src/radeon_dri.c b/src/radeon_dri.c index 0c6d555..2d36f87 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.39 2003/11/06 18:38:00 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.36 2003/07/09 01:45:22 dawes Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * VA Linux Systems Inc., Fremont, California. @@ -40,12 +40,12 @@ #include "radeon.h" #include "radeon_macros.h" #include "radeon_dri.h" +#include "radeon_pci.h" #include "radeon_reg.h" #include "radeon_version.h" /* X and server generic header files */ #include "xf86.h" -#include "xf86PciInfo.h" #include "windowstr.h" @@ -516,7 +516,7 @@ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx) { /* NOOP. There's no need for the 2d driver to be clearing buffers - * for the 3d client. It knows how to do that on its own. + * for the 3d client. It knows how to do that on its own. */ } @@ -716,8 +716,8 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) { unsigned char *RADEONMMIO = info->MMIO; unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */ - unsigned int vendor = drmAgpVendorId(info->drmFD); - unsigned int device = drmAgpDeviceId(info->drmFD); + unsigned long vendor = drmAgpVendorId(info->drmFD); + unsigned long device = drmAgpDeviceId(info->drmFD); mode &= ~RADEON_AGP_MODE_MASK; switch (info->agpMode) { @@ -727,7 +727,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) } if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE; - + if ((vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761)) { @@ -794,7 +794,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] %d kB allocated with handle 0x%08lx\n", + "[agp] %d kB allocated with handle 0x%08x\n", info->gartSize*1024, info->agpMemHandle); if (drmAgpBind(info->drmFD, @@ -903,7 +903,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] %d kB allocated with handle 0x%08lx\n", + "[pci] %d kB allocated with handle 0x%08x\n", info->gartSize*1024, info->pciMemHandle); RADEONDRIInitGARTValues(info); @@ -1077,7 +1077,7 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen) drmHeap.region = RADEON_MEM_REGION_GART; drmHeap.start = 0; drmHeap.size = info->gartTexMapSize; - + if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP, &drmHeap, sizeof(drmHeap))) { xf86DrvMsg(pScreen->myNum, X_ERROR, @@ -1239,7 +1239,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) (info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280) ) pDRIInfo->clientDriverName = R200_DRIVER_NAME; - else + else pDRIInfo->clientDriverName = RADEON_DRIVER_NAME; pDRIInfo->busIdString = xalloc(64); @@ -1366,20 +1366,20 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) (info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280)) { req_minor = 5; - req_patch = 0; + req_patch = 0; } else { #if X_BYTE_ORDER == X_LITTLE_ENDIAN req_minor = 1; req_patch = 0; #else req_minor = 2; - req_patch = 1; + req_patch = 1; #endif } if (version->version_major != 1 || version->version_minor < req_minor || - (version->version_minor == req_minor && + (version->version_minor == req_minor && version->version_patchlevel < req_patch)) { /* Incompatible drm version */ xf86DrvMsg(pScreen->myNum, X_ERROR, @@ -1449,9 +1449,9 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) { void *scratch_ptr; int scratch_int; - + DRIGetDeviceInfo(pScreen, &info->fbHandle, - &scratch_int, &scratch_int, + &scratch_int, &scratch_int, &scratch_int, &scratch_int, &scratch_ptr); } @@ -1594,10 +1594,10 @@ void RADEONDRIResume(ScreenPtr pScreen) RADEONSetAgpBase(info); } - _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME); - if (_ret) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP resume %d\n", __FUNCTION__, _ret); + _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME); + if (_ret) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "%s: CP resume %d\n", __FUNCTION__, _ret); /* FIXME: return? */ } @@ -1898,10 +1898,10 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) } else { xf86DrvMsg(pScreen->myNum, X_WARNING, "[dri] RADEONDRITransitionTo2d: " - "kernel failed to unflip buffers.\n"); + "kernel failed to unflip buffers.\n"); } - xf86FreeOffscreenArea(info->depthTexArea); + xf86FreeOffscreenArea(info->depthTexArea); info->have3DWindows = 0; diff --git a/src/radeon_dripriv.h b/src/radeon_dripriv.h index 8859316..5f01192 100644 --- a/src/radeon_dripriv.h +++ b/src/radeon_dripriv.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dripriv.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dripriv.h,v 1.4 2002/10/30 12:52:13 alanh Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * VA Linux Systems Inc., Fremont, California. diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 1efa07a..4f56827 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.117 2004/02/19 22:38:12 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.104 2003/08/23 15:02:54 dawes Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -61,6 +61,7 @@ /* Driver data structures */ #include "radeon.h" #include "radeon_macros.h" +#include "radeon_pci.h" #include "radeon_probe.h" #include "radeon_reg.h" #include "radeon_version.h" @@ -80,7 +81,6 @@ /* X and server generic header files */ #include "xf86.h" #include "xf86_OSproc.h" -#include "xf86PciInfo.h" #include "xf86RAC.h" #include "xf86Resources.h" #include "xf86cmap.h" @@ -93,9 +93,6 @@ #ifndef MAX #define MAX(a,b) ((a)>(b)?(a):(b)) #endif -#ifndef MIN -#define MIN(a,b) ((a)>(b)?(b):(a)) -#endif /* Forward definitions for driver functions */ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); @@ -106,7 +103,6 @@ static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode); static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags); -static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); typedef enum { OPTION_NOACCEL, @@ -115,7 +111,6 @@ typedef enum { OPTION_DAC_8BIT, #ifdef XF86DRI OPTION_IS_PCI, - OPTION_BUS_TYPE, OPTION_CP_PIO, OPTION_USEC_TIMEOUT, OPTION_AGP_MODE, @@ -136,10 +131,7 @@ typedef enum { OPTION_CLONE_HSYNC, OPTION_CLONE_VREFRESH, OPTION_FBDEV, - OPTION_VIDEO_KEY, - OPTION_DISP_PRIORITY, - OPTION_PANEL_SIZE, - OPTION_MIN_DOTCLOCK + OPTION_VIDEO_KEY } RADEONOpts; const OptionInfoRec RADEONOptions[] = { @@ -149,12 +141,10 @@ const OptionInfoRec RADEONOptions[] = { { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, #ifdef XF86DRI { OPTION_IS_PCI, "ForcePCIMode", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_GART_SIZE, "AGPSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, @@ -172,12 +162,15 @@ const OptionInfoRec RADEONOptions[] = { { OPTION_CLONE_VREFRESH, "CloneVRefresh", OPTV_ANYSTR, {0}, FALSE }, { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, - { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, { -1, NULL, OPTV_NONE, {0}, FALSE } }; +RADEONRAMRec RADEONRAM[] = { /* Memory Specifications + From Radeon Manual */ + { 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SDRAM" }, + { 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SDRAM" }, +}; + static const char *vgahwSymbols[] = { "vgaHWFreeHWRec", "vgaHWGetHWRec", @@ -377,7 +370,7 @@ static struct {1024, 768, 87}, {832, 624, 75}, {800, 600, 75}, - {800, 600, 72}, + {800, 600, 72}, {800, 600, 60}, {800, 600, 56}, {640, 480, 75}, @@ -388,24 +381,6 @@ static struct {720, 400, 70}, }; -static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = -{ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_UNKNOW*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_LEGACY*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RADEON*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV100*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS100*/ - {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV200*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS200*/ - {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/ - {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/ - {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x400f7/*0x40111*/}, {0, 0}}, /*CHIP_FAMILY_RV280*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/ -}; - extern int gRADEONEntityIndex; struct RADEONInt10Save { @@ -439,7 +414,7 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); - /* + /* * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 */ OUTREG(RADEON_MEM_CNTL, 0); @@ -468,20 +443,20 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) * the saved registers. */ CardTmp = INREG(RADEON_MEM_CNTL); - if (!CardTmp || - ((CardTmp & 1) && + if (!CardTmp || + ((CardTmp & 1) && (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { /* Restore the saved registers */ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring MEM_CNTL (%08lx), setting to %08lx\n", - (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); + "Restoring MEM_CNTL (%08x), setting to %08x\n", + CardTmp, pSave->MEM_CNTL); OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); CardTmp = INREG(RADEON_CONFIG_MEMSIZE); if (CardTmp != pSave->MEMSIZE) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", - (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); + "Restoring CONFIG_MEMSIZE (%08x), setting to %08x\n", + CardTmp, pSave->MEMSIZE); OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); } } @@ -489,9 +464,8 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) CardTmp = INREG(RADEON_MPP_TB_CONFIG); if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", - (unsigned long)CardTmp >> 24, - (unsigned long)pSave->MPP_TB_CONFIG >> 24); + "Restoring MPP_TB_CONFIG<31:24> (%02x), setting to %02x\n", + CardTmp >> 24, pSave->MPP_TB_CONFIG >> 24); CardTmp &= 0x00ffffffu; CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); @@ -811,7 +785,7 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT OUTREG(info->DDCReg, INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1)); - for (i = 0; i < 10; i++) { + for (i = 0; i < 3; i++) { usleep(15000); if (INREG(info->DDCReg) & RADEON_GPIO_Y_1) break; @@ -864,7 +838,7 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT info->DDCReg = DDCReg; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DDC Type: %d, Detected Type: %d\n", DDCType, MonType); return MonType; @@ -875,7 +849,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int bConnected = 0; + int bConnected = 0; /* the monitor either wasn't connected or it is a non-DDC CRT. * try to probe it @@ -901,7 +875,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) ulData = ulOrigCRTC_EXT_CNTL; ulData |= RADEON_CRTC_CRT_ON; OUTREG(RADEON_CRTC_EXT_CNTL, ulData); - + ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL); ulData = ulOrigDAC_EXT_CNTL; ulData &= ~RADEON_DAC_FORCE_DATA_MASK; @@ -928,7 +902,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) ulData = INREG(RADEON_DAC_CNTL); bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0; - + ulData = ulOrigVCLK_ECP_CNTL; ulMask = 0xFFFFFFFFL; OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask); @@ -938,10 +912,10 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); } else { /* TV DAC */ - /* This doesn't seem to work reliably (maybe worse on some OEM cards), - for now we always return false. If one wants to connected a - non-DDC monitor on the DVI port when CRT port is also connected, - he will need to explicitly tell the driver in the config file + /* This doesn't seem to work reliably (maybe worse on some OEM cards), + for now we always return false. If one wants to connected a + non-DDC monitor on the DVI port when CRT port is also connected, + he will need to explicitly tell the driver in the config file with Option MonitorLayout. */ bConnected = FALSE; @@ -1005,7 +979,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) ulData = INREG(RADEON_GPIO_MONID); bConnected = (ulData & RADEON_GPIO_Y_0)?1:0; if (!bConnected) break; - + usleep(1000); } @@ -1031,7 +1005,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) unsigned long ulOrigDAC_CNTL2; unsigned long ulData; unsigned long ulMask; - + ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL); ulData = ulOrigPIXCLKSDATA; @@ -1047,10 +1021,10 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) OUTREG(RADEON_TV_MASTER_CNTL, ulData); ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2); - ulData = ulOrigDAC_CNTL2; + ulData = ulOrigDAC_CNTL2; ulData &= ~RADEON_DAC2_DAC2_CLK_SEL; OUTREG(RADEON_DAC_CNTL2, ulData); - + ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL); ulData = 0x00880213; @@ -1075,12 +1049,12 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) usleep(1000); ulData = INREG(RADEON_TV_DAC_CNTL); - bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0; + bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0; ulData = ulOrigPIXCLKSDATA; ulMask = 0xFFFFFFFFL; OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask); - + OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL); OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2); OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL); @@ -1088,7 +1062,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) } #endif } - + return(bConnected ? MT_CRT : MT_NONE); } @@ -1107,7 +1081,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn (info->VBIOS[(v) + 1] << 8) | \ (info->VBIOS[(v) + 2] << 16) | \ (info->VBIOS[(v) + 3] << 24)) - + pRADEONEnt->MonType1 = MT_NONE; pRADEONEnt->MonType2 = MT_NONE; pRADEONEnt->MonInfo1 = NULL; @@ -1121,16 +1095,16 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn */ if (xf86GetOptValBool(info->Options, OPTION_IGNORE_EDID, &ignore_edid)) { if (ignore_edid) - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "IgnoreEDID is specified, EDID data will be ignored\n"); + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "IgnoreEDID is specified, EDID data will be ignored\n"); } - /* + /* * MonitorLayout option takes a string for two monitors connected in following format: * Option "MonitorLayout" "primary-port-display, secondary-port-display" - * primary and secondary port displays can have one of following: - * NONE, CRT, LVDS, TMDS - * With this option, driver will bring up monitors as specified, + * primary and secondary port displays can have one of following: + * NONE, CRT, LVDS, TMDS + * With this option, driver will bring up monitors as specified, * not using auto-detection routines to probe monitors. */ @@ -1149,7 +1123,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn * CRTC1 -> FP/TMDS -> DVI port -> TMDS panel --> Primary or * CRTC1 -> FP/LVDS -> Int. LCD -> LVDS panel --> Primary or * CRTC1 -> TV DAC -> DVI port -> CRT monitor --> Primary - * + * * Only VGA (can be DVI on some dual-DVI boards) connected: * CRTC1 -> CRT DAC -> VGA port -> CRT monitor --> Primary or * CRTC1 -> FP2/Ext. -> DVI port -> TMDS panel --> Primary (not supported) @@ -1159,19 +1133,19 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn * otherwise, VGA port will be treated as 1st port * * Here we always treat DVI port as primary if both ports are connected. - * When only one port is connected, it will be treated as - * primary regardless which port or what type of display is involved. + * When only one port is connected, it will be treated as + * primary regardless which port or what type of display is involved. */ if ((s = xf86GetOptValString(info->Options, OPTION_MONITOR_LAYOUT))) { char s1[5], s2[5]; int i = 0, second = 0; - + /* When using user specified monitor types, we will not do DDC detection - * + * */ do { - switch(*s) + switch(*s) { case ',': s1[i] = '\0'; @@ -1202,9 +1176,9 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn pRADEONEnt->MonType1 = MT_DFP; else if (strcmp(s1, "LVDS") == 0) pRADEONEnt->MonType1 = MT_LCD; - else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Invalid Monitor type specified for 1st port \n"); + else + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Invalid Monitor type specified for 1st port \n"); if (strcmp(s2, "NONE") == 0) pRADEONEnt->MonType2 = MT_NONE; else if (strcmp(s2, "CRT") == 0) @@ -1213,20 +1187,20 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn pRADEONEnt->MonType2 = MT_DFP; else if (strcmp(s2, "LVDS") == 0) pRADEONEnt->MonType2 = MT_LCD; - else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Invalid Monitor type specified for 2nd port \n"); + else + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Invalid Monitor type specified for 2nd port \n"); if (!ignore_edid) { if (pRADEONEnt->MonType1) /* assuming the first port using DDC_DVI */ - if(!RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)) { + if(!RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)) { RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1); ddc_crt2_used = TRUE; - } + } if (pRADEONEnt->MonType2) { /* assuming the second port using DDC_VGA/DDC_CRT2 */ if(!RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2)) if (!ddc_crt2_used) - RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2); + RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2); } } @@ -1236,8 +1210,8 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; } else { pRADEONEnt->MonType1 = MT_CRT; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No valid monitor specified, force to CRT on 1st port\n"); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "No valid monitor specified, force to CRT on 1st port\n"); } pRADEONEnt->MonType2 = MT_NONE; pRADEONEnt->MonInfo2 = NULL; @@ -1284,8 +1258,8 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn * If that's the case, we need also reverse the port arrangement. * BIOS settings are supposed report this correctly, work fine for all cards tested. * But there may be some exceptions, in that case, user can reverse their monitor - * definition in config file to correct the problem. - */ + * definition in config file to correct the problem. + */ if (info->VBIOS && (tmp = RADEON_BIOS16(info->FPBIOSstart + 0x50))) { for (i = 1; i < 4; i++) { unsigned int tmp0; @@ -1297,7 +1271,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn } if ((((tmp0 >> 8) & 0x0f) == DDC_DVI ) && ((tmp0 >> 4) & 0x1)) { pRADEONEnt->ReversedTMDS = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed TMDS detected\n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed TMDS detected\n"); } } } @@ -1305,10 +1279,10 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn /* Primary Head (DVI or Laptop Int. panel)*/ /* A ddc capable display connected on DVI port */ if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1))); - else if((pRADEONEnt->MonType1 = + else if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1))) { ddc_crt2_used = TRUE; - } else if ((info->IsMobility) && + } else if ((info->IsMobility) && (info->VBIOS && (INREG(RADEON_BIOS_4_SCRATCH) & 4))) { /* non-DDC laptop panel connected on primary */ pRADEONEnt->MonType1 = MT_LCD; @@ -1319,17 +1293,30 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn } /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ - if((pRADEONEnt->MonType2 = + if((pRADEONEnt->MonType2 = RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2))); - else if(!ddc_crt2_used) - pRADEONEnt->MonType2 = + else if(!ddc_crt2_used) + pRADEONEnt->MonType2 = RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2); if (!pRADEONEnt->MonType2) pRADEONEnt->MonType2 = RADEONCrtIsPhysicallyConnected(pScrn, !pRADEONEnt->ReversedDAC); + /* no display detected on DVI port*/ + if (pRADEONEnt->MonType1 == MT_NONE) { + if (pRADEONEnt->MonType2 != MT_NONE) { + /* Only one detected on VGA, let it to be primary */ + pRADEONEnt->MonType1 = pRADEONEnt->MonType2; + pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; + pRADEONEnt->MonType2 = MT_NONE; + } else { + /* Non detected, Default to a CRT connected */ + pRADEONEnt->MonType1 = MT_CRT; + } + } + if(pRADEONEnt->ReversedTMDS) { /* always keep internal TMDS as primary head */ - if (pRADEONEnt->MonType1 == MT_DFP || + if (pRADEONEnt->MonType1 == MT_DFP || pRADEONEnt->MonType2 == MT_DFP) { int tmp1 = pRADEONEnt->MonType1; xf86MonPtr MonInfo = pRADEONEnt->MonInfo1; @@ -1337,35 +1324,21 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn pRADEONEnt->MonInfo2 = MonInfo; pRADEONEnt->MonType1 = pRADEONEnt->MonType2; pRADEONEnt->MonType2 = tmp1; - if ((pRADEONEnt->MonType1 == MT_CRT) || + if ((pRADEONEnt->MonType1 == MT_CRT) || (pRADEONEnt->MonType2 == MT_CRT)) { pRADEONEnt->ReversedDAC ^= 1; } } } - - /* no display detected on DVI port*/ - if (pRADEONEnt->MonType1 == MT_NONE) { - if (pRADEONEnt->MonType2 != MT_NONE) { - /* Only one detected on VGA, let it to be primary */ - pRADEONEnt->MonType1 = pRADEONEnt->MonType2; - pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; - pRADEONEnt->MonType2 = MT_NONE; - pRADEONEnt->MonInfo2 = NULL; - } else { - /* Non detected, Default to a CRT connected */ - pRADEONEnt->MonType1 = MT_CRT; - } - } } if(s) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Displays Configured by MonitorLayout: \n\tMonitor1--Type %d, Monitor2--Type %d\n\n", + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Displays Configured by MonitorLayout: \n\tMonitor1--Type %d, Monitor2--Type %d\n\n", pRADEONEnt->MonType1, pRADEONEnt->MonType2); } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Displays Detected: Monitor1--Type %d, Monitor2--Type %d\n\n", + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Displays Detected: Monitor1--Type %d, Monitor2--Type %d\n\n", pRADEONEnt->MonType1, pRADEONEnt->MonType2); } @@ -1386,7 +1359,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor2 EDID data --------------------\n"); } } - + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n"); info->OverlayOnCRTC2 = FALSE; @@ -1394,7 +1367,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn info->OverlayOnCRTC2 = TRUE; } - if (pRADEONEnt->MonType2 == MT_NONE) + if (pRADEONEnt->MonType2 == MT_NONE) pRADEONEnt->HasSecondary = FALSE; } @@ -1404,6 +1377,7 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned long tmp, i; + unsigned char *RADEONMMIO; if (!(info->VBIOS = xalloc(RADEON_VBIOS_SIZE))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -1445,35 +1419,34 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONMMIO = info->MMIO; info->Clone = FALSE; info->CloneType = MT_NONE; - if(info->HasCRTC2) { - if(info->IsSecondary) { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2; - if(info->DisplayType == MT_NONE) return FALSE; + if(info->HasCRTC2) { + if(info->IsSecondary) { + if(!(info->DisplayType = pRADEONEnt->MonType2)) return FALSE; } else { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1; + info->DisplayType = pRADEONEnt->MonType1; if(!pRADEONEnt->HasSecondary) { - info->CloneType = (RADEONMonitorType)pRADEONEnt->MonType2; - if (info->CloneType != MT_NONE) + if ((info->CloneType = pRADEONEnt->MonType2)) info->Clone = TRUE; - } + } } } else { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1; + info->DisplayType = pRADEONEnt->MonType1; } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s Display == Type %d\n", - (info->IsSecondary ? "Secondary" : "Primary"), + (info->IsSecondary ? "Secondary" : "Primary"), info->DisplayType); if (info->Clone) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone Display == Type %d\n", info->CloneType); - + info->HBlank = 0; info->HOverPlus = 0; info->HSyncWidth = 0; @@ -1483,8 +1456,7 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->DotClock = 0; info->UseBiosDividers = FALSE; - if (info->DisplayType == MT_LCD && info->VBIOS && - !(xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { + if (info->DisplayType == MT_LCD && info->VBIOS) { tmp = RADEON_BIOS16(info->FPBIOSstart + 0x40); if (!tmp) { info->PanelPwrDly = 200; @@ -1505,7 +1477,7 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->PanelYRes = RADEON_BIOS16(tmp+27); xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", info->PanelXRes, info->PanelYRes); - + info->PanelPwrDly = RADEON_BIOS16(tmp+44); if (info->PanelPwrDly > 2000 || info->PanelPwrDly < 0) info->PanelPwrDly = 2000; @@ -1515,18 +1487,14 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->RefDivider = RADEON_BIOS16(tmp+46); info->PostDivider = RADEON_BIOS8(tmp+48); info->FeedbackDivider = RADEON_BIOS16(tmp+49); - if ((info->RefDivider != 0) && + if ((info->RefDivider != 0) && (info->FeedbackDivider > 3)) { info->UseBiosDividers = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS provided dividers will be used.\n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "BIOS provided dividers will be used."); } - /* We don't use a while loop here just in case we have a corrupted BIOS image. - The max number of table entries is 23 at present, but may grow in future. - To ensure it works with future revisions we loop it to 32. - */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 20; i++) { tmp0 = RADEON_BIOS16(tmp+64+i*2); if (tmp0 == 0) break; if ((RADEON_BIOS16(tmp0) == info->PanelXRes) && @@ -1545,60 +1513,9 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->Flags = 0; } } - - if (info->DotClock == 0) { - DisplayModePtr tmp_mode = NULL; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No valid timing info from BIOS.\n"); - /* No timing information for the native mode, - use whatever specified in the Modeline. - If no Modeline specified, we'll just pick - the VESA mode at 60Hz refresh rate which - is likely to be the best for a flat panel. - */ - tmp_mode = pScrn->monitor->Modes; - while(tmp_mode) { - if ((tmp_mode->HDisplay == info->PanelXRes) && - (tmp_mode->VDisplay == info->PanelYRes)) { - - float refresh = - (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal; - if ((abs(60.0 - refresh) < 1.0) || - (tmp_mode->type == 0)) { - info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay; - info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay; - info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart; - info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay; - info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay; - info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart; - info->DotClock = tmp_mode->Clock; - info->Flags = 0; - break; - } - tmp_mode = tmp_mode->next; - } - } - if ((info->DotClock == 0) && !pRADEONEnt->MonInfo1) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Panel size is not correctly detected.\n" - "Please try to use PanelSize option for correct settings.\n"); - return FALSE; - } - } } - } - } - - if (info->VBIOS) { - tmp = RADEON_BIOS16(info->FPBIOSstart + 0x30); - info->sclk = RADEON_BIOS16(tmp + 8) / 100.0; - info->mclk = RADEON_BIOS16(tmp + 10) / 100.0; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No valid info for SCLK/MCLK for display bandwidth calculation.\n"); - info->sclk = 200.00; - info->mclk = 200.00; - } - + } + } return TRUE; } @@ -1615,25 +1532,27 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs; int i; + tmp = INREG(RADEON_DEVICE_ID); + for(i=0; i<1000000; i++) if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) break; - + xf86getsecs(&start_secs, &start_usecs); - + for(i=0; i<1000000; i++) if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) break; - + for(i=0; i<1000000; i++) if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) break; - + xf86getsecs(&stop_secs, &stop_usecs); - + total_usecs = abs(stop_usecs - start_usecs); hz = 1000000/total_usecs; - + hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0x3ff) + 1); vclk = (float)(hTotal * (float)(vTotal * hz)); @@ -1657,7 +1576,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) denom = 2*m; break; } - + OUTREG(RADEON_CLOCK_CNTL_INDEX, 1); ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_DATA + 1) & 0x3; @@ -1666,7 +1585,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) num *= n; denom *= m; - + switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { case 1: denom *= 2; @@ -1681,7 +1600,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) denom *= 3; break; case 6: - denom *= 6; + denom *= 6; break; case 7: denom *= 12; @@ -1714,56 +1633,6 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) return TRUE; } -static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 tmp; - int i, n; - - for (i=0; i<4; i++) { - info->tmds_pll[i].value = 0; - info->tmds_pll[i].freq = 0; - } - - if (info->VBIOS) { - tmp = RADEON_BIOS16(info->FPBIOSstart + 0x34); - if (tmp) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "DFP table revision: %d\n", RADEON_BIOS8(tmp)); - if (RADEON_BIOS8(tmp) == 3) { - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - info->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); - info->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); - } - return; - } - - /* revision 4 has some problem as it appears in RV280, - comment it off for new, use default instead */ - /* - else if (RADEON_BIOS8(tmp) == 4) { - int stride = 0; - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - info->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); - info->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); - if (i == 0) stride += 10; - else stride += 6; - } - return; - } - */ - } - } - - for (i=0; i<4; i++) { - info->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value; - info->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq; - } -} /* Read PLL parameters from BIOS block. Default to typical values if * there is no BIOS. @@ -1774,22 +1643,22 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn) RADEONPLLPtr pll = &info->pll; CARD16 bios_header; CARD16 pll_info_block; - double min_dotclock; if (!info->VBIOS) { pll->min_pll_freq = 12500; pll->max_pll_freq = 35000; - + if (!RADEONProbePLLParameters(pScrn)) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected, using default PLL parameters!\n"); + "Video BIOS not detected, using default PLL parameters!\n"); switch (info->Chipset) { case PCI_CHIP_R200_QL: case PCI_CHIP_R200_QN: case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Ql: case PCI_CHIP_R200_BB: pll->reference_freq = 2700; pll->reference_div = 12; @@ -1811,7 +1680,7 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn) default: pll->reference_freq = 2700; pll->reference_div = 67; - pll->xclk = 16615; + pll->xclk = 16615; break; } } @@ -1828,26 +1697,6 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn) pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); } - /* (Some?) Radeon BIOSes seem too lie about their minimum dot - * clocks. Allow users to override the detected minimum dot clock - * value (e.g., and allow it to be suitable for TV sets). - */ - if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, - OPTUNITS_MHZ, &min_dotclock)) { - if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Illegal minimum dotclock specified %.2f MHz " - "(option ignored)\n", - min_dotclock); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Forced minimum dotclock to %.2f MHz " - "(instead of detected %.2f MHz)\n", - min_dotclock, ((double)pll->min_pll_freq/1000)); - pll->min_pll_freq = min_dotclock * 1000; - } - } - return TRUE; } @@ -1940,44 +1789,6 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) return TRUE; } -static void RADEONGetVRamType(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; - - if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || - (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) - info->IsDDR = TRUE; - else - info->IsDDR = FALSE; - - tmp = INREG(RADEON_MEM_CNTL); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { - tmp &= R300_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: info->RamWidth = 64; break; - case 1: info->RamWidth = 128; break; - case 2: info->RamWidth = 256; break; - default: info->RamWidth = 128; break; - } - } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)){ - if (tmp & RV100_HALF_MODE) info->RamWidth = 32; - else info->RamWidth = 64; - } else { - if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; - else info->RamWidth = 64; - } - - /* This may not be correct, as some cards can have half of channel disabled - * ToDo: identify these cases - */ -} - /* This is called by RADEONPreInit to handle config file overrides for * things like chipset and memory regions. Also determine memory size * and type. If memory type ever needs an override, put it in this @@ -1988,12 +1799,9 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); EntityInfoPtr pEnt = info->pEnt; GDevPtr dev = pEnt->device; + int offset = 0; /* RAM Type */ MessageType from; unsigned char *RADEONMMIO = info->MMIO; -#ifdef XF86DRI - const char *s; - CARD32 agpCommand; -#endif /* Chipset */ from = X_PROBED; @@ -2060,27 +1868,45 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) break; case PCI_CHIP_R200_BB: - case PCI_CHIP_R200_BC: case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QI: + case PCI_CHIP_R200_QJ: + case PCI_CHIP_R200_QK: case PCI_CHIP_R200_QL: case PCI_CHIP_R200_QM: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Qh: + case PCI_CHIP_R200_Qi: + case PCI_CHIP_R200_Qj: + case PCI_CHIP_R200_Qk: + case PCI_CHIP_R200_Ql: info->ChipFamily = CHIP_FAMILY_R200; break; + case PCI_CHIP_RV200_QW: /* RV200 desktop */ + case PCI_CHIP_RV200_QX: + info->ChipFamily = CHIP_FAMILY_RV200; + break; + case PCI_CHIP_RADEON_LW: case PCI_CHIP_RADEON_LX: info->IsMobility = TRUE; - case PCI_CHIP_RV200_QW: /* RV200 desktop */ - case PCI_CHIP_RV200_QX: info->ChipFamily = CHIP_FAMILY_RV200; break; + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + info->ChipFamily = CHIP_FAMILY_RV250; + break; + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: case PCI_CHIP_RV250_Lf: case PCI_CHIP_RV250_Lg: info->IsMobility = TRUE; - case PCI_CHIP_RV250_If: - case PCI_CHIP_RV250_Ig: info->ChipFamily = CHIP_FAMILY_RV250; break; @@ -2091,13 +1917,18 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) info->IsIGP = TRUE; break; - case PCI_CHIP_RV280_5C61: - case PCI_CHIP_RV280_5C63: - info->IsMobility = TRUE; case PCI_CHIP_RV280_5960: case PCI_CHIP_RV280_5961: case PCI_CHIP_RV280_5962: - case PCI_CHIP_RV280_5964: + case PCI_CHIP_RV280_5963: + info->ChipFamily = CHIP_FAMILY_RV280; + break; + + case PCI_CHIP_RV280_5968: + case PCI_CHIP_RV280_5969: + case PCI_CHIP_RV280_596A: + case PCI_CHIP_RV280_596B: + info->IsMobility = TRUE; info->ChipFamily = CHIP_FAMILY_RV280; break; @@ -2113,29 +1944,15 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) break; case PCI_CHIP_RV350_NP: - case PCI_CHIP_RV350_NQ: - case PCI_CHIP_RV350_NR: - case PCI_CHIP_RV350_NS: - case PCI_CHIP_RV350_NT: - case PCI_CHIP_RV350_NV: info->IsMobility = TRUE; case PCI_CHIP_RV350_AP: - case PCI_CHIP_RV350_AQ: - case PCI_CHIP_RV360_AR: - case PCI_CHIP_RV350_AS: - case PCI_CHIP_RV350_AT: - case PCI_CHIP_RV350_AV: + case PCI_CHIP_RV350_AR: info->ChipFamily = CHIP_FAMILY_RV350; break; - case PCI_CHIP_R350_AH: - case PCI_CHIP_R350_AI: - case PCI_CHIP_R350_AJ: case PCI_CHIP_R350_AK: case PCI_CHIP_R350_NH: - case PCI_CHIP_R350_NI: case PCI_CHIP_R350_NK: - case PCI_CHIP_R360_NJ: info->ChipFamily = CHIP_FAMILY_R350; break; @@ -2152,7 +1969,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) pScrn->memPhysBase = info->LinearAddr; if (dev->MemBase) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Linear address override, using 0x%08lx instead of 0x%08lx\n", + "Linear address override, using 0x%08x instead of 0x%08x\n", dev->MemBase, info->LinearAddr); info->LinearAddr = dev->MemBase; @@ -2170,7 +1987,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; if (dev->BiosBase) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS address override, using 0x%08lx instead of 0x%08lx\n", + "BIOS address override, using 0x%08x instead of 0x%08x\n", dev->BiosBase, info->BIOSAddr); info->BIOSAddr = dev->BiosBase; @@ -2181,15 +1998,15 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) "BIOS at 0x%08lx\n", info->BIOSAddr); } - /* Read registers used to determine options */ + /* Read registers used to determine options */ from = X_PROBED; if (info->FBDev) pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024; - else if ((info->ChipFamily == CHIP_FAMILY_RS100) || + else if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300)) { CARD32 tom = INREG(RADEON_NB_TOM); - pScrn->videoRam = (((tom >> 16) - + pScrn->videoRam = (((tom >> 16) - (tom & 0xffff) + 1) << 6); OUTREG(RADEON_MC_FB_LOCATION, tom); OUTREG(RADEON_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); @@ -2198,10 +2015,10 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) /* This is supposed to fix the crtc2 noise problem. */ - OUTREG(RADEON_GRPH2_BUFFER_CNTL, + OUTREG(RADEON_GRPH2_BUFFER_CNTL, INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000); - if ((info->ChipFamily == CHIP_FAMILY_RS100) || + if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200)) { /* This is to workaround the asic bug for RMX, some versions of BIOS dosen't have this register initialized correctly. @@ -2241,7 +2058,13 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); info->BusCntl = INREG(RADEON_BUS_CNTL); - RADEONGetVRamType(pScrn); + /* RAM */ + switch (info->MemCntl >> 30) { + case 0: offset = 0; break; /* 64-bit SDR SDRAM */ + case 1: offset = 1; break; /* 64-bit DDR SDRAM */ + default: offset = 0; + } + info->ram = &RADEONRAM[offset]; if (dev->videoRam) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -2254,92 +2077,70 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) pScrn->videoRam &= ~1023; info->FbMapSize = pScrn->videoRam * 1024; xf86DrvMsg(pScrn->scrnIndex, from, - "VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); + "VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name); #ifdef XF86DRI /* AGP/PCI */ - /* Proper autodetection of an AGP capable device requires examining - * PCI config registers to determine if the device implements extended - * PCI capabilities, and then walking the capability list as indicated - * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP - * capability is present. The procedure is outlined as follows: - * - * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device - * to determine wether or not this device implements any extended - * capabilities. If this bit is zero, then the device is a PCI 2.1 - * or earlier device and is not AGP capable, and we can conclude it - * to be a PCI device. - * - * 2) If bit 4 of the status register is set, then the device implements - * extended capabilities. There is an 8 bit wide capabilities pointer - * register located at offset 0x34 in PCI config space which points to - * the first capability in a linked list of extended capabilities that - * this device implements. The lower two bits of this register are - * reserved and MBZ so must be masked out. - * - * 3) The extended capabilities list is formed by one or more extended - * capabilities structures which are aligned on DWORD boundaries. - * The first byte of the structure is the capability ID (CAP_ID) - * indicating what extended capability this structure refers to. The - * second byte of the structure is an offset from the beginning of - * PCI config space pointing to the next capability in the linked - * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower - * two bits of this pointer are reserved and MBZ. By examining the - * CAP_ID of each capability and walking through the list, we will - * either find the AGP_CAP_ID (0x02) indicating this device is an - * AGP device, or we'll reach the end of the list, indicating it is - * a PCI device. - * - * Mike A. Harris <mharris@redhat.com> - * - * References: - * - PCI Local Bus Specification Revision 2.2, Chapter 6 - * - AGP Interface Specification Revision 2.0, Section 6.1.5 - */ - - info->IsPCI = TRUE; - - if (pciReadLong(info->PciTag, PCI_CMD_STAT_REG) & RADEON_CAP_LIST) { - CARD32 cap_ptr, cap_id; - - cap_ptr = pciReadLong(info->PciTag, - RADEON_CAPABILITIES_PTR_PCI_CONFIG) - & RADEON_CAP_PTR_MASK; - - while(cap_ptr != RADEON_CAP_ID_NULL) { - cap_id = pciReadLong(info->PciTag, cap_ptr); - if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { - info->IsPCI = FALSE; - break; - } - cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; - } - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", - (info->IsPCI) ? "PCI" : "AGP"); - - if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { - if (strcmp(s, "AGP") == 0) { - info->IsPCI = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); - } else if (strcmp(s, "PCI") == 0) { - info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); - } else if (strcmp(s, "PCIE") == 0) { - info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "PCI Express not supported yet, using PCI mode\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Invalid BusType option, using detected type\n"); - } - } else if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) { + if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) { info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "ForcePCIMode is deprecated -- " - "use BusType option instead\n"); + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI-only mode\n"); + } else { + switch (info->Chipset) { +#if 0 + case PCI_CHIP_RADEON_XX: info->IsPCI = TRUE; break; +#endif + case PCI_CHIP_RV100_QY: + case PCI_CHIP_RV100_QZ: + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + case PCI_CHIP_RADEON_QD: + case PCI_CHIP_RADEON_QE: + case PCI_CHIP_RADEON_QF: + case PCI_CHIP_RADEON_QG: + case PCI_CHIP_R200_BB: + case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QI: + case PCI_CHIP_R200_QJ: + case PCI_CHIP_R200_QK: + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QM: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Qh: + case PCI_CHIP_R200_Qi: + case PCI_CHIP_R200_Qj: + case PCI_CHIP_R200_Qk: + case PCI_CHIP_R200_Ql: + case PCI_CHIP_RV200_QW: + case PCI_CHIP_RV200_QX: + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + case PCI_CHIP_RV280_5960: + case PCI_CHIP_RV280_5961: + case PCI_CHIP_RV280_5962: + case PCI_CHIP_RV280_5963: + case PCI_CHIP_RV280_5968: + case PCI_CHIP_RV280_5969: + case PCI_CHIP_RV280_596A: + case PCI_CHIP_RV280_596B: + case PCI_CHIP_R300_AD: + case PCI_CHIP_R300_AE: + case PCI_CHIP_R300_AF: + case PCI_CHIP_R300_AG: + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + default: info->IsPCI = FALSE; break; + } } #endif @@ -2371,9 +2172,6 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) val |= (Clock ? 0:RADEON_GPIO_EN_1); val |= (data ? 0:RADEON_GPIO_EN_0); OUTREG(info->DDCReg, val); - - /* read back to improve reliability on some cards. */ - val = INREG(info->DDCReg); } static Bool RADEONI2cInit(ScrnInfoPtr pScrn) @@ -2503,7 +2301,7 @@ static void RADEONSortModes(DisplayModePtr *new, DisplayModePtr *first, p = *last; while (p) { - if ((((*new)->HDisplay < p->HDisplay) && + if ((((*new)->HDisplay < p->HDisplay) && ((*new)->VDisplay < p->VDisplay)) || (((*new)->HDisplay == p->HDisplay) && ((*new)->VDisplay == p->VDisplay) && @@ -2522,7 +2320,7 @@ static void RADEONSortModes(DisplayModePtr *new, DisplayModePtr *first, p->prev = *new; *first = *new; break; - } + } p = p->prev; } @@ -2548,7 +2346,7 @@ static void RADEONSetPitch (ScrnInfoPtr pScrn) pScrn->displayWidth = dummy; } -/* When no mode provided in config file, this will add all modes supported in +/* When no mode provided in config file, this will add all modes supported in * DDC date the pScrn->modes list */ static DisplayModePtr RADEONDDCModes(ScrnInfoPtr pScrn) @@ -2658,7 +2456,7 @@ static DisplayModePtr RADEONDDCModes(ScrnInfoPtr pScrn) strcpy(new->name, p->name); new->status = MODE_OK; new->type = M_T_DEFAULT; - + count++; xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -2786,7 +2584,7 @@ static int RADEONValidateDDCModes(ScrnInfoPtr pScrn, char **ppModeName, } } - /* + /* * Add remaining DDC modes if they're smaller than the user * specified modes */ @@ -2939,7 +2737,7 @@ static int RADEONValidateFPModes(ScrnInfoPtr pScrn, char **ppModeName) new->HSyncEnd = new->HSyncStart + info->HSyncWidth; new->VTotal = info->PanelYRes + info->VBlank; new->VSyncStart = info->PanelYRes + info->VOverPlus; - new->VSyncEnd = new->VSyncStart + info->VSyncWidth; + new->VSyncEnd = new->VSyncStart + info->VSyncWidth; new->Clock = info->DotClock; new->Flags |= RADEON_USE_RMX; @@ -2990,7 +2788,7 @@ static int RADEONValidateFPModes(ScrnInfoPtr pScrn, char **ppModeName) new->HSyncEnd = new->HSyncStart + info->HSyncWidth; new->VTotal = info->PanelYRes + info->VBlank; new->VSyncStart = info->PanelYRes + info->VOverPlus; - new->VSyncEnd = new->VSyncStart + info->VSyncWidth; + new->VSyncEnd = new->VSyncStart + info->VSyncWidth; new->Clock = info->DotClock; new->Flags |= RADEON_USE_RMX; @@ -3168,12 +2966,12 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) else count++; clone_mode_names[0] = xnfalloc(strlen(s)+1); sprintf(clone_mode_names[0], "%dx%d", tmp_hdisplay, tmp_vdisplay); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone mode %s in config file is used\n", clone_mode_names[0]); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone mode %s in config file is used\n"); } } for (i = 0; i < count; i++) { - if (sscanf(clone_mode_names[i], "%dx%d", + if (sscanf(clone_mode_names[i], "%dx%d", &tmp_hdisplay, &tmp_vdisplay) == 2) { if (pScrn->display->virtualX < tmp_hdisplay) pScrn->display->virtualX = tmp_hdisplay; @@ -3230,8 +3028,8 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) if (info->CloneType == MT_CRT && !ddc_mode) { modesFound = - xf86ValidateModes(pScrn, pScrn->monitor->Modes, - clone_mode_names, + xf86ValidateModes(pScrn, pScrn->monitor->Modes, + clone_mode_names, clockRanges, NULL, /* linePitches */ 8 * 64, /* minPitch */ @@ -3241,7 +3039,7 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) 2048, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, - info->FbMapSize, + info->FbMapSize, LOOKUP_BEST_REFRESH); } else { /* Try to add DDC modes */ @@ -3255,8 +3053,8 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) */ if (modesFound < 1 && info->CloneType != MT_CRT) { modesFound = - xf86ValidateModes(pScrn, pScrn->monitor->Modes, - clone_mode_names, + xf86ValidateModes(pScrn, pScrn->monitor->Modes, + clone_mode_names, clockRanges, NULL, /* linePitches */ 8 * 64, /* minPitch */ @@ -3266,7 +3064,7 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) 2048, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, - info->FbMapSize, + info->FbMapSize, LOOKUP_BEST_REFRESH); } } @@ -3300,7 +3098,7 @@ static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) clone_mode->prev->next = clone_mode; } valid++; - + tmp_mode = clone_mode; clone_mode->next = NULL; } @@ -3362,7 +3160,6 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) ClockRangePtr clockRanges; int modesFound; RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - char *s; /* This option has two purposes: * @@ -3434,7 +3231,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) } xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Validating modes on %s head ---------\n", + "Validating modes on %s head ---------\n", info->IsSecondary ? "Secondary" : "Primary"); if (info->IsSecondary) @@ -3448,59 +3245,6 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) "No DDC data available, DDCMode option is dismissed\n"); } - if ((info->DisplayType == MT_DFP) || - (info->DisplayType == MT_LCD)) { - if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { - int PanelX, PanelY; - DisplayModePtr tmp_mode = NULL; - if (sscanf(s, "%dx%d", &PanelX, &PanelY) == 2) { - info->PanelXRes = PanelX; - info->PanelYRes = PanelY; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Panel size is forced to: %s\n", s); - - /* We can't trust BIOS or DDC timings anymore, - Use whatever specified in the Modeline. - If no Modeline specified, we'll just pick the VESA mode at - 60Hz refresh rate which is likely to be the best for a flat panel. - */ - info->ddc_mode = FALSE; - pScrn->monitor->DDC = NULL; - tmp_mode = pScrn->monitor->Modes; - while(tmp_mode) { - if ((tmp_mode->HDisplay == PanelX) && - (tmp_mode->VDisplay == PanelY)) { - - float refresh = - (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal; - if ((abs(60.0 - refresh) < 1.0) || - (tmp_mode->type == 0)) { - info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay; - info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay; - info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart; - info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay; - info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay; - info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart; - info->DotClock = tmp_mode->Clock; - info->Flags = 0; - break; - } - } - tmp_mode = tmp_mode->next; - } - if (info->DotClock == 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No valid timing info for specified panel size.\n" - "Please specify the Modeline for this panel\n"); - return FALSE; - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Invalid PanelSize value: %s\n", s); - } - } - } - if (pScrn->monitor->DDC) { /* If we still don't know sync range yet, let's try EDID. * @@ -3579,14 +3323,14 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) * add the flat panel modes */ if (info->DisplayType != MT_CRT) { - + /* some panels have DDC, but don't have internal scaler. * in this case, we need to validate additional modes * by using on-chip RMX. */ int user_modes_asked = 0, user_modes_found = 0, i; DisplayModePtr tmp_mode = pScrn->modes; - while (pScrn->display->modes[user_modes_asked]) user_modes_asked++; + while (pScrn->display->modes[user_modes_asked]) user_modes_asked++; if (tmp_mode) { for (i = 0; i < modesFound; i++) { if (tmp_mode->type & M_T_USERDEF) user_modes_found++; @@ -3594,8 +3338,8 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) } } - if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) { - /* when panel size is not valid, try to validate + if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) { + /* when panel size is not valid, try to validate * mode using xf86ValidateModes routine * This can happen when DDC is disabled. */ @@ -3617,7 +3361,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) LOOKUP_BEST_REFRESH); else if (!info->IsSecondary) modesFound = RADEONValidateFPModes(pScrn, pScrn->display->modes); - } + } } /* Setup the screen's clockRanges for the VidMode extension */ @@ -3653,9 +3397,9 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) if ((clone_mode->HDisplay > pScrn->virtualX) || (clone_mode->VDisplay > pScrn->virtualY)) { pScrn->virtualX = - pScrn->display->virtualX = clone_mode->HDisplay; + pScrn->display->virtualX = clone_mode->HDisplay; pScrn->virtualY = - pScrn->display->virtualY = clone_mode->VDisplay; + pScrn->display->virtualY = clone_mode->VDisplay; RADEONSetPitch(pScrn); } if (!clone_mode->next) break; @@ -3774,7 +3518,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling AGP Fast Write\n"); } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AGP Fast Write disabled by default\n"); } } @@ -3853,7 +3597,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) * for dedicated 3d rendering boxes */ info->noBackBuffer = xf86ReturnOptValBool(info->Options, - OPTION_NO_BACKBUFFER, + OPTION_NO_BACKBUFFER, FALSE); if (info->noBackBuffer) { @@ -3894,7 +3638,6 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) RADEONInfoPtr info; xf86Int10InfoPtr pInt10 = NULL; void *int10_save = NULL; - const char *s; RADEONTRACE(("RADEONPreInit\n")); if (pScrn->numEntities != 1) return FALSE; @@ -3919,7 +3662,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info->MMIOAddr = info->PciInfo->memBase[2] & 0xffffff00; if (info->pEnt->device->IOBase) { xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "MMIO address override, using 0x%08lx instead of 0x%08lx\n", + "MMIO address override, using 0x%08x instead of 0x%08x\n", info->pEnt->device->IOBase, info->MMIOAddr); info->MMIOAddr = info->pEnt->device->IOBase; @@ -3931,7 +3674,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) "MMIO registers at 0x%08lx\n", info->MMIOAddr); if(!RADEONMapMMIO(pScrn)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Memory map the MMIO region failed\n"); goto fail1; } @@ -3945,7 +3688,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) * going to run it again - so make sure to "fix up" the card * so that (1) we can read the BIOS ROM and (2) the BIOS will * get the memory config right. - */ + */ RADEONPreInt10Save(pScrn, &int10_save); #endif @@ -4027,18 +3770,6 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info->videoKey = 0x1E; } - info->DispPriority = 1; - if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { - if (strcmp(s, "AUTO") == 0) { - info->DispPriority = 1; - } else if (strcmp(s, "BIOS") == 0) { - info->DispPriority = 0; - } else if (strcmp(s, "HIGH") == 0) { - info->DispPriority = 2; - } else - info->DispPriority = 1; - } - if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE)) { /* check for Linux framebuffer device */ @@ -4074,9 +3805,6 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONGetBIOSParameters(pScrn, pInt10)) goto fail; - if (info->DisplayType == MT_DFP) - RADEONGetTMDSInfo(pScrn); - if (!RADEONGetPLLParameters(pScrn)) goto fail; if (!RADEONPreInitGamma(pScrn)) goto fail; @@ -4101,7 +3829,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (pInt10) xf86FreeInt10(pInt10); - if(info->MMIO) RADEONUnmapMMIO(pScrn); + if(info->MMIO) RADEONUnmapMMIO(pScrn); info->MMIO = NULL; xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, @@ -4129,7 +3857,7 @@ fail: vgaHWFreeHWRec(pScrn); fail2: - if(info->MMIO) RADEONUnmapMMIO(pScrn); + if(info->MMIO) RADEONUnmapMMIO(pScrn); info->MMIO = NULL; fail1: RADEONFreeRec(pScrn); @@ -4236,7 +3964,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, g = colors[idx].green; b = colors[idx / 2].blue; OUTPAL(idx * 4, r, g, b); - + /* AH - Added to write extra green data - How come * this isn't needed on R128? We didn't load the * extra green data in the other routine. @@ -4392,7 +4120,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) /* Xinerama has sync problem with DRI, disable it for now */ if (xf86IsEntityShared(info->pEnt->index)) { info->directRenderingEnabled = FALSE; - xf86DrvMsg(scrnIndex, X_WARNING, + xf86DrvMsg(scrnIndex, X_WARNING, "Direct Rendering Disabled -- " "Dual-head configuration is not working with " "DRI at present.\n" @@ -4503,7 +4231,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize; } if (info->textureSize < (int)info->FbMapSize / 2) { - info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; + info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; } /* If there's still no space for textures, try without pixmap cache */ if (info->textureSize < 0) { @@ -4734,7 +4462,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) int width, height; xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using hardware cursor (scanline %ld)\n", + "Using hardware cursor (scanline %d)\n", info->cursor_start / pScrn->displayWidth / info->CurrentLayout.pixel_bytes); if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, @@ -4788,10 +4516,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); } if (info->directRenderingEnabled) { - if ((info->DispPriority == 1) && (!info->IsPCI)) { - /* we need to re-calculate bandwidth because of AGPMode difference. */ - RADEONInitDispBandwidth(pScrn); - } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering disabled\n"); @@ -4898,7 +4622,6 @@ static void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); - OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl); } /* Write CRTC2 registers */ @@ -4935,8 +4658,8 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); - if ((info->DisplayType == MT_DFP && info->IsSecondary) || - info->CloneType == MT_DFP) { + if ((info->DisplayType == MT_DFP && info->IsSecondary) || + info->CloneType == MT_DFP) { OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid); OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid); OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); @@ -4964,11 +4687,11 @@ static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch); OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); - /* old AIW Radeon has some BIOS initialization problem + /* old AIW Radeon has some BIOS initialization problem * with display buffer underflow, only occurs to DFP - */ + */ if (!info->HasCRTC2) - OUTREG(RADEON_GRPH_BUFFER_CNTL, + OUTREG(RADEON_GRPH_BUFFER_CNTL, INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); if (info->DisplayType != MT_DFP) { @@ -4981,7 +4704,7 @@ static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) */ if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) { OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); - } + } } tmp = INREG(RADEON_LVDS_GEN_CNTL); @@ -5068,10 +4791,10 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; if (info->IsMobility) { - /* A temporal workaround for the occational blanking on certain laptop panels. - This appears to related to the PLL divider registers (fail to lock?). - It occurs even when all dividers are the same with their old settings. - In this case we really don't need to fiddle with PLL registers. + /* A temporal workaround for the occational blanking on certain laptop panels. + This appears to related to the PLL divider registers (fail to lock?). + It occurs even when all dividers are the same with their old settings. + In this case we really don't need to fiddle with PLL registers. By doing this we can avoid the blanking problem with some panels. */ if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && @@ -5097,7 +4820,6 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, ~(RADEON_PLL_DIV_SEL)); if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_R350) || (info->ChipFamily == CHIP_FAMILY_RV350)) { if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { @@ -5110,7 +4832,7 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, } else { /* R300 uses ref_div_acc field as real ref divider */ OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, - (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), + (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), ~R300_PPLL_REF_DIV_ACC_MASK); } } else { @@ -5339,8 +5061,6 @@ static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL); save->bus_cntl = INREG(RADEON_BUS_CNTL); save->surface_cntl = INREG(RADEON_SURFACE_CNTL); - save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); - save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); } /* Read miscellaneous registers which might be destroyed by an fbdevHW call */ @@ -5382,7 +5102,6 @@ static void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); save->crtc_pitch = INREG(RADEON_CRTC_PITCH); save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); - save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL); } /* Read flat panel registers */ @@ -5403,11 +5122,6 @@ static void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL); save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL); save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); - - if (info->ChipFamily == CHIP_FAMILY_RV280) { - /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ - save->tmds_pll_cntl ^= (1 << 22); - } } /* Read CRTC2 registers */ @@ -5495,12 +5209,12 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONTRACE(("RADEONSaveMode(%p)\n", save)); - RADEONSaveCommonRegisters(pScrn, save); if (info->IsSecondary) { RADEONSaveCrtc2Registers(pScrn, save); RADEONSavePLL2Registers(pScrn, save); } else { RADEONSavePLLRegisters(pScrn, save); + RADEONSaveCommonRegisters(pScrn, save); RADEONSaveCrtcRegisters(pScrn, save); RADEONSaveFPRegisters(pScrn, save); @@ -5576,8 +5290,6 @@ static void RADEONRestore(ScrnInfoPtr pScrn) if (info->R300CGWorkaround) R300CGWorkaround(pScrn); OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); - OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); - OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); #if 0 /* M6 card has trouble restoring text mode for its CRT. @@ -5650,322 +5362,6 @@ static void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; } -/* Calculate display buffer watermark to prevent buffer underflow */ -static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONInfoPtr info2 = NULL; - - DisplayModePtr mode1, mode2; - - CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; - float mem_tcas; - int k1, c; - CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; - CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4}; - CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - - CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; - - float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; - float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; - float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5}; - - float mem_bw, peak_disp_bw; - float min_mem_eff = 0.8; - float sclk_eff, sclk_delay; - float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; - float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2; - float pix_clk, pix_clk2; /* in MHz */ - int cur_size = 16; /* in octawords */ - int critical_point, critical_point2; - int stop_req, max_stop_req; - float read_return_rate, time_disp1_drop_priority; - - if (pRADEONEnt->pSecondaryScrn) { - if (info->IsSecondary) return; - info2 = RADEONPTR(pRADEONEnt->pSecondaryScrn); - } else if (info->Clone) info2 = info; - - /* - * Determine if there is enough bandwidth for current display mode - */ - mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); - - mode1 = info->CurrentLayout.mode; - if (info->Clone) - mode2 = info->CurCloneMode; - else if ((pRADEONEnt->HasSecondary) && info2) - mode2 = info2->CurrentLayout.mode; - else - mode2 = NULL; - - pix_clk = mode1->Clock/1000.0; - if (mode2) - pix_clk2 = mode2->Clock/1000.0; - else - pix_clk2 = 0; - - peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes); - if (info2) - peak_disp_bw += (pix_clk2 * info2->CurrentLayout.pixel_bytes); - - if (peak_disp_bw >= mem_bw * min_mem_eff) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "You may not have enough display bandwidth for current mode\n" - "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); - } - - /* CRTC1 - Set GRPH_BUFFER_CNTL register using h/w defined optimal values. - GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] - */ - stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; - - /* setup Max GRPH_STOP_REQ default value */ - if ((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200) || - (info->ChipFamily == CHIP_FAMILY_RS300)) - max_stop_req = 0x5c; - else - max_stop_req = 0x7c; - if (stop_req > max_stop_req) - stop_req = max_stop_req; - - /* Get values from the EXT_MEM_CNTL register...converting its contents. */ - temp = INREG(RADEON_MEM_TIMING_CNTL); - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2]; - mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0]; - mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4]; - } else { /* RV200 and later */ - mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0]; - mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8]; - mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12]; - } - - /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ - temp = INREG(RADEON_MEM_SDRAM_MODE_REG); - data = (temp & (7<<20)) >> 20; - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - mem_tcas = MemTcas [data]; - } else { - mem_tcas = MemTcas2 [data]; - } - - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { - - /* on the R300, Tcas is included in Trbs. - */ - temp = INREG(RADEON_MEM_CNTL); - data = (R300_MEM_NUM_CHANNELS_MASK & temp); - if (data == 2) { - if (R300_MEM_USE_CD_CH_ONLY & temp) { - temp = INREG(R300_MC_IND_INDEX); - temp &= ~R300_MC_IND_ADDR_MASK; - temp |= R300_MC_READ_CNTL_CD_mcind; - OUTREG(R300_MC_IND_INDEX, temp); - temp = INREG(R300_MC_IND_DATA); - data = (R300_MEM_RBS_POSITION_C_MASK & temp); - } else { - temp = INREG(R300_MC_READ_CNTL_AB); - data = (R300_MEM_RBS_POSITION_A_MASK & temp); - } - } else { - temp = INREG(R300_MC_READ_CNTL_AB); - data = (R300_MEM_RBS_POSITION_A_MASK & temp); - } - - mem_trbs = MemTrbs[data]; - mem_tcas += mem_trbs; - } - - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - /* DDR64 SCLK_EFF = SCLK for analysis */ - sclk_eff = info->sclk; - } else { -#ifdef XF86DRI - if (info->directRenderingEnabled) - sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0); - else -#endif - sclk_eff = info->sclk; - } - - /* Find the memory controller latency for the display client. - */ - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { - /*not enough for R350 ???*/ - /* - if (!mode2) sclk_delay = 150; - else { - if (info->RamWidth == 256) sclk_delay = 87; - else sclk_delay = 97; - } - */ - sclk_delay = 250; - } else { - if ((info->ChipFamily == CHIP_FAMILY_RV100) || - info->IsIGP) { - if (info->IsDDR) sclk_delay = 41; - else sclk_delay = 33; - } else { - if (info->RamWidth == 128) sclk_delay = 57; - else sclk_delay = 41; - } - } - - mc_latency_sclk = sclk_delay / sclk_eff; - - if (info->IsDDR) { - if (info->RamWidth == 32) { - k1 = 40; - c = 3; - } else { - k1 = 20; - c = 1; - } - } else { - k1 = 40; - c = 3; - } - mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) / - info->mclk) + (4.0 / sclk_eff); - - /* - HW cursor time assuming worst case of full size colour cursor. - */ - cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk; - cur_latency_sclk = cur_size / sclk_eff; - - /* - Find the total latency for the display data. - */ - disp_latency_overhead = 8.0 / info->sclk; - mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk; - mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; - disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); - - /* - Find the drain rate of the display buffer. - */ - disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes); - if (info2) - disp_drain_rate2 = pix_clk2 / (16.0/info2->CurrentLayout.pixel_bytes); - else - disp_drain_rate2 = 0; - - /* - Find the critical point of the display buffer. - */ - critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); - - /* ???? */ - /* - temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; - if (critical_point < temp) critical_point = temp; - */ - if (info->DispPriority == 2) { - if (mode2) { - /*??some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ - if (info->ChipFamily == CHIP_FAMILY_R300) - critical_point += 0x10; - else - critical_point = 0; - } - else - critical_point = 0; - } - - /* - The critical point should never be above max_stop_req-4. Setting - GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. - */ - if (max_stop_req - critical_point < 4) critical_point = 0; - - temp = info->SavedReg.grph_buffer_cntl; - temp &= ~(RADEON_GRPH_STOP_REQ_MASK); - temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); - temp &= ~(RADEON_GRPH_START_REQ_MASK); - if ((info->ChipFamily == CHIP_FAMILY_R350) && - (stop_req > 0x15)) { - stop_req -= 0x10; - } - temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); - - temp |= RADEON_GRPH_BUFFER_SIZE; - temp &= ~(RADEON_GRPH_CRITICAL_CNTL | - RADEON_GRPH_CRITICAL_AT_SOF | - RADEON_GRPH_STOP_CNTL); - /* - Write the result into the register. - */ - OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | - (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - - RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n", - info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL))); - - if (mode2) { - stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16; - - if (stop_req > max_stop_req) stop_req = max_stop_req; - - temp = info->SavedReg.grph2_buffer_cntl; - temp &= ~(RADEON_GRPH_STOP_REQ_MASK); - temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); - temp &= ~(RADEON_GRPH_START_REQ_MASK); - if ((info->ChipFamily == CHIP_FAMILY_R350) && - (stop_req > 0x15)) { - stop_req -= 0x10; - } - temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); - temp |= RADEON_GRPH_BUFFER_SIZE; - temp &= ~(RADEON_GRPH_CRITICAL_CNTL | - RADEON_GRPH_CRITICAL_AT_SOF | - RADEON_GRPH_STOP_CNTL); - - if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)) - critical_point2 = 0; - else { - read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); - time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); - - critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority + - disp_latency) * disp_drain_rate2 + 0.5); - - if (info->DispPriority == 2) { - if (info->ChipFamily == CHIP_FAMILY_R300) - critical_point2 += 0x10; - else - critical_point2 = 0; - } - - if (max_stop_req - critical_point2 < 4) critical_point2 = 0; - - } - - OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | - (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - - RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n", - info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL))); - } -} - /* Define CRTC registers for requested video mode */ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, RADEONInfoPtr info) @@ -5977,22 +5373,24 @@ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, int hsync_wid; int hsync_fudge; int vsync_wid; + int bytpp; int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; int hsync_fudge_fp[] = { 0x02, 0x02, 0x00, 0x00, 0x05, 0x05 }; switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ + case 4: format = 1; bytpp = 0; break; + case 8: format = 2; bytpp = 1; break; + case 15: format = 3; bytpp = 2; break; /* 555 */ + case 16: format = 4; bytpp = 2; break; /* 565 */ + case 24: format = 5; bytpp = 3; break; /* RGB */ + case 32: format = 6; bytpp = 4; break; /* xRGB */ default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel); return FALSE; } + RADEONTRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp)); if ((info->DisplayType == MT_DFP) || (info->DisplayType == MT_LCD)) { @@ -6089,31 +5487,18 @@ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, (pScrn->bitsPerPixel * 8)); save->crtc_pitch |= save->crtc_pitch << 16; - /* Some versions of BIOS setup CRTC_MORE_CNTL for a DFP, if we - have a CRT here, it should be cleared to avoild a blank screen. - */ - if (info->DisplayType == MT_CRT) - save->crtc_more_cntl = (info->SavedReg.crtc_more_cntl & - ~(RADEON_CRTC_H_CUTOFF_ACTIVE_EN | - RADEON_CRTC_V_CUTOFF_ACTIVE_EN)); - else - save->crtc_more_cntl = info->SavedReg.crtc_more_cntl; - save->surface_cntl = 0; save->disp_merge_cntl = info->SavedReg.disp_merge_cntl; save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; #if X_BYTE_ORDER == X_BIG_ENDIAN - /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */ switch (pScrn->bitsPerPixel) { case 16: save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; - save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; break; case 32: save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; - save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; break; } #endif @@ -6136,21 +5521,23 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, int hsync_wid; int hsync_fudge; int vsync_wid; + int bytpp; int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ + case 4: format = 1; bytpp = 0; break; + case 8: format = 2; bytpp = 1; break; + case 15: format = 3; bytpp = 2; break; /* 555 */ + case 16: format = 4; bytpp = 2; break; /* 565 */ + case 24: format = 5; bytpp = 3; break; /* RGB */ + case 32: format = 6; bytpp = 4; break; /* xRGB */ default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel); return FALSE; } + RADEONTRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp)); hsync_fudge = hsync_fudge_default[format-1]; @@ -6180,10 +5567,10 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK | RADEON_DISP_DAC2_SOURCE_MASK); if (pRADEONEnt->MonType1 != MT_CRT) { - save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 | + save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 | RADEON_DISP_DAC2_SOURCE_CRTC2); } else { - if (pRADEONEnt->ReversedDAC) { + if (pRADEONEnt->ReversedDAC) { save->disp_output_cntl |= RADEON_DISP_DAC2_SOURCE_CRTC2; } else { save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; @@ -6201,7 +5588,7 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL; } else { - if (pRADEONEnt->ReversedDAC) { + if (pRADEONEnt->ReversedDAC) { save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; } else { @@ -6258,7 +5645,7 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl; save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); - if ((info->DisplayType == MT_DFP && info->IsSecondary) || + if ((info->DisplayType == MT_DFP && info->IsSecondary) || info->CloneType == MT_DFP) { save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8)); save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid; @@ -6280,15 +5667,23 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; } - if (pScrn->rgbBits == 8) + if (pScrn->rgbBits == 8) save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format */ else save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format */ /* FIXME: When there are two DFPs, the 2nd DFP is driven by the * external TMDS transmitter. It may have a problem at - * high dot clock for certain panels. + * high dot clock for certain panels. Since we don't + * know how to control the external TMDS transmitter, not + * much we can do here. */ +#if 0 + if (save->dot_clock_freq > 15000) + save->tmds_pll_cntl = 0xA3F; + else if(save->tmds_pll_cntl != 0xA3F) + save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl; +#endif /* If BIOS has not turned it on, we'll keep it on so that we'll * have a valid VGA screen even after X quits or VT is switched @@ -6313,8 +5708,8 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, int yres = mode->VDisplay; float Hratio, Vratio; - /* If the FP registers have been initialized before for a panel, - * but the primary port is a CRT, we need to reinitialize + /* If the FP registers have been initialized before for a panel, + * but the primary port is a CRT, we need to reinitialize * FP registers in order for CRT to work properly */ @@ -6352,7 +5747,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) { save->fp_horz_stretch = orig->fp_horz_stretch; save->fp_horz_stretch &= ~(RADEON_HORZ_STRETCH_BLEND | - RADEON_HORZ_STRETCH_ENABLE); + RADEON_HORZ_STRETCH_ENABLE); save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO | RADEON_HORZ_PANEL_SIZE); save->fp_horz_stretch |= ((xres/8-1)<<16); @@ -6407,7 +5802,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR | RADEON_FP_CRTC_DONT_SHADOW_HEND ); - if (pScrn->rgbBits == 8) + if (pScrn->rgbBits == 8) save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ else save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ @@ -6415,6 +5810,16 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, save->lvds_gen_cntl = orig->lvds_gen_cntl; save->lvds_pll_cntl = orig->lvds_pll_cntl; + /* This is needed for some panel at high resolution (>=1600x1200) + */ + if ((save->dot_clock_freq > 15000) && + (info->ChipFamily != CHIP_FAMILY_R300) && + (info->ChipFamily != CHIP_FAMILY_R350) && + (info->ChipFamily != CHIP_FAMILY_RV350)) + save->tmds_pll_cntl = 0xA3F; + else + save->tmds_pll_cntl = orig->tmds_pll_cntl; + info->PanelOff = FALSE; /* This option is used to force the ONLY DEVICE in XFConfig to use * CRT port, instead of default DVI port. @@ -6423,7 +5828,6 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, info->PanelOff = TRUE; } - save->tmds_pll_cntl = orig->tmds_pll_cntl; save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl; if (info->PanelOff && info->Clone) { info->OverlayOnCRTC2 = TRUE; @@ -6452,28 +5856,13 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); } else if (info->DisplayType == MT_DFP) { - int i; - CARD32 tmp = orig->tmds_pll_cntl & 0xfffff; - for (i=0; i<4; i++) { - if (info->tmds_pll[i].freq == 0) break; - if (save->dot_clock_freq < info->tmds_pll[i].freq) { - tmp = info->tmds_pll[i].value ; - break; - } - } - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350) || - (info->ChipFamily == CHIP_FAMILY_RV280)) { - if (tmp & 0xfff00000) - save->tmds_pll_cntl = tmp; - else - save->tmds_pll_cntl = (orig->tmds_pll_cntl & 0xfff00000) | tmp; - } else save->tmds_pll_cntl = tmp; - - RADEONTRACE(("TMDS_PLL from %x to %x\n", - orig->tmds_pll_cntl, - save->tmds_pll_cntl)); + /* This is needed for some panel at high resolution (>=1600x1200) + */ + if ((save->dot_clock_freq > 15000) && + (info->ChipFamily != CHIP_FAMILY_R300) && + (info->ChipFamily != CHIP_FAMILY_R350) && + (info->ChipFamily != CHIP_FAMILY_RV350)) + save->tmds_pll_cntl = 0xA3F; save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST); if ((info->ChipFamily == CHIP_FAMILY_R300) || @@ -6484,7 +5873,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig, else /* weird, RV chips got this bit reversed? */ save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); - save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); + save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); } } @@ -6677,12 +6066,12 @@ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode, info->Flags = mode->Flags; - RADEONInitCommonRegisters(save, info); if (info->IsSecondary) { if (!RADEONInitCrtc2Registers(pScrn, save, mode, info)) return FALSE; RADEONInitPLL2Registers(save, &info->pll, dot_clock); } else { + RADEONInitCommonRegisters(save, info); if (!RADEONInitCrtcRegisters(pScrn, save, mode, info)) return FALSE; dot_clock = mode->Clock/1000.0; @@ -6728,10 +6117,6 @@ static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode) RADEONUnblank(pScrn); info->CurrentLayout.mode = mode; - - if (info->DispPriority) - RADEONInitDispBandwidth(pScrn); - return TRUE; } @@ -6777,7 +6162,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) if (info->Clone && info->CloneModes) { DisplayModePtr clone_mode = info->CloneModes; - /* Try to match a mode on primary head + /* Try to match a mode on primary head * FIXME: This may not be good if both heads don't have * exactly the same list of mode. */ @@ -6854,8 +6239,8 @@ Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, #endif /* Used to disallow modes that are not supported by the hardware */ -ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, - Bool verbose, int flag) +int RADEONValidMode(int scrnIndex, DisplayModePtr mode, + Bool verbose, int flag) { /* There are problems with double scan mode at high clocks * They're likely related PLL and display buffer settings. @@ -6899,7 +6284,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, int clone) #ifdef XF86DRI if (info->directRenderingEnabled) { - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); if (clone || info->IsSecondary) { pSAREAPriv->crtc2_base = Base; @@ -6962,7 +6347,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONDRIResume(pScrn->pScreen); } #endif - /* this will get XVideo going again, but only if XVideo was initialised + /* this will get XVideo going again, but only if XVideo was initialised during server startup (hence the info->adaptor if). */ if (info->adaptor) RADEONResetVideo(pScrn); @@ -7070,79 +6455,12 @@ void RADEONFreeScreen(int scrnIndex, int flags) RADEONFreeRec(pScrn); } -/* - * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant). - * - * Note for current DAC mapping when calling this function: - * For most of cards: - * single CRT: Driver doesn't change the existing CRTC->DAC mapping, - * CRTC1 could be driving either DAC or both DACs. - * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC - * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC. - * Some boards have two DACs reversed or don't even have a primary DAC, - * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't - * have a second DAC. - * It's kind of messy, we'll need to redo DAC mapping part some day. - */ -static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IsPrimaryDAC) { - CARD32 dac_cntl; - CARD32 dac_macro_cntl = 0; - dac_cntl = INREG(RADEON_DAC_CNTL); - if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) - dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); - if (IsOn) { - dac_cntl &= ~RADEON_DAC_PDWN; - dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | - RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - } else { - dac_cntl |= RADEON_DAC_PDWN; - dac_macro_cntl |= (RADEON_DAC_PDWN_R | - RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - } - OUTREG(RADEON_DAC_CNTL, dac_cntl); - if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) - OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); - } else { - if (info->ChipFamily != CHIP_FAMILY_R200) { - CARD32 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - if (IsOn) { - tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } else { - tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); - } else { - CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); - if (IsOn) { - fp2_gen_cntl |= RADEON_FP2_DV0_EN; - } else { - fp2_gen_cntl &= ~RADEON_FP2_DV0_EN; - } - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); - } - } -} - /* Sets VESA Display Power Management Signaling (DPMS) Mode */ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; #ifdef XF86DRI @@ -7161,6 +6479,8 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS); + /* TODO: additional handling for LCD ? */ + switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On; HSync: On, VSync: On */ @@ -7227,37 +6547,23 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, if (info->ChipFamily >= CHIP_FAMILY_R200) { OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); } - } else if (info->DisplayType == MT_CRT) { - RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); } } else { - if (info->Clone) { - if (info->CloneType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); - } - } else if (info->CloneType == MT_CRT) { - RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); + if ((info->Clone) && (info->CloneType == MT_DFP)) { + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); } } if (info->DisplayType == MT_DFP) { - OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN), + OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN), ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN)); } else if (info->DisplayType == MT_LCD) { OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON); usleep (info->PanelPwrDly * 1000); OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON); - } else if (info->DisplayType == MT_CRT) { - if ((pRADEONEnt->HasSecondary) || info->Clone) { - RADEONDacPowerSet(pScrn, TRUE, pRADEONEnt->ReversedDAC); - } else { - RADEONDacPowerSet(pScrn, TRUE, TRUE); - if (info->HasCRTC2) - RADEONDacPowerSet(pScrn, TRUE, FALSE); - } } } } else if ((PowerManagementMode == DPMSModeOff) || @@ -7270,19 +6576,13 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, if (info->ChipFamily >= CHIP_FAMILY_R200) { OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); } - } else if (info->DisplayType == MT_CRT) { - RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); } } else { - if (info->Clone) { - if(info->CloneType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); - } - } else if (info->CloneType == MT_CRT) { - RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); + if ((info->Clone) && (info->CloneType == MT_DFP)) { + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); } } if (info->DisplayType == MT_DFP) { @@ -7297,23 +6597,12 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); } - OUTREGP (RADEON_LVDS_GEN_CNTL, 0, + OUTREGP (RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON)); if (info->IsMobility || info->IsIGP) { OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl); } - } else if (info->DisplayType == MT_CRT) { - if ((pRADEONEnt->HasSecondary) || info->Clone) { - RADEONDacPowerSet(pScrn, FALSE, pRADEONEnt->ReversedDAC); - } else { - /* single CRT, turning both DACs off, we don't really know - * which DAC is actually connected. - */ - RADEONDacPowerSet(pScrn, FALSE, TRUE); - if (info->HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */ - RADEONDacPowerSet(pScrn, FALSE, FALSE); - } } } } diff --git a/src/radeon_macros.h b/src/radeon_macros.h index b420a30..5beaee8 100644 --- a/src/radeon_macros.h +++ b/src/radeon_macros.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v 1.2 2003/07/08 15:39:48 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v 1.3 2003/07/08 16:55:35 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. diff --git a/src/radeon_misc.c b/src/radeon_misc.c index c7671b7..d9c978f 100644 --- a/src/radeon_misc.c +++ b/src/radeon_misc.c @@ -1,6 +1,6 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c,v 1.7 2003/01/01 19:16:35 tsi Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -38,7 +38,7 @@ static XF86ModuleVersionInfo RADEONVersionRec = MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, - XORG_VERSION_CURRENT, + XF86_VERSION_CURRENT, RADEON_VERSION_MAJOR, RADEON_VERSION_MINOR, RADEON_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, diff --git a/src/radeon_probe.c b/src/radeon_probe.c index a8edceb..58a8a11 100644 --- a/src/radeon_probe.c +++ b/src/radeon_probe.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c,v 1.30 2003/10/07 22:47:12 martin Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c,v 1.27 2003/07/02 17:31:30 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -38,6 +38,7 @@ #include "atimodule.h" #include "ativersion.h" +#include "radeon_pci.h" #include "radeon_probe.h" #include "radeon_version.h" @@ -87,8 +88,8 @@ SymTabRec RADEONChipsets[] = { { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, - { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, - { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, + { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP)" }, + { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP)" }, { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, @@ -100,53 +101,53 @@ SymTabRec RADEONChipsets[] = { { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, + { PCI_CHIP_R200_QI, "ATI Radeon 8500 QI (AGP)" }, + { PCI_CHIP_R200_QJ, "ATI Radeon 8500 QJ (AGP)" }, + { PCI_CHIP_R200_QK, "ATI Radeon 8500 QK (AGP)" }, { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, - { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, - { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, - { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, - { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, - { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, - { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, - { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, - { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, - { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, - { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, - { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, - { PCI_CHIP_RV280_5960, "ATI Radeon 9200PRO 5960 (AGP)" }, + { PCI_CHIP_R200_QN, "ATI Radeon 8500 QN (AGP)" }, + { PCI_CHIP_R200_QO, "ATI Radeon 8500 QO (AGP)" }, + { PCI_CHIP_R200_Qh, "ATI Radeon 8500 Qh (AGP)" }, + { PCI_CHIP_R200_Qi, "ATI Radeon 8500 Qi (AGP)" }, + { PCI_CHIP_R200_Qj, "ATI Radeon 8500 Qj (AGP)" }, + { PCI_CHIP_R200_Qk, "ATI Radeon 8500 Qk (AGP)" }, + { PCI_CHIP_R200_Ql, "ATI Radeon 8500 Ql (AGP)" }, + { PCI_CHIP_R200_BB, "ATI Radeon 8500 BB (AGP)" }, + { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP)" }, + { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP)" }, + { PCI_CHIP_RV250_Id, "ATI Radeon 9000 Id (AGP)" }, + { PCI_CHIP_RV250_Ie, "ATI Radeon 9000 Ie (AGP)" }, + { PCI_CHIP_RV250_If, "ATI Radeon 9000 If (AGP)" }, + { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP)" }, + { PCI_CHIP_RV250_Ld, "ATI Radeon Mobility M9 Ld (AGP)" }, + { PCI_CHIP_RV250_Le, "ATI Radeon Mobility M9 Le (AGP)" }, + { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility M9 Lf (AGP)" }, + { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility M9 Lg (AGP)" }, + { PCI_CHIP_RS300_5834, "ATI Radeon 9000 IGP (A5) 5834" }, + { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9000 IGP (U3) 5835" }, + { PCI_CHIP_RV280_5960, "ATI Radeon 9200 5960 (AGP)" }, { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, - { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, - { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, - { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, + { PCI_CHIP_RV280_5963, "ATI Radeon 9200 5963 (AGP)" }, + { PCI_CHIP_RV280_5968, "ATI Radeon M9+ 5968 (AGP)" }, + { PCI_CHIP_RV280_5969, "ATI Radeon M9+ 5969 (AGP)" }, + { PCI_CHIP_RV280_596A, "ATI Radeon M9+ 596A (AGP)" }, + { PCI_CHIP_RV280_596B, "ATI Radeon M9+ 596B (AGP)" }, { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, - { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, - { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, + { PCI_CHIP_R300_AF, "ATI Radeon 9500 AF (AGP)" }, + { PCI_CHIP_R300_AG, "ATI FireGL Z1/X1 AG (AGP)" }, { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, { PCI_CHIP_R300_NF, "ATI Radeon 9700 NF (AGP)" }, { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, - { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, - { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, - { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, - { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, - { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, - { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600 (M10) NP (AGP)" }, - { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, - { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, - { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, - { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, - { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2 (M11) NV (AGP)" }, - { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, - { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, - { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, - { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, - { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, - { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, - { PCI_CHIP_R350_NK, "ATI FireGL X2 NK (AGP)" }, - { PCI_CHIP_R360_NJ, "ATI Radeon 9800XT NJ (AGP)" }, + { PCI_CHIP_RV350_AR, "ATI Radeon 9600PRO AR (AGP)" }, + { PCI_CHIP_RV350_NP, "ATI Radeon Mobility M10 NP (AGP)" }, + { PCI_CHIP_R350_AK, "ATI FireGL (R350) AK (AGP)" }, + { PCI_CHIP_R350_NH, "ATI Radeon 9800 NH (AGP)" }, + { PCI_CHIP_R350_NK, "ATI FireGL (R350) NL (AGP)" }, { -1, NULL } }; @@ -168,15 +169,27 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, + { PCI_CHIP_R200_QI, PCI_CHIP_R200_QI, RES_SHARED_VGA }, + { PCI_CHIP_R200_QJ, PCI_CHIP_R200_QJ, RES_SHARED_VGA }, + { PCI_CHIP_R200_QK, PCI_CHIP_R200_QK, RES_SHARED_VGA }, { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, + { PCI_CHIP_R200_QN, PCI_CHIP_R200_QN, RES_SHARED_VGA }, + { PCI_CHIP_R200_QO, PCI_CHIP_R200_QO, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qh, PCI_CHIP_R200_Qh, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qi, PCI_CHIP_R200_Qi, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qj, PCI_CHIP_R200_Qj, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qk, PCI_CHIP_R200_Qk, RES_SHARED_VGA }, + { PCI_CHIP_R200_Ql, PCI_CHIP_R200_Ql, RES_SHARED_VGA }, { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, - { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA }, { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Id, PCI_CHIP_RV250_Id, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Ie, PCI_CHIP_RV250_Ie, RES_SHARED_VGA }, { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Le, PCI_CHIP_RV250_Le, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, @@ -184,9 +197,11 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5963, PCI_CHIP_RV280_5963, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5968, PCI_CHIP_RV280_5968, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5969, PCI_CHIP_RV280_5969, RES_SHARED_VGA }, + { PCI_CHIP_RV280_596A, PCI_CHIP_RV280_596A, RES_SHARED_VGA }, + { PCI_CHIP_RV280_596B, PCI_CHIP_RV280_596A, RES_SHARED_VGA }, { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, @@ -196,25 +211,11 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, - { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AR, PCI_CHIP_RV350_AR, RES_SHARED_VGA }, { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, - { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, - { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, - { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, - { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, - { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, { -1, -1, RES_UNDEFINED } }; @@ -337,10 +338,10 @@ RADEONProbe(DriverPtr drv, int flags) pEnt = xf86GetEntityInfo(usedChips[i]); - /* create a RADEONEntity for all chips, even with - old single head Radeon, need to use pRADEONEnt + /* create a RADEONEntity for all chips, even with + old single head Radeon, need to use pRADEONEnt for new monitor detection routines - */ + */ { DevUnion *pPriv; RADEONEntPtr pRADEONEnt; diff --git a/src/radeon_probe.h b/src/radeon_probe.h index af32f25..77d7e86 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h,v 1.13 2003/10/30 17:37:00 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h,v 1.11 2003/07/02 17:31:30 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -60,9 +60,9 @@ typedef struct ScrnInfoPtr pPrimaryScrn; int MonType1; - int MonType2; + int MonType2; xf86MonPtr MonInfo1; - xf86MonPtr MonInfo2; + xf86MonPtr MonInfo2; Bool ReversedDAC; /* TVDAC used as primary dac */ Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */ } RADEONEntRec, *RADEONEntPtr; @@ -100,7 +100,7 @@ extern void RADEONLeaveVT FunctionPrototype((int, int)); extern void RADEONFreeScreen FunctionPrototype((int, int)); -extern ModeStatus RADEONValidMode +extern int RADEONValidMode FunctionPrototype((int, DisplayModePtr, Bool, int)); diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 8af5da5..73b5da1 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.31 2003/11/10 18:41:23 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.28 2003/07/02 17:31:30 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -65,15 +65,7 @@ # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) -#define RADEON_STATUS_PCI_CONFIG 0x06 -# define RADEON_CAP_LIST 0x100000 -#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ -# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ -# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ -# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ -# define RADEON_AGP_ENABLE (1<<8) #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ #define RADEON_AGP_STATUS 0x0f5c /* PCI */ # define RADEON_AGP_1X_MODE 0x01 @@ -241,27 +233,9 @@ #define RADEON_CRC_CMDFIFO_ADDR 0x0740 #define RADEON_CRC_CMDFIFO_DOUT 0x0744 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 -# define RADEON_GRPH_START_REQ_MASK (0x7f) -# define RADEON_GRPH_START_REQ_SHIFT 0 -# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH_STOP_REQ_SHIFT 8 -# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH_BUFFER_SIZE (1<<29) -# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH_STOP_CNTL (1<<31) +# define GRPH_CRITICAL_POINT_MASK (0x7f<<16) #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 -# define RADEON_GRPH2_START_REQ_MASK (0x7f) -# define RADEON_GRPH2_START_REQ_SHIFT 0 -# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH2_STOP_REQ_SHIFT 8 -# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH2_BUFFER_SIZE (1<<29) -# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH2_STOP_CNTL (1<<31) +# define GRPH2_CRITICAL_POINT_MASK (0x7f<<16) #define RADEON_CRTC_CRNT_FRAME 0x0214 #define RADEON_CRTC_EXT_CNTL 0x0054 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) @@ -303,8 +277,7 @@ # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) #define RADEON_CRTC_MORE_CNTL 0x27c -# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) @@ -407,16 +380,11 @@ # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 # define RADEON_DAC_FORCE_DATA_SHIFT 8 -#define RADEON_DAC_MACRO_CNTL 0x0d04 -# define RADEON_DAC_PDWN_R (1 << 16) -# define RADEON_DAC_PDWN_G (1 << 17) -# define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_STD_MASK 0x0300 # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) -# define RADEON_TV_DAC_BGSLEEP (1 << 26) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 @@ -441,7 +409,7 @@ #define RADEON_DEVICE_ID 0x0f02 /* PCI */ #define RADEON_DISP_MISC_CNTL 0x0d00 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) -#define RADEON_DISP_MERGE_CNTL 0x0d60 +#define RADEON_DISP_MERGE_CNTL 0x0d60 # define RADEON_DISP_ALPHA_MODE_MASK 0x03 # define RADEON_DISP_ALPHA_MODE_KEY 0 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 @@ -450,7 +418,7 @@ # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) -#define RADEON_DISP2_MERGE_CNTL 0x0d68 +#define RADEON_DISP2_MERGE_CNTL 0x0d68 # define RADEON_DISP2_RGB_OFFSET_EN (1<<8) #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 @@ -786,12 +754,6 @@ #define RADEON_MEM_ADDR_CONFIG 0x0148 #define RADEON_MEM_BASE 0x0f10 /* PCI */ #define RADEON_MEM_CNTL 0x0140 -# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 -# define RADEON_MEM_USE_B_CH_ONLY (1<<1) -# define RV100_HALF_MODE (1<<3) -# define R300_MEM_NUM_CHANNELS_MASK 0x03 -# define R300_MEM_USE_CD_CH_ONLY (1<<2) -#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ #define RADEON_MEM_INIT_LAT_TIMER 0x0154 #define RADEON_MEM_INTF_CNTL 0x014c #define RADEON_MEM_SDRAM_MODE_REG 0x0158 @@ -804,13 +766,7 @@ #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ -#define R300_MC_IND_INDEX 0x01f8 -# define R300_MC_IND_ADDR_MASK 0x3f -#define R300_MC_IND_DATA 0x01fc -#define R300_MC_READ_CNTL_AB 0x017c -# define R300_MEM_RBS_POSITION_A_MASK 0x03 -#define R300_MC_READ_CNTL_CD_mcind 0x24 -# define R300_MEM_RBS_POSITION_C_MASK 0x03 + #define RADEON_N_VIF_COUNT 0x0248 @@ -1075,8 +1031,6 @@ # define RADEON_SURF_TRANSLATION_DIS (1 << 8) # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) -# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) -# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_INFO 0x0b0c #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 diff --git a/src/radeon_version.h b/src/radeon_version.h index c2a1195..264724d 100644 --- a/src/radeon_version.h +++ b/src/radeon_version.h @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h,v 1.10 2003/09/28 20:15:57 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h,v 1.9 2003/04/06 20:07:34 martin Exp $ */ /* - * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that diff --git a/src/radeon_video.c b/src/radeon_video.c index d551ccc..a7c20fd 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.30 2003/11/10 18:22:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.28 2003/07/02 17:31:30 martin Exp $ */ #include "radeon.h" #include "radeon_macros.h" @@ -53,7 +53,7 @@ typedef struct { int red_intensity; int green_intensity; int blue_intensity; - int ecp_div; + int ecp_div; Bool doubleBuffer; unsigned char currentBuffer; @@ -173,7 +173,7 @@ REF_TRANSFORM trans[2] = /* Gamma curve definition */ -typedef struct +typedef struct { unsigned int gammaReg; unsigned int gammaSlope; @@ -181,7 +181,7 @@ typedef struct } GAMMA_SETTINGS; /* Recommended gamma curve parameters */ -GAMMA_SETTINGS def_gamma[18] = +GAMMA_SETTINGS def_gamma[18] = { {RADEON_OV0_GAMMA_000_00F, 0x100, 0x0000}, {RADEON_OV0_GAMMA_010_01F, 0x100, 0x0020}, @@ -222,10 +222,10 @@ GAMMA_SETTINGS def_gamma[18] = static void RADEONSetTransform (ScrnInfoPtr pScrn, float bright, float cont, - float sat, + float sat, float hue, - float red_intensity, - float green_intensity, + float red_intensity, + float green_intensity, float blue_intensity, CARD32 ref) { @@ -249,7 +249,7 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, CARD32 dwOvGCb, dwOvGCr; CARD32 dwOvBCb, dwOvBCr; - if (ref >= 2) + if (ref >= 2) return; OvHueSin = sin(hue); @@ -287,23 +287,23 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, OvBCr = CAdjBCr; OvROff = RedAdj + CAdjOff - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = GreenAdj + CAdjOff - + OvGOff = GreenAdj + CAdjOff - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = BlueAdj + CAdjOff - + OvBOff = BlueAdj + CAdjOff - OvLuma * Loff - (OvBCb + OvBCr) * Coff; #if 0 /* default constants */ OvROff = -888.5; OvGOff = 545; OvBOff = -1104; -#endif +#endif dwOvROff = ((INT32)(OvROff * 2.0)) & 0x1fff; dwOvGOff = ((INT32)(OvGOff * 2.0)) & 0x1fff; dwOvBOff = ((INT32)(OvBOff * 2.0)) & 0x1fff; /* * Whatever docs say about R200 having 3.8 format instead of 3.11 - * as in Radeon is a lie - * Or more precisely the location of bit fields is a lie + * as in Radeon is a lie + * Or more precisely the location of bit fields is a lie */ if(1 || info->ChipFamily < CHIP_FAMILY_R200) { @@ -390,11 +390,11 @@ RADEONResetVideo(ScrnInfoPtr pScrn) OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); OUTREG(RADEON_CAP0_TRIG_CNTL, 0); RADEONSetColorKey(pScrn, pPriv->colorKey); - + if ((info->ChipFamily == CHIP_FAMILY_R300) || (info->ChipFamily == CHIP_FAMILY_R350) || (info->ChipFamily == CHIP_FAMILY_RV350) || - (info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_R200) || (info->ChipFamily == CHIP_FAMILY_RADEON)) { int i; @@ -462,11 +462,11 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) pPriv->autopaint_colorkey = TRUE; /* - * Unlike older Mach64 chips, RADEON has only two ECP settings: + * Unlike older Mach64 chips, RADEON has only two ECP settings: * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) - * for higher clocks, sure makes life nicer + * for higher clocks, sure makes life nicer */ - if(info->ModeReg.dot_clock_freq < 17500) + if(info->ModeReg.dot_clock_freq < 17500) pPriv->ecp_div = 0; else pPriv->ecp_div = 1; @@ -474,15 +474,15 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) #if 0 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dotclock is %g Mhz, setting ecp_div to %d\n", info->ModeReg.dot_clock_freq/100.0, pPriv->ecp_div); #endif - - OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & + + OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (pPriv->ecp_div << 8)); - if ((info->ChipFamily == CHIP_FAMILY_RS100) || + if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300)) { /* Force the overlay clock on for integrated chips - */ + */ OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) | (1<<18))); } @@ -525,8 +525,8 @@ RADEONSetupImageVideo(ScreenPtr pScreen) adapt->QueryImageAttributes = RADEONQueryImageAttributes; pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr); - REGION_NULL(pScreen, &(pPriv->clip)); - + REGION_INIT(pScreen, &(pPriv->clip), NullBox, 0); + xvBrightness = MAKE_ATOM("XV_BRIGHTNESS"); xvSaturation = MAKE_ATOM("XV_SATURATION"); xvColor = MAKE_ATOM("XV_COLOR"); @@ -540,7 +540,7 @@ RADEONSetupImageVideo(ScreenPtr pScreen) xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY"); xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS"); - + RADEONResetVideo(pScrn); return adapt; @@ -592,11 +592,11 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, #define RTFHue(a) (((a)*3.1416)/1000.0) #define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) - if(attribute == xvAutopaintColorkey) + if(attribute == xvAutopaintColorkey) { pPriv->autopaint_colorkey = ClipValue (value, 0, 1); } - else if(attribute == xvSetDefaults) + else if(attribute == xvSetDefaults) { pPriv->autopaint_colorkey = TRUE; pPriv->brightness = 0; @@ -608,69 +608,69 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, pPriv->blue_intensity = 0; pPriv->doubleBuffer = FALSE; setTransform = TRUE; - } - else if(attribute == xvBrightness) + } + else if(attribute == xvBrightness) { pPriv->brightness = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if((attribute == xvSaturation) || (attribute == xvColor)) + } + else if((attribute == xvSaturation) || (attribute == xvColor)) { pPriv->saturation = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvContrast) + } + else if(attribute == xvContrast) { pPriv->contrast = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvHue) + } + else if(attribute == xvHue) { pPriv->hue = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvRedIntensity) + } + else if(attribute == xvRedIntensity) { pPriv->red_intensity = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvGreenIntensity) + } + else if(attribute == xvGreenIntensity) { pPriv->green_intensity = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvBlueIntensity) + } + else if(attribute == xvBlueIntensity) { pPriv->blue_intensity = ClipValue (value, -1000, 1000); setTransform = TRUE; - } - else if(attribute == xvDoubleBuffer) + } + else if(attribute == xvDoubleBuffer) { pPriv->doubleBuffer = ClipValue (value, 0, 1); pPriv->doubleBuffer = value; - } - else if(attribute == xvColorKey) + } + else if(attribute == xvColorKey) { pPriv->colorKey = value; RADEONSetColorKey (pScrn, pPriv->colorKey); REGION_EMPTY(pScrn->pScreen, &pPriv->clip); - } - else + } + else return BadMatch; if (setTransform) { - RADEONSetTransform(pScrn, - RTFBrightness(pPriv->brightness), - RTFContrast(pPriv->contrast), - RTFSaturation(pPriv->saturation), + RADEONSetTransform(pScrn, + RTFBrightness(pPriv->brightness), + RTFContrast(pPriv->contrast), + RTFSaturation(pPriv->saturation), RTFHue(pPriv->hue), RTFIntensity(pPriv->red_intensity), RTFIntensity(pPriv->green_intensity), RTFIntensity(pPriv->blue_intensity), pPriv->transform_index); } - + return Success; } @@ -705,7 +705,7 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, *value = pPriv->doubleBuffer ? 1 : 0; else if(attribute == xvColorKey) *value = pPriv->colorKey; - else + else return BadMatch; return Success; @@ -857,14 +857,14 @@ RADEONDisplayVideo( CARD32 scaler_src; /* Unlike older Mach64 chips, RADEON has only two ECP settings: 0 for PIXCLK < 175Mhz, and 1 (divide by 2) - for higher clocks, sure makes life nicer - + for higher clocks, sure makes life nicer + Here we need to find ecp_div again, as the user may have switched resolutions */ - if(info->ModeReg.dot_clock_freq < 17500) + if(info->ModeReg.dot_clock_freq < 17500) ecp_div = 0; else ecp_div = 1; - + OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8)); v_inc_shift = 20; @@ -930,7 +930,7 @@ RADEONDisplayVideo( /* Put the hardware overlay on CRTC2: * - * Since one hardware overlay can not be displayed on two heads + * Since one hardware overlay can not be displayed on two heads * at the same time, we might need to consider using software * rendering for the second head. */ @@ -1021,7 +1021,7 @@ RADEONPutImage( RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; INT32 xa, xb, ya, yb; unsigned char *dst_start; - int new_size, offset, s2offset, s3offset; + int pitch, new_size, offset, s2offset, s3offset; int srcPitch, srcPitch2, dstPitch; int top, left, npixels, nlines, bpp; BoxRec dstBox; @@ -1030,7 +1030,7 @@ RADEONPutImage( unsigned char *RADEONMMIO = info->MMIO; CARD32 surface_cntl = INREG(RADEON_SURFACE_CNTL); - OUTREG(RADEON_SURFACE_CNTL, (surface_cntl | + OUTREG(RADEON_SURFACE_CNTL, (surface_cntl | RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); #endif @@ -1074,6 +1074,7 @@ RADEONPutImage( dstBox.y2 -= pScrn->frameY0; bpp = pScrn->bitsPerPixel >> 3; + pitch = bpp * pScrn->displayWidth; switch(id) { case FOURCC_YV12: @@ -1156,7 +1157,7 @@ RADEONPutImage( #endif /* update cliplist */ - if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) + if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); /* draw these */ @@ -1251,16 +1252,16 @@ typedef struct { Bool isOn; } OffscreenPrivRec, * OffscreenPrivPtr; -static int +static int RADEONAllocateSurface( ScrnInfoPtr pScrn, int id, - unsigned short w, + unsigned short w, unsigned short h, XF86SurfacePtr surface ){ FBLinearPtr linear; - int pitch, size, bpp; + int pitch, fbpitch, size, bpp; OffscreenPrivPtr pPriv; if((w > 1024) || (h > 1024)) return BadAlloc; @@ -1268,6 +1269,7 @@ RADEONAllocateSurface( w = (w + 1) & ~1; pitch = ((w << 1) + 15) & ~15; bpp = pScrn->bitsPerPixel >> 3; + fbpitch = bpp * pScrn->displayWidth; size = ((pitch * h) + bpp - 1) / bpp; if(!(linear = RADEONAllocateMemory(pScrn, NULL, size))) @@ -1296,7 +1298,7 @@ RADEONAllocateSurface( pPriv->isOn = FALSE; surface->pScrn = pScrn; - surface->id = id; + surface->id = id; surface->pitches[0] = pitch; surface->offsets[0] = linear->offset * bpp; surface->devPrivate.ptr = (pointer)pPriv; @@ -1304,7 +1306,7 @@ RADEONAllocateSurface( return Success; } -static int +static int RADEONStopSurface( XF86SurfacePtr surface ){ @@ -1320,7 +1322,7 @@ RADEONStopSurface( } -static int +static int RADEONFreeSurface( XF86SurfacePtr surface ){ @@ -1342,8 +1344,8 @@ RADEONGetSurfaceAttribute( Atom attribute, INT32 *value ){ - return RADEONGetPortAttribute(pScrn, attribute, value, - (pointer)(GET_PORT_PRIVATE(pScrn))); + return RADEONGetPortAttribute(pScrn, attribute, value, + (pointer)(GET_PORT_PRIVATE(pScrn))); } static int @@ -1352,17 +1354,17 @@ RADEONSetSurfaceAttribute( Atom attribute, INT32 value ){ - return RADEONSetPortAttribute(pScrn, attribute, value, - (pointer)(GET_PORT_PRIVATE(pScrn))); + return RADEONSetPortAttribute(pScrn, attribute, value, + (pointer)(GET_PORT_PRIVATE(pScrn))); } -static int +static int RADEONDisplaySurface( XF86SurfacePtr surface, - short src_x, short src_y, + short src_x, short src_y, short drw_x, short drw_y, - short src_w, short src_h, + short src_w, short src_h, short drw_w, short drw_h, RegionPtr clipBoxes ){ @@ -1374,7 +1376,7 @@ RADEONDisplaySurface( INT32 xa, ya, xb, yb; BoxRec dstBox; - + if (src_w > (drw_w << 4)) drw_w = src_w >> 4; if (src_h > (drw_h << 4)) @@ -1390,7 +1392,7 @@ RADEONDisplaySurface( dstBox.y1 = drw_y; dstBox.y2 = drw_y + drw_h; - if (!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes, + if (!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes, surface->width, surface->height)) return Success; @@ -1412,7 +1414,7 @@ RADEONDisplaySurface( pPriv->isOn = TRUE; /* we've prempted the XvImage stream so set its free timer */ if (portPriv->videoStatus & CLIENT_VIDEO_ON) { - REGION_EMPTY(pScrn->pScreen, &portPriv->clip); + REGION_EMPTY(pScrn->pScreen, &portPriv->clip); UpdateCurrentTime(); portPriv->videoStatus = FREE_TIMER; portPriv->freeTime = currentTime.milliseconds + FREE_DELAY; @@ -1423,7 +1425,7 @@ RADEONDisplaySurface( } -static void +static void RADEONInitOffscreenImages(ScreenPtr pScreen) { /* ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -1435,7 +1437,7 @@ RADEONInitOffscreenImages(ScreenPtr pScreen) return; offscreenImages[0].image = &Images[0]; - offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES | + offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; offscreenImages[0].alloc_surface = RADEONAllocateSurface; offscreenImages[0].free_surface = RADEONFreeSurface; |