summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--man/radeon.man2
-rw-r--r--src/radeon_accel.c13
-rw-r--r--src/radeon_accelfuncs.c11
-rw-r--r--src/radeon_dri.c8
-rw-r--r--src/radeon_reg.h2
-rw-r--r--src/radeon_render.c30
6 files changed, 31 insertions, 35 deletions
diff --git a/man/radeon.man b/man/radeon.man
index 1a93459..e464f79 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -455,7 +455,7 @@ parameter may be specified as a float value with standard suffixes like
Enable Render acceleration. Does not support component alpha (subpixel)
rendering. Only supported on Radeon series up to and including 9200 (9500/9700
and newer unsupported). The default is
-.B on.
+.B off.
.TP
.BI "Option \*qSubPixelOrder\*q \*q" "string" \*q
Force subpixel order to specified order.
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 43f7d46..0799033 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -314,17 +314,8 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff);
#ifdef RENDER
- /* In the DRI case, it's initialized when the server grabs the lock. We
- * don't hold the lock here, so don't do it in that case.
- */
-#ifdef XF86DRI
- if (!info->directRenderingEnabled) {
-#endif
- if (info->RenderAccel)
- RADEONInit3DEngineForRender(pScrn);
-#ifdef XF86DRI
- }
-#endif
+ if (info->RenderAccel)
+ RADEONInit3DEngineForRender(pScrn);
#endif
RADEONWaitForIdleMMIO(pScrn);
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index 3d69b3f..0fd9fa1 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1349,10 +1349,8 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
#endif
#if defined(RENDER)
-#if defined(XF86DRI)
- if (info->RenderAccel && info->directRenderingEnabled &&
+ if (info->RenderAccel &&
info->xaaReq.minorversion >= 2) {
- /* XXX: The non-CP vertex dispatch doesn't seem to work. */
a->CPUToScreenAlphaTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY;
a->CPUToScreenAlphaTextureFormats = RADEONTextureFormats;
@@ -1388,12 +1386,9 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
a->SubsequentCPUToScreenTexture =
FUNC_NAME(R100SubsequentCPUToScreenTexture);
}
- } else
-#endif /* XF86DRI */
- if (info->RenderAccel)
- {
+ } else if (info->RenderAccel) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration currently "
- "requires the DRI.\n");
+ "requires XAA v1.2 or newer.\n");
}
if (!a->SetupForCPUToScreenAlphaTexture2 && !a->SetupForCPUToScreenTexture2)
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 176adf8..f585ca2 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -345,15 +345,7 @@ static void RADEONEnterServer(ScreenPtr pScreen)
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->accel) info->accel->NeedToSync = TRUE;
-#ifdef RENDER
- if (info->RenderAccel) {
- RADEONSAREAPrivPtr pSAREAPriv;
- RADEONInit3DEngineForRender(pScrn);
- pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
- }
-#endif
}
/* Called when the X server goes to sleep to allow the X server's
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index f2c4d6d..8849cab 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -2064,7 +2064,7 @@
# define RADEON_VF_PRIM_WALK_LIST (2<<4)
# define RADEON_VF_PRIM_WALK_DATA (3<<4)
# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
-# define RADEON_VF_RADEON_MODE (1<<7)
+# define RADEON_VF_RADEON_MODE (1<<8)
# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
# define RADEON_VF_PROG_STREAM_ENA (1<<10)
# define RADEON_VF_INDEX_SIZE_SHIFT 11
diff --git a/src/radeon_render.c b/src/radeon_render.c
index 8b4f5da..073ca66 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -230,7 +230,7 @@ void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn)
#ifdef XF86DRI
RADEONInfoPtr info = RADEONPTR (pScrn);
- if (info->directRenderingEnabled)
+ if (info->CPStarted)
RadeonInit3DEngineCP(pScrn);
else
#endif
@@ -321,8 +321,13 @@ static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
(info->ChipFamily == CHIP_FAMILY_RV280) ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_R200)) {
+
BEGIN_ACCEL(7);
- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
+ if (info->ChipFamily == CHIP_FAMILY_RS300) {
+ OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
+ } else {
+ OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
+ }
OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
@@ -334,7 +339,11 @@ static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
FINISH_ACCEL();
} else {
BEGIN_ACCEL(2);
- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
+ if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
+ (info->ChipFamily == CHIP_FAMILY_RV200))
+ OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
+ else
+ OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_ST0_NONPARAMETRIC |
@@ -423,8 +432,13 @@ static Bool FUNC_NAME(R100SetupTexture)(
/* Upload texture to card. Should use ImageWrite to avoid syncing. */
i = height;
dst = (CARD8*)(info->FB + offset);
- if (info->accel->NeedToSync)
+
+ if (info->accel->NeedToSync) {
info->accel->Sync(pScrn);
+ if (info->CPStarted)
+ RADEONInit3DEngineForRender(pScrn);
+ }
+
while(i--) {
memcpy(dst, src, width * tex_bytepp);
src += src_pitch;
@@ -475,7 +489,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
blend_cntl = RadeonGetBlendCntl(op, dstFormat);
if (blend_cntl == 0)
return FALSE;
-
+
if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
width, height, flags))
return FALSE;
@@ -727,8 +741,12 @@ static Bool FUNC_NAME(R200SetupTexture)(
/* Upload texture to card. Should use ImageWrite to avoid syncing. */
i = height;
dst = (CARD8*)(info->FB + offset);
- if (info->accel->NeedToSync)
+ if (info->accel->NeedToSync) {
info->accel->Sync(pScrn);
+ if (info->CPStarted)
+ RADEONInit3DEngineForRender(pScrn);
+ }
+
while(i--) {
memcpy(dst, src, width * tex_bytepp);
src += src_pitch;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 02:00:39 +0000