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-rw-r--r--man/radeon.man117
-rw-r--r--src/r128.h12
-rw-r--r--src/r128_accel.c9
-rw-r--r--src/r128_dri.c18
-rw-r--r--src/r128_dri.h2
-rw-r--r--src/r128_driver.c251
-rw-r--r--src/r128_sarea.h4
-rw-r--r--src/radeon.h18
-rw-r--r--src/radeon_accel.c16
-rw-r--r--src/radeon_accelfuncs.c8
-rw-r--r--src/radeon_common.h29
-rw-r--r--src/radeon_cursor.c18
-rw-r--r--src/radeon_dri.c34
-rw-r--r--src/radeon_dripriv.h2
-rw-r--r--src/radeon_driver.c527
-rw-r--r--src/radeon_reg.h19
-rw-r--r--src/radeon_video.c143
17 files changed, 706 insertions, 521 deletions
diff --git a/man/radeon.man b/man/radeon.man
index 0a11d53..50f8cfe 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -1,22 +1,22 @@
-.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.0 2003/01/31 23:04:50
+.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.0 2003/01/31 23:04:50 $
.ds q \N'34'
.TH RADEON __drivermansuffix__ __vendorversion__
.SH NAME
radeon \- ATI RADEON video driver
.SH SYNOPSIS
-.nf
+.nf
.B "Section \*qDevice\*q"
.BI " Identifier \*q" devname \*q
.B " Driver \*qradeon\*q"
\ \ ...
.B EndSection
-.fi
+.fi
.SH DESCRIPTION
.B radeon
-is a XFree86 driver for ATI RADEON based video cards. It contains
-full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup,
-flat panel, hardware 2D acceleration, hardware 3D acceleration
-(except R300 series cards), hardware cursor, XV extension, Xinerama extension.
+is a __xservername__ driver for ATI RADEON based video cards. It contains
+full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup,
+flat panel, hardware 2D acceleration, hardware 3D acceleration
+(except R300 and IGP series cards), hardware cursor, XV extension, Xinerama extension.
.SH SUPPORTED HARDWARE
The
.B radeon
@@ -68,53 +68,53 @@ Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 (2D only)
Radeon 9600XT (2d only)
.SH CONFIGURATION DETAILS
-Please refer to XF86Config(__filemansuffix__) for general configuration
+Please refer to __xconfigfile__(__filemansuffix__) for general configuration
details. This section only covers configuration details specific to this
driver.
-.PP
+.PP
The driver auto\-detects all device information necessary to initialize
the card. However, if you have problems with auto\-detection, you can
specify:
-.PP
+.PP
.RS 4
VideoRam \- in kilobytes
-.br
+.br
MemBase \- physical address of the linear framebuffer
-.br
+.br
IOBase \- physical address of the MMIO registers
-.br
+.br
ChipID \- PCI DEVICE ID
.RE
-.PP
+.PP
In addition, the following driver
.B Options
are supported:
-.TP
+.TP
.BI "Option \*qSWcursor\*q \*q" boolean \*q
Selects software cursor. The default is
.B off.
-.TP
+.TP
.BI "Option \*qNoAccel\*q \*q" boolean \*q
-Enables or disables all hardware acceleration.
+Enables or disables all hardware acceleration.
.br
The default is to
.B enable
hardware acceleration.
-.TP
+.TP
.BI "Option \*qDac6Bit\*q \*q" boolean \*q
Enables or disables the use of 6 bits per color component when in 8 bpp
mode (emulates VGA mode). By default, all 8 bits per color component
-are used.
+are used.
.br
The default is
.B off.
-.TP
+.TP
.BI "Option \*qVideoKey\*q \*q" integer \*q
This overrides the default pixel value for the YUV video overlay key.
.br
The default value is
.B 0x1E.
-.TP
+.TP
.BI "Option \*qUseFBDev\*q \*q" boolean \*q
Enable or disable use of an OS\-specific framebuffer device interface
(which is not supported on all OSs). MergedFB does not work when this
@@ -122,7 +122,7 @@ option is in use. See fbdevhw(__drivermansuffix__) for further information.
.br
The default is
.B off.
-.TP
+.TP
.BI "Option \*qAGPMode\*q \*q" integer \*q
Set AGP data transfer rate.
(used only when DRI is enabled)
@@ -134,7 +134,7 @@ Set AGP data transfer rate.
4 \-\- x4
.br
others \-\- invalid
-.TP
+.TP
.BI "Option \*qAGPFastWrite\*q \*q" boolean \*q
Enable AGP fast write.
.br
@@ -142,7 +142,7 @@ Enable AGP fast write.
.br
The default is
.B off.
-.TP
+.TP
.BI "Option \*qBusType\*q \*q" string \*q
Used to replace previous ForcePCIMode option.
Should only be used when driver's bus detection is incorrect
@@ -165,34 +165,34 @@ Force to use the modes queried from the connected monitor.
.br
The default is
.B off.
-.TP
+.TP
.BI "Option \*qDisplayPriority\*q \*q" string \*q
-.br
+.br
Used to prevent flickering or tearing problem caused by display buffer underflow.
-.br
+.br
AUTO \-\- Driver calculated (default).
-.br
+.br
BIOS \-\- Remain unchanged from BIOS setting.
- Use this if the calculation is not correct
+ Use this if the calculation is not correct
for your card.
-.br
-HIGH \-\- Force to the highest priority.
+.br
+HIGH \-\- Force to the highest priority.
Use this if you have problem with above options.
- This may affect performance slightly.
-.br
+ This may affect performence slightly.
+.br
The default value is
.B AUTO.
-.TP
+.TP
.BI "Option \*qMonitorLayout\*q \*q" string \*q
-.br
+.br
This option is used to overwrite the detected monitor types.
This is only required when driver makes a false detection.
The possible monitor types are:
-.br
+.br
NONE \-\- Not connected
-.br
+.br
CRT \-\- Analog CRT monitor
-.br
+.br
TMDS \-\- Desktop flat panel
.br
LVDS \-\- Laptop flat panel
@@ -204,23 +204,23 @@ Option "MonitorLayout" "[type on primary], [type on secondary]"
For example, Option "MonitorLayout" "CRT, TMDS"
Primary/Secondary head for dual\-head cards:
-.br
+.br
(when only one port is used, it will be treated as the primary regardless)
-.br
+.br
.B Primary head:
-.br
+.br
DVI port on DVI+VGA cards
-.br
+.br
LCD output on laptops
.br
Internal TMDS port on DVI+DVI cards
.br
.B Secondary head:
-.br
+.br
VGA port on DVI+VGA cards
-.br
+.br
VGA port on laptops
-.br
+.br
External TMDS port on DVI+DVI cards
The default value is
@@ -348,7 +348,13 @@ For example, Option "MetaModes" "1024x768-1024x768 800x600-1024x768 640x480-800x
.br
The default value is
.B undefined.
-.TP
+.TP
+.BI "Option \*qOverlayOnCRTC2\*q \*q" boolean \*q
+Force hardware overlay to clone head.
+.br
+The default value is
+.B off.
+.TP
.BI "Option \*qNoMergedXinerama\*q \*q" boolean \*q
Since merged framebuffer mode does not use Xinerama, apps are not able to intelligently
place windows. Merged framebuffer mode provides its own pseudo-Xinerama. This allows
@@ -385,7 +391,7 @@ The default value is
.TP
.BI "Option \*qIgnoreEDID\*q \*q" boolean \*q
Do not use EDID data for mode validation, but DDC is still used
-for monitor detection. This is different from NoDDC option.
+for monitor detection. This is different from NoDDC option.
.br
The default value is
.B off.
@@ -408,7 +414,7 @@ Disable panel output.
.br
The default value is
.B off.
-.TP
+.TP
.BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
Enable page flipping for 3D acceleration. This will increase performance
but not work correctly in some rare cases, hence the default is
@@ -418,9 +424,20 @@ but not work correctly in some rare cases, hence the default is
Page flipping does not work well in certain configurations with MergedFB. If you
see rendering errors or other strange behavior, disable page flipping.
+.TP
+.BI "Option \*qForceMinDotClock\*q \*q" frequency \*q
+Override minimum dot clock. Some Radeon BIOSes report a minimum dot
+clock unsuitable (too high) for use with television sets even when they
+actually can produce lower dot clocks. If this is the case you can
+override the value here.
+.B Note that using this option may damage your hardware.
+You have been warned. The
+.B frequency
+parameter may be specified as a float value with standard suffixes like
+"k", "kHz", "M", "MHz".
.SH SEE ALSO
-XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__)
+__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
.SH AUTHORS
-.nf
+.nf
Authors include: ...
diff --git a/src/r128.h b/src/r128.h
index eac70f8..b5c203a 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.24 2002/12/16 16:19:10 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.26 2003/11/06 18:37:58 tsi Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
@@ -172,8 +172,8 @@ typedef struct {
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
- CARD32 min_pll_freq;
- CARD32 max_pll_freq;
+ unsigned min_pll_freq;
+ unsigned max_pll_freq;
CARD16 xclk;
} R128PLLRec, *R128PLLPtr;
@@ -491,7 +491,7 @@ do { \
!info->CCEInUse , __FUNCTION__ ); \
} \
if ( !info->CCEInUse ) { \
- R128CCEWaitForIdle(pScrn); \
+ R128CCEWaitForIdle(pScrn); \
BEGIN_RING( 6 ); \
OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \
OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \
@@ -523,9 +523,9 @@ do { \
xf86DrvMsg( pScrn->scrnIndex, X_INFO, \
"ADVANCE_RING() used: %d+%d=%d/%d\n", \
info->indirectBuffer->used - info->indirectStart, \
- __count * sizeof(CARD32), \
+ __count * (int)sizeof(CARD32), \
info->indirectBuffer->used - info->indirectStart + \
- __count * sizeof(CARD32), \
+ __count * (int)sizeof(CARD32), \
info->indirectBuffer->total - info->indirectStart ); \
} \
info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
diff --git a/src/r128_accel.c b/src/r128_accel.c
index 9887796..90c5cb5 100644
--- a/src/r128_accel.c
+++ b/src/r128_accel.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.16 2002/11/15 03:01:35 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.17 2003/10/03 20:11:11 herrb Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
@@ -82,7 +82,6 @@
/* Driver data structures */
#include "r128.h"
#include "r128_reg.h"
-#include "r128_sarea.h"
#ifdef XF86DRI
#include "r128_sarea.h"
#define _XF86DRI_SERVER_
@@ -1102,7 +1101,7 @@ static void R128CCESetupForSolidFill(ScrnInfoPtr pScrn,
OUT_RING_REG( R128_DP_BRUSH_FRGD_CLR, color );
OUT_RING_REG( R128_DP_WRITE_MASK, planemask );
- OUT_RING_REG( R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT |
+ OUT_RING_REG( R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT |
R128_DST_Y_TOP_TO_BOTTOM));
ADVANCE_RING();
}
@@ -1577,7 +1576,7 @@ drmBufPtr R128CCEGetBuffer( ScrnInfoPtr pScrn )
xf86DrvMsg( pScrn->scrnIndex, X_ERROR,
"GetBuffer timed out, resetting engine...\n");
R128EngineReset( pScrn );
- /* R128EngineRestore( pScrn ); FIXME ??? */
+ /* R128EngineRestore( pScrn ); FIXME ??? */
/* Always restart the engine when doing CCE 2D acceleration */
R128CCE_RESET( pScrn, info );
@@ -1657,7 +1656,7 @@ static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
a->PolyFillRectSolidFlags = 0;
a->SetupForSolidFill = R128CCESetupForSolidFill;
a->SubsequentSolidFillRect = R128CCESubsequentSolidFillRect;
-
+
/* Screen-to-screen Copy */
/* Transparency uses the wrong colors for
24 bpp mode -- the transparent part is
diff --git a/src/r128_dri.c b/src/r128_dri.c
index ef2f9da..4dec476 100644
--- a/src/r128_dri.c
+++ b/src/r128_dri.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.29 2003/07/09 01:45:22 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.31 2003/09/28 20:15:53 alanh Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
@@ -153,7 +153,7 @@ static Bool R128InitVisualConfigs(ScreenPtr pScreen)
pConfigs[i].accumBlueSize = 0;
pConfigs[i].accumAlphaSize = 0;
}
- if (db)
+ if (db)
pConfigs[i].doubleBuffer = TRUE;
else
pConfigs[i].doubleBuffer = FALSE;
@@ -364,9 +364,9 @@ static void R128DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx)
int nbox, nboxSave;
int depth;
- /* FIXME: Use accel when CCE 2D code is written
+ /* FIXME: Use accel when CCE 2D code is written
* EA: What is this code kept for? Radeon doesn't have it and
- * has a comment: "There's no need for the 2d driver to be clearing
+ * has a comment: "There's no need for the 2d driver to be clearing
* buffers for the 3d client. It knows how to do that on its own."
*/
if (info->directRenderingEnabled)
@@ -490,7 +490,7 @@ static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] %d kB allocated with handle 0x%08x\n",
+ "[agp] %d kB allocated with handle 0x%08lx\n",
info->agpSize*1024, info->agpMemHandle);
if (drmAgpBind(info->drmFD, info->agpMemHandle, info->agpOffset) < 0) {
@@ -619,7 +619,7 @@ static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen)
return FALSE;
}
agpBase = drmAgpBase(info->drmFD);
- OUTREG(R128_AGP_BASE, agpBase);
+ OUTREG(R128_AGP_BASE, agpBase);
OUTREG(R128_AGP_CNTL, cntl);
/* Disable Rage 128's PCIGART registers */
@@ -650,7 +650,7 @@ static Bool R128DRIPciInit(R128InfoPtr info, ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] %d kB allocated with handle 0x%08x\n",
+ "[pci] %d kB allocated with handle 0x%08lx\n",
info->agpSize*1024, info->pciMemHandle);
/* Initialize the CCE ring buffer data */
@@ -1183,9 +1183,9 @@ Bool R128DRIScreenInit(ScreenPtr pScreen)
{
void *scratch_ptr;
int scratch_int;
-
+
DRIGetDeviceInfo(pScreen, &info->fbHandle,
- &scratch_int, &scratch_int,
+ &scratch_int, &scratch_int,
&scratch_int, &scratch_int,
&scratch_ptr);
}
diff --git a/src/r128_dri.h b/src/r128_dri.h
index c3ab275..a20ec59 100644
--- a/src/r128_dri.h
+++ b/src/r128_dri.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.h,v 1.7 2002/10/30 12:52:12 alanh Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.h,v 1.6 2001/03/21 17:02:21 dawes Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
diff --git a/src/r128_driver.c b/src/r128_driver.c
index d990610..b90e50f 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.79 2003/08/23 15:02:54 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.88 2004/01/29 02:51:17 dawes Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
@@ -502,7 +502,9 @@ static void R128Unblank(ScrnInfoPtr pScrn)
if(info->isDFP)
OUTREGP(R128_FP_GEN_CNTL, 0, ~R128_FP_BLANK_DIS);
else
- OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS);
+ OUTREGP(R128_CRTC_EXT_CNTL, 0, ~(R128_CRTC_DISPLAY_DIS |
+ R128_CRTC_VSYNC_DIS |
+ R128_CRTC_HSYNC_DIS));
}
/* Compute log base 2 of val. */
@@ -639,7 +641,7 @@ static Bool R128GetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->HasPanelRegs = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Can't determine panel dimensions, and none specified. \
- Disabling programming of FP registers.\n");
+ Disabling programming of FP registers.\n");
}
return TRUE;
@@ -856,7 +858,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
pScrn->memPhysBase = info->LinearAddr;
if (dev->MemBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Linear address override, using 0x%08x instead of 0x%08x\n",
+ "Linear address override, using 0x%08lx instead of 0x%08lx\n",
dev->MemBase,
info->LinearAddr);
info->LinearAddr = dev->MemBase;
@@ -874,7 +876,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
info->MMIOAddr = info->PciInfo->memBase[2] & 0xffffff00;
if (dev->IOBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "MMIO address override, using 0x%08x instead of 0x%08x\n",
+ "MMIO address override, using 0x%08lx instead of 0x%08lx\n",
dev->IOBase,
info->MMIOAddr);
info->MMIOAddr = dev->IOBase;
@@ -891,7 +893,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000;
if (dev->BiosBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS address override, using 0x%08x instead of 0x%08x\n",
+ "BIOS address override, using 0x%08lx instead of 0x%08lx\n",
dev->BiosBase,
info->BIOSAddr);
info->BIOSAddr = dev->BiosBase;
@@ -916,8 +918,8 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
switch (info->Chipset) {
/* R128 Pro and Pro2 can have DFP, we will deal with it.
No support for dual-head/xinerama yet.
- M3 can also have DFP, no support for now */
- case PCI_CHIP_RAGE128TF:
+ M3 can also have DFP, no support for now */
+ case PCI_CHIP_RAGE128TF:
case PCI_CHIP_RAGE128TL:
case PCI_CHIP_RAGE128TR:
/* FIXME: RAGE128 TS/TT/TU are assumed to be PRO2 as all 6 chips came
@@ -925,9 +927,9 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
* This requires confirmation however to be fully correct.
* Mike A. Harris <mharris@redhat.com>
*/
- case PCI_CHIP_RAGE128TS:
+ case PCI_CHIP_RAGE128TS:
case PCI_CHIP_RAGE128TT:
- case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE;
+ case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE;
/* FIXME: RAGE128 P[ABCEGHIJKLMNOQSTUVWX] are assumed to have DFP
* capability, as the comment at the top suggests.
* This requires confirmation however to be fully correct.
@@ -1232,7 +1234,7 @@ R128I2CPutBits(I2CBusPtr b, int Clock, int data)
unsigned long val;
unsigned char *R128MMIO = info->MMIO;
- val = INREG(info->DDCReg)
+ val = INREG(info->DDCReg)
& ~(CARD32)(R128_GPIO_MONID_EN_0 | R128_GPIO_MONID_EN_3);
val |= (Clock ? 0:R128_GPIO_MONID_EN_3);
val |= (data ? 0:R128_GPIO_MONID_EN_0);
@@ -1247,7 +1249,7 @@ R128I2cInit(ScrnInfoPtr pScrn)
if ( xf86LoadSubModule(pScrn, "i2c") )
xf86LoaderReqSymLists(i2cSymbols,NULL);
else{
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to load i2c module\n");
return FALSE;
}
@@ -1278,11 +1280,11 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn)
unsigned char *R128MMIO = info->MMIO;
if(!R128I2cInit(pScrn)){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"I2C initialization failed!\n");
}
- OUTREG(info->DDCReg, (INREG(info->DDCReg)
+ OUTREG(info->DDCReg, (INREG(info->DDCReg)
| R128_GPIO_MONID_MASK_0 | R128_GPIO_MONID_MASK_3));
OUTREG(info->DDCReg, INREG(info->DDCReg)
@@ -1290,7 +1292,7 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn)
MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus);
if(!MonInfo) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No DFP detected\n");
return FALSE;
}
@@ -1308,19 +1310,19 @@ static Bool R128GetDFPInfo(ScrnInfoPtr pScrn)
info->HOverPlus =
ddc->det_mon[i].section.d_timings.h_sync_off;
- info->HSyncWidth =
+ info->HSyncWidth =
ddc->det_mon[i].section.d_timings.h_sync_width;
info->HBlank =
ddc->det_mon[i].section.d_timings.h_blanking;
info->VOverPlus =
ddc->det_mon[i].section.d_timings.v_sync_off;
- info->VSyncWidth =
+ info->VSyncWidth =
ddc->det_mon[i].section.d_timings.v_sync_width;
info->VBlank =
ddc->det_mon[i].section.d_timings.v_blanking;
- }
+ }
}
- return TRUE;
+ return TRUE;
}
@@ -1335,63 +1337,63 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
if(ddc->det_mon[i].type == DS_RANGES)
{
pScrn->monitor->nHsync = 1;
- pScrn->monitor->hsync[0].lo =
+ pScrn->monitor->hsync[0].lo =
ddc->det_mon[i].section.ranges.min_h;
- pScrn->monitor->hsync[0].hi =
+ pScrn->monitor->hsync[0].hi =
ddc->det_mon[i].section.ranges.max_h;
return;
}
}
/*if no sync ranges detected in detailed timing table,
let's try to derive them from supported VESA modes
- Are we doing too much here!!!?
+ Are we doing too much here!!!?
**/
i = 0;
if(ddc->timings1.t1 & 0x02) /*800x600@56*/
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 35.2;
i++;
- }
+ }
if(ddc->timings1.t1 & 0x04) /*640x480@75*/
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 37.5;
i++;
- }
+ }
if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t1 & 0x01))
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 37.9;
i++;
- }
+ }
if(ddc->timings1.t2 & 0x40)
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 46.9;
i++;
}
if((ddc->timings1.t2 & 0x80) || (ddc->timings1.t2 & 0x08))
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 48.1;
i++;
- }
+ }
if(ddc->timings1.t2 & 0x04)
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 56.5;
i++;
- }
+ }
if(ddc->timings1.t2 & 0x02)
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 60.0;
i++;
- }
+ }
if(ddc->timings1.t2 & 0x01)
{
- pScrn->monitor->hsync[i].lo =
+ pScrn->monitor->hsync[i].lo =
pScrn->monitor->hsync[i].hi = 64.0;
i++;
}
@@ -1404,42 +1406,42 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
if(ddc->det_mon[i].type == DS_RANGES)
{
pScrn->monitor->nVrefresh = 1;
- pScrn->monitor->vrefresh[0].lo =
+ pScrn->monitor->vrefresh[0].lo =
ddc->det_mon[i].section.ranges.min_v;
- pScrn->monitor->vrefresh[0].hi =
+ pScrn->monitor->vrefresh[0].hi =
ddc->det_mon[i].section.ranges.max_v;
return;
}
}
i = 0;
if(ddc->timings1.t1 & 0x02) /*800x600@56*/
- {
- pScrn->monitor->vrefresh[i].lo =
+ {
+ pScrn->monitor->vrefresh[i].lo =
pScrn->monitor->vrefresh[i].hi = 56;
i++;
}
if((ddc->timings1.t1 & 0x01) || (ddc->timings1.t2 & 0x08))
- {
- pScrn->monitor->vrefresh[i].lo =
+ {
+ pScrn->monitor->vrefresh[i].lo =
pScrn->monitor->vrefresh[i].hi = 60;
i++;
}
if(ddc->timings1.t2 & 0x04)
- {
- pScrn->monitor->vrefresh[i].lo =
+ {
+ pScrn->monitor->vrefresh[i].lo =
pScrn->monitor->vrefresh[i].hi = 70;
i++;
}
if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t2 & 0x80))
- {
- pScrn->monitor->vrefresh[i].lo =
+ {
+ pScrn->monitor->vrefresh[i].lo =
pScrn->monitor->vrefresh[i].hi = 72;
i++;
}
if((ddc->timings1.t1 & 0x04) || (ddc->timings1.t2 & 0x40)
|| (ddc->timings1.t2 & 0x02) || (ddc->timings1.t2 & 0x01))
- {
- pScrn->monitor->vrefresh[i].lo =
+ {
+ pScrn->monitor->vrefresh[i].lo =
pScrn->monitor->vrefresh[i].hi = 75;
i++;
}
@@ -1447,13 +1449,13 @@ static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
}
}
-/***********
+/***********
xfree's xf86ValidateModes routine deosn't work well with DFPs
- here is our own validation routine. All modes between
- 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted.
- NOTE: RageProII doesn't support rmx, can only work with the
+ here is our own validation routine. All modes between
+ 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted.
+ NOTE: RageProII doesn't support rmx, can only work with the
standard modes the monitor can support (scale).
-************/
+************/
static int R128ValidateFPModes(ScrnInfoPtr pScrn)
{
@@ -1488,15 +1490,15 @@ static int R128ValidateFPModes(ScrnInfoPtr pScrn)
if (sscanf(pScrn->display->modes[i], "%dx%d", &width, &height) == 2)
{
- if(width < 640 || width > info->PanelXRes ||
+ if(width < 640 || width > info->PanelXRes ||
height < 480 || height > info->PanelYRes)
{
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Mode %s is out of range.\n"
"Valid mode should be between 640x480-%dx%d\n",
pScrn->display->modes[i], info->PanelXRes, info->PanelYRes);
continue;
- }
+ }
new = xnfcalloc(1, sizeof(DisplayModeRec));
new->prev = last;
@@ -1526,8 +1528,8 @@ static int R128ValidateFPModes(ScrnInfoPtr pScrn)
}
else
{
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Mode name %s is invalid\n", pScrn->display->modes[i]);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Mode name %s is invalid\n", pScrn->display->modes[i]);
continue;
}
}
@@ -1578,16 +1580,16 @@ static Bool R128PreInitModes(ScrnInfoPtr pScrn)
info->isDFP = FALSE;
info->BIOSDisplay = R128_BIOS_DISPLAY_CRT;
} else if(!info->isPro2) {
- /* RageProII doesn't support rmx, we can't use native-mode
+ /* RageProII doesn't support rmx, we can't use native-mode
stretching for other non-native modes. It will rely on
whatever VESA modes monitor can support. */
modesFound = R128ValidateFPModes(pScrn);
if(modesFound < 1) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No valid mode found for this DFP/LCD\n");
R128UnmapMem(pScrn);
return FALSE;
-
+
}
}
R128UnmapMem(pScrn);
@@ -1639,9 +1641,9 @@ static Bool R128PreInitModes(ScrnInfoPtr pScrn)
LOOKUP_BEST_REFRESH);
if (modesFound < 1 && info->FBDev) {
- fbdevHWUseBuildinMode(pScrn);
- pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8);
- modesFound = 1;
+ fbdevHWUseBuildinMode(pScrn);
+ pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8);
+ modesFound = 1;
}
if (modesFound == -1) return FALSE;
@@ -2402,7 +2404,7 @@ Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
int width, height;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor (scanline %d)\n",
+ "Using hardware cursor (scanline %ld)\n",
info->cursor_start / pScrn->displayWidth);
if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
0, 0, 0)) {
@@ -2874,25 +2876,23 @@ static Bool R128InitCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
int hsync_wid;
int hsync_fudge;
int vsync_wid;
- int bytpp;
int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 };
int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 };
switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; bytpp = 0; break;
- case 8: format = 2; bytpp = 1; break;
- case 15: format = 3; bytpp = 2; break; /* 555 */
- case 16: format = 4; bytpp = 2; break; /* 565 */
- case 24: format = 5; bytpp = 3; break; /* RGB */
- case 32: format = 6; bytpp = 4; break; /* xRGB */
+ case 4: format = 1; break;
+ case 8: format = 2; break;
+ case 15: format = 3; break; /* 555 */
+ case 16: format = 4; break; /* 565 */
+ case 24: format = 5; break; /* RGB */
+ case 32: format = 6; break; /* xRGB */
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Unsupported pixel depth (%d)\n",
info->CurrentLayout.bitsPerPixel);
return FALSE;
}
- R128TRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp));
switch (info->BIOSDisplay) {
case R128_BIOS_DISPLAY_FP:
@@ -3018,7 +3018,7 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
R128_FP_CRTC_DONT_SHADOW_VPAR);
save->fp_panel_cntl = orig->fp_panel_cntl & (CARD32)~R128_FP_DIGON;
save->lvds_gen_cntl = orig->lvds_gen_cntl &
- (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON);
+ (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON);
return;
}
@@ -3036,9 +3036,9 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
R128_HORZ_STRETCH_RESERVED)));
save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN;
save->fp_horz_stretch &= ~R128_AUTO_HORZ_RATIO;
- if (xres == info->PanelXRes)
+ if (xres == info->PanelXRes)
save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE);
- else
+ else
save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE);
save->fp_vert_stretch =
@@ -3047,9 +3047,9 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
(orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE |
R128_VERT_STRETCH_RESERVED)));
save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN;
- if (yres == info->PanelYRes)
+ if (yres == info->PanelYRes)
save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND);
- else
+ else
save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND);
save->fp_gen_cntl = (orig->fp_gen_cntl &
@@ -3058,7 +3058,7 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_USE_SHADOW_EN));
-
+
save->fp_panel_cntl = orig->fp_panel_cntl;
save->lvds_gen_cntl = orig->lvds_gen_cntl;
save->tmds_crc = orig->tmds_crc;
@@ -3068,28 +3068,28 @@ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
want to use the dual CRTC capabilities of the R128 to allow both
the flat panel and external CRT to either simultaneously display
the same image or display two different images. */
-
+
if(!info->isDFP){
if (info->BIOSDisplay == R128_BIOS_DISPLAY_FP_CRT) {
- save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
+ save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
} else {
- save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
- save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
- save->crtc2_gen_cntl = 0;
+ save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
+ save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
+ save->crtc2_gen_cntl = 0;
}
}
/* WARNING: Be careful about turning on the flat panel */
if(info->isDFP){
save->fp_gen_cntl = orig->fp_gen_cntl;
-
+
save->fp_gen_cntl &= ~(R128_FP_CRTC_USE_SHADOW_VEND |
R128_FP_CRTC_USE_SHADOW_ROWCUR |
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_CRT_SYNC_SEL |
R128_FP_USE_SHADOW_EN);
-
+
save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON);
save->fp_gen_cntl |= (R128_FP_FPON | R128_FP_TDMS_EN |
R128_FP_CRTC_DONT_SHADOW_VPAR | R128_FP_CRTC_DONT_SHADOW_HEND);
@@ -3159,7 +3159,7 @@ static void R128InitPLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
/* Define DDA registers for requested video mode. */
static Bool R128InitDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save,
- R128PLLPtr pll, R128InfoPtr info,
+ R128PLLPtr pll, R128InfoPtr info,
DisplayModePtr mode)
{
int DisplayFifoWidth = 128;
@@ -3300,7 +3300,7 @@ static Bool R128Init(ScrnInfoPtr pScrn, DisplayModePtr mode, R128SavePtr save)
if(dot_clock > 0){
R128InitPLLRegisters(pScrn, save, &info->pll, dot_clock);
if (!R128InitDDARegisters(pScrn, save, &info->pll, info, mode))
- return FALSE;
+ return FALSE;
}
else{
save->ppll_ref_div = info->SavedReg.ppll_ref_div;
@@ -3355,8 +3355,8 @@ Bool R128SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
}
/* Used to disallow modes that are not supported by the hardware. */
-int R128ValidMode(int scrnIndex, DisplayModePtr mode,
- Bool verbose, int flag)
+ModeStatus R128ValidMode(int scrnIndex, DisplayModePtr mode,
+ Bool verbose, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
R128InfoPtr info = R128PTR(pScrn);
@@ -3383,46 +3383,47 @@ int R128ValidMode(int scrnIndex, DisplayModePtr mode,
if (mode->CrtcHDisplay == R128_BIOS16(j) &&
mode->CrtcVDisplay == R128_BIOS16(j+2)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Modifying mode according to VBIOS: %ix%i [pclk %.1f MHz] for FP to: ",
- mode->CrtcHDisplay,mode->CrtcVDisplay,
- (float)mode->Clock/1000);
-
- /* Assume we are using expanded mode */
- if (R128_BIOS16(j+5)) j = R128_BIOS16(j+5);
- else j += 9;
-
- mode->Clock = (CARD32)R128_BIOS16(j) * 10;
-
- mode->HDisplay = mode->CrtcHDisplay =
- ((R128_BIOS16(j+10) & 0x01ff)+1)*8;
- mode->HSyncStart = mode->CrtcHSyncStart =
- ((R128_BIOS16(j+12) & 0x01ff)+1)*8;
- mode->HSyncEnd = mode->CrtcHSyncEnd =
- mode->CrtcHSyncStart + (R128_BIOS8(j+14) & 0x1f);
- mode->HTotal = mode->CrtcHTotal =
- ((R128_BIOS16(j+8) & 0x01ff)+1)*8;
-
- mode->VDisplay = mode->CrtcVDisplay =
- (R128_BIOS16(j+17) & 0x07ff)+1;
- mode->VSyncStart = mode->CrtcVSyncStart =
- (R128_BIOS16(j+19) & 0x07ff)+1;
- mode->VSyncEnd = mode->CrtcVSyncEnd =
- mode->CrtcVSyncStart + ((R128_BIOS16(j+19) >> 11) & 0x1f);
- mode->VTotal = mode->CrtcVTotal =
- (R128_BIOS16(j+15) & 0x07ff)+1;
- xf86ErrorF("%ix%i [pclk %.1f MHz]\n",
- mode->CrtcHDisplay,mode->CrtcVDisplay,
- (float)mode->Clock/1000);
-
+ if ((flags & MODECHECK_FINAL) == MODECHECK_FINAL) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Modifying mode according to VBIOS: %ix%i [pclk %.1f MHz] for FP to: ",
+ mode->CrtcHDisplay,mode->CrtcVDisplay,
+ (float)mode->Clock/1000);
+
+ /* Assume we are using expanded mode */
+ if (R128_BIOS16(j+5)) j = R128_BIOS16(j+5);
+ else j += 9;
+
+ mode->Clock = (CARD32)R128_BIOS16(j) * 10;
+
+ mode->HDisplay = mode->CrtcHDisplay =
+ ((R128_BIOS16(j+10) & 0x01ff)+1)*8;
+ mode->HSyncStart = mode->CrtcHSyncStart =
+ ((R128_BIOS16(j+12) & 0x01ff)+1)*8;
+ mode->HSyncEnd = mode->CrtcHSyncEnd =
+ mode->CrtcHSyncStart + (R128_BIOS8(j+14) & 0x1f);
+ mode->HTotal = mode->CrtcHTotal =
+ ((R128_BIOS16(j+8) & 0x01ff)+1)*8;
+
+ mode->VDisplay = mode->CrtcVDisplay =
+ (R128_BIOS16(j+17) & 0x07ff)+1;
+ mode->VSyncStart = mode->CrtcVSyncStart =
+ (R128_BIOS16(j+19) & 0x07ff)+1;
+ mode->VSyncEnd = mode->CrtcVSyncEnd =
+ mode->CrtcVSyncStart + ((R128_BIOS16(j+19) >> 11) & 0x1f);
+ mode->VTotal = mode->CrtcVTotal =
+ (R128_BIOS16(j+15) & 0x07ff)+1;
+ xf86ErrorF("%ix%i [pclk %.1f MHz]\n",
+ mode->CrtcHDisplay,mode->CrtcVDisplay,
+ (float)mode->Clock/1000);
+ }
return MODE_OK;
}
}
- xf86DrvMsgVerb(5,pScrn->scrnIndex, X_INFO,
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 5,
"Mode rejected for FP %ix%i [pclk: %.1f] "
"(not listed in VBIOS)\n",
mode->CrtcHDisplay, mode->CrtcVDisplay,
- mode->Clock / 1000);
+ (float)mode->Clock / 1000);
return MODE_NOMODE;
}
@@ -3666,7 +3667,7 @@ static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on)
lvds_gen_cntl |= R128_LVDS_DISPLAY_DIS;
OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl);
usleep(10);
- lvds_gen_cntl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON
+ lvds_gen_cntl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON
| R128_LVDS_DIGON);
}
diff --git a/src/r128_sarea.h b/src/r128_sarea.h
index 63f432b..b9ad29d 100644
--- a/src/r128_sarea.h
+++ b/src/r128_sarea.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_sarea.h,v 1.7 2002/02/16 21:26:35 herrb Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_sarea.h,v 1.8 2003/09/28 20:15:54 alanh Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
@@ -158,12 +158,10 @@ typedef struct {
unsigned int vertsize;
unsigned int vc_format;
-#ifdef XF86DRI
/* The current cliprects, or a subset thereof.
*/
drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
unsigned int nbox;
-#endif
/* Counters for throttling of rendering clients.
*/
diff --git a/src/radeon.h b/src/radeon.h
index 8b2c8f9..612552f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.42 2003/10/07 22:47:12 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.43 2003/11/06 18:38:00 tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -93,8 +93,8 @@ typedef enum {
#define RADEON_MMIOSIZE 0x80000
#define RADEON_VBIOS_SIZE 0x00010000
-#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
- * Need to comfirm this is not used
+#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
+ * Need to comfirm this is not used
* for something else.
*/
@@ -192,8 +192,8 @@ typedef struct {
int post_div;
/* PLL registers */
- CARD32 ppll_ref_div;
- CARD32 ppll_div_3;
+ unsigned ppll_ref_div;
+ unsigned ppll_div_3;
CARD32 htotal_cntl;
/* Computed values for PLL2 */
@@ -305,14 +305,14 @@ typedef struct {
RADEONDDCType DDCType;
RADEONConnectorType ConnectorType;
Bool HasCRTC2; /* All cards except original Radeon */
- Bool IsMobility; /* Mobile chips for laptops */
- Bool IsIGP; /* IGP chips */
+ Bool IsMobility; /* Mobile chips for laptops */
+ Bool IsIGP; /* IGP chips */
Bool IsSecondary; /* Second Screen */
Bool IsSwitching; /* Flag for switching mode */
Bool OverlayOnCRTC2;
Bool PanelOff; /* Force panel (LCD/DFP) off */
int FPBIOSstart; /* Start of the flat panel info */
- Bool ddc_mode; /* Validate mode by matching exactly
+ Bool ddc_mode; /* Validate mode by matching exactly
* the modes supported in DDC data
*/
Bool R300CGWorkaround;
@@ -722,7 +722,7 @@ do { \
"ADVANCE_RING() start: %d used: %d count: %d\n", \
info->indirectStart, \
info->indirectBuffer->used, \
- __count * sizeof(CARD32)); \
+ __count * (int)sizeof(CARD32)); \
} \
info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
} while (0)
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 0fabcbe..ccf9a39 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.34 2003/07/02 17:31:29 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.36 2003/11/10 18:41:22 tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -296,8 +296,10 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn)
OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN);
#endif
- /* Restore SURFACE_CNTL */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ /* Restore SURFACE_CNTL - only the first head contains valid data -ReneR */
+ if (!info->IsSecondary) {
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ }
RADEONWaitForFifo(pScrn, 1);
OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
@@ -411,7 +413,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.flush = 1;
stop.idle = 1;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
if (ret == 0) {
@@ -421,10 +423,10 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
}
stop.flush = 0;
-
+
i = 0;
do {
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
} while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY);
@@ -491,7 +493,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
buf->used = 0;
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " GetBuffer returning %d %08x\n",
+ " GetBuffer returning %d %p\n",
buf->idx, buf->address);
}
return buf;
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index 2dbd6b2..442c0fd 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.7 2003/04/06 20:07:33 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.7tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -1306,12 +1306,6 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
| HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY);
if (xf86IsEntityShared(info->pEnt->index)) {
- DevUnion *pPriv;
- RADEONEntPtr pRADEONEnt;
-
- pPriv = xf86GetEntityPrivate(info->pEnt->index, gRADEONEntityIndex);
- pRADEONEnt = pPriv->ptr;
-
/* If there are more than one devices sharing this entity, we
* have to assign this call back, otherwise the XAA will be
* disabled
diff --git a/src/radeon_common.h b/src/radeon_common.h
index bf11863..994f5bb 100644
--- a/src/radeon_common.h
+++ b/src/radeon_common.h
@@ -31,7 +31,8 @@
* Converted to common header format:
* Jens Owen <jens@tungstengraphics.com>
*
- * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $
+ * $XdotOrg: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2004/04/23 19:26:46 eich Exp $
+ * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.8tsi Exp $
*
*/
@@ -172,7 +173,7 @@ typedef struct {
#define RADEON_MAX_TEXTURE_UNITS 3
-/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
+/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
*/
typedef struct {
struct {
@@ -235,7 +236,7 @@ typedef struct {
unsigned int pp_border_color;
} texture[RADEON_MAX_TEXTURE_UNITS];
struct {
- unsigned int se_zbias_factor;
+ unsigned int se_zbias_factor;
unsigned int se_zbias_constant;
} zbias;
unsigned int dirty;
@@ -378,23 +379,23 @@ typedef struct {
typedef union {
int i;
- struct {
+ struct {
unsigned char cmd_type, pad0, pad1, pad2;
} header;
- struct {
+ struct {
unsigned char cmd_type, packet_id, pad0, pad1;
} packet;
- struct {
- unsigned char cmd_type, offset, stride, count;
+ struct {
+ unsigned char cmd_type, offset, stride, count;
} scalars;
- struct {
- unsigned char cmd_type, offset, stride, count;
+ struct {
+ unsigned char cmd_type, offset, stride, count;
} vectors;
- struct {
- unsigned char cmd_type, buf_idx, pad0, pad1;
+ struct {
+ unsigned char cmd_type, buf_idx, pad0, pad1;
} dma;
- struct {
- unsigned char cmd_type, flags, pad0, pad1;
+ struct {
+ unsigned char cmd_type, flags, pad0, pad1;
} wait;
} drmRadeonCmdHeader;
@@ -444,7 +445,7 @@ typedef struct drm_radeon_mem_free {
typedef struct drm_radeon_mem_init_heap {
int region;
int size;
- int start;
+ int start;
} drmRadeonMemInitHeap;
/* 1.6: Userspace can request & wait on irq's:
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index fe0d12b..885144b 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -105,16 +105,16 @@ static void RADEONSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
if (info->cursor_argb)
return;
#endif
-
+
fg |= 0xff000000;
bg |= 0xff000000;
-
+
/* Don't recolour the image if we don't have to. */
if (fg == info->cursor_fg && bg == info->cursor_bg)
return;
CURSOR_SWAPPING_START();
-
+
/* Note: We assume that the pixels are either fully opaque or fully
* transparent, so we won't premultiply them, and we can just
* check for non-zero pixel values; those are either fg or bg
@@ -222,7 +222,7 @@ static void RADEONLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image)
*d++ = mono_cursor_color[chunk & 3];
}
CURSOR_SWAPPING_END();
-
+
info->cursor_bg = mono_cursor_color[2];
info->cursor_fg = mono_cursor_color[3];
@@ -299,7 +299,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs)
if (!image)
return; /* XXX can't happen */
-
+
if (!info->IsSecondary) {
save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20);
save1 |= (CARD32) (2 << 20);
@@ -315,7 +315,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs)
#ifdef ARGB_CURSOR
info->cursor_argb = TRUE;
#endif
-
+
CURSOR_SWAPPING_START();
w = pCurs->bits->width;
@@ -350,7 +350,7 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs)
}
#endif
-
+
/* Initialize hardware cursor support. */
Bool RADEONCursorInit(ScreenPtr pScreen)
@@ -371,7 +371,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
cursor->Flags = (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP
| HARDWARE_CURSOR_AND_SOURCE_WITH_MASK
#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* this is a lie --
+ /* this is a lie --
* HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
* actually inverts the bit order, so
* this switches to LSBFIRST
@@ -409,7 +409,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
"Hardware cursor disabled"
" due to insufficient offscreen memory\n");
} else {
- info->cursor_start = RADEON_ALIGN((fbarea->box.x1 +
+ info->cursor_start = RADEON_ALIGN((fbarea->box.x1 +
fbarea->box.y1 * width) *
info->CurrentLayout.pixel_bytes,
256);
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index f0af094..9ecf807 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.36 2003/07/09 01:45:22 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.39 2003/11/06 18:38:00 tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
@@ -516,7 +516,7 @@ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx)
{
/* NOOP. There's no need for the 2d driver to be clearing buffers
- * for the 3d client. It knows how to do that on its own.
+ * for the 3d client. It knows how to do that on its own.
*/
}
@@ -716,8 +716,8 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
{
unsigned char *RADEONMMIO = info->MMIO;
unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */
- unsigned long vendor = drmAgpVendorId(info->drmFD);
- unsigned long device = drmAgpDeviceId(info->drmFD);
+ unsigned int vendor = drmAgpVendorId(info->drmFD);
+ unsigned int device = drmAgpDeviceId(info->drmFD);
mode &= ~RADEON_AGP_MODE_MASK;
switch (info->agpMode) {
@@ -727,7 +727,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
}
if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE;
-
+
if ((vendor == PCI_VENDOR_AMD) &&
(device == PCI_CHIP_AMD761)) {
@@ -794,7 +794,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] %d kB allocated with handle 0x%08x\n",
+ "[agp] %d kB allocated with handle 0x%08lx\n",
info->gartSize*1024, info->agpMemHandle);
if (drmAgpBind(info->drmFD,
@@ -903,7 +903,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] %d kB allocated with handle 0x%08x\n",
+ "[pci] %d kB allocated with handle 0x%08lx\n",
info->gartSize*1024, info->pciMemHandle);
RADEONDRIInitGARTValues(info);
@@ -1075,7 +1075,7 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmHeap.region = RADEON_MEM_REGION_GART;
drmHeap.start = 0;
drmHeap.size = info->gartTexMapSize;
-
+
if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP,
&drmHeap, sizeof(drmHeap))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
@@ -1367,20 +1367,20 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
req_patch = 0;
} else if (info->ChipFamily >= CHIP_FAMILY_R200) {
req_minor = 5;
- req_patch = 0;
+ req_patch = 0;
} else {
#if X_BYTE_ORDER == X_LITTLE_ENDIAN
req_minor = 1;
req_patch = 0;
#else
req_minor = 2;
- req_patch = 1;
+ req_patch = 1;
#endif
}
if (version->version_major != 1 ||
version->version_minor < req_minor ||
- (version->version_minor == req_minor &&
+ (version->version_minor == req_minor &&
version->version_patchlevel < req_patch)) {
/* Incompatible drm version */
xf86DrvMsg(pScreen->myNum, X_ERROR,
@@ -1446,9 +1446,9 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
{
void *scratch_ptr;
int scratch_int;
-
+
DRIGetDeviceInfo(pScreen, &info->fbHandle,
- &scratch_int, &scratch_int,
+ &scratch_int, &scratch_int,
&scratch_int, &scratch_int,
&scratch_ptr);
}
@@ -1591,10 +1591,10 @@ void RADEONDRIResume(ScreenPtr pScreen)
RADEONSetAgpBase(info);
}
- _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
- if (_ret) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CP resume %d\n", __FUNCTION__, _ret);
+ _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
+ if (_ret) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "%s: CP resume %d\n", __FUNCTION__, _ret);
/* FIXME: return? */
}
diff --git a/src/radeon_dripriv.h b/src/radeon_dripriv.h
index 59f5458..34e5dbc 100644
--- a/src/radeon_dripriv.h
+++ b/src/radeon_dripriv.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dripriv.h,v 1.4 2002/10/30 12:52:13 alanh Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dripriv.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index bfc50c4..8818379 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.104 2003/08/23 15:02:54 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.117 2004/02/19 22:38:12 tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -154,7 +154,8 @@ typedef enum {
OPTION_NORADEONXINERAMA,
OPTION_CRT2ISSCRN0,
OPTION_DISP_PRIORITY,
- OPTION_PANEL_SIZE
+ OPTION_PANEL_SIZE,
+ OPTION_MIN_DOTCLOCK
} RADEONOpts;
const OptionInfoRec RADEONOptions[] = {
@@ -192,6 +193,7 @@ const OptionInfoRec RADEONOptions[] = {
{ OPTION_CRT2ISSCRN0, "MergedXineramaCRT2IsScreen0", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE },
+ { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -395,7 +397,7 @@ static struct
{1024, 768, 87},
{832, 624, 75},
{800, 600, 75},
- {800, 600, 72},
+ {800, 600, 72},
{800, 600, 60},
{800, 600, 56},
{640, 480, 75},
@@ -457,7 +459,7 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
- /*
+ /*
* Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
*/
OUTREG(RADEON_MEM_CNTL, 0);
@@ -486,8 +488,8 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
* the saved registers.
*/
CardTmp = INREG(RADEON_MEM_CNTL);
- if (!CardTmp ||
- ((CardTmp & 1) &&
+ if (!CardTmp ||
+ ((CardTmp & 1) &&
(((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) {
/* Restore the saved registers */
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -924,7 +926,7 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT
info->DDCReg = DDCReg;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"DDC Type: %d, Detected Type: %d\n", DDCType, MonType);
return MonType;
@@ -935,7 +937,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- int bConnected = 0;
+ int bConnected = 0;
/* the monitor either wasn't connected or it is a non-DDC CRT.
* try to probe it
@@ -961,7 +963,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
ulData = ulOrigCRTC_EXT_CNTL;
ulData |= RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, ulData);
-
+
ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL);
ulData = ulOrigDAC_EXT_CNTL;
ulData &= ~RADEON_DAC_FORCE_DATA_MASK;
@@ -988,7 +990,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
ulData = INREG(RADEON_DAC_CNTL);
bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0;
-
+
ulData = ulOrigVCLK_ECP_CNTL;
ulMask = 0xFFFFFFFFL;
OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask);
@@ -998,10 +1000,10 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
} else { /* TV DAC */
- /* This doesn't seem to work reliably (maybe worse on some OEM cards),
- for now we always return false. If one wants to connected a
- non-DDC monitor on the DVI port when CRT port is also connected,
- he will need to explicitly tell the driver in the config file
+ /* This doesn't seem to work reliably (maybe worse on some OEM cards),
+ for now we always return false. If one wants to connected a
+ non-DDC monitor on the DVI port when CRT port is also connected,
+ he will need to explicitly tell the driver in the config file
with Option MonitorLayout.
*/
bConnected = FALSE;
@@ -1065,7 +1067,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
ulData = INREG(RADEON_GPIO_MONID);
bConnected = (ulData & RADEON_GPIO_Y_0)?1:0;
if (!bConnected) break;
-
+
usleep(1000);
}
@@ -1091,7 +1093,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
unsigned long ulOrigDAC_CNTL2;
unsigned long ulData;
unsigned long ulMask;
-
+
ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
ulData = ulOrigPIXCLKSDATA;
@@ -1107,10 +1109,10 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
OUTREG(RADEON_TV_MASTER_CNTL, ulData);
ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2);
- ulData = ulOrigDAC_CNTL2;
+ ulData = ulOrigDAC_CNTL2;
ulData &= ~RADEON_DAC2_DAC2_CLK_SEL;
OUTREG(RADEON_DAC_CNTL2, ulData);
-
+
ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL);
ulData = 0x00880213;
@@ -1135,12 +1137,12 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
usleep(1000);
ulData = INREG(RADEON_TV_DAC_CNTL);
- bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0;
+ bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0;
ulData = ulOrigPIXCLKSDATA;
ulMask = 0xFFFFFFFFL;
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask);
-
+
OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL);
OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2);
OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL);
@@ -1148,7 +1150,7 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
}
#endif
}
-
+
return(bConnected ? MT_CRT : MT_NONE);
}
@@ -1167,7 +1169,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
(info->VBIOS[(v) + 1] << 8) | \
(info->VBIOS[(v) + 2] << 16) | \
(info->VBIOS[(v) + 3] << 24))
-
+
pRADEONEnt->MonType1 = MT_NONE;
pRADEONEnt->MonType2 = MT_NONE;
pRADEONEnt->MonInfo1 = NULL;
@@ -1181,16 +1183,16 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
*/
if (xf86GetOptValBool(info->Options, OPTION_IGNORE_EDID, &ignore_edid)) {
if (ignore_edid)
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "IgnoreEDID is specified, EDID data will be ignored\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "IgnoreEDID is specified, EDID data will be ignored\n");
}
- /*
+ /*
* MonitorLayout option takes a string for two monitors connected in following format:
* Option "MonitorLayout" "primary-port-display, secondary-port-display"
- * primary and secondary port displays can have one of following:
- * NONE, CRT, LVDS, TMDS
- * With this option, driver will bring up monitors as specified,
+ * primary and secondary port displays can have one of following:
+ * NONE, CRT, LVDS, TMDS
+ * With this option, driver will bring up monitors as specified,
* not using auto-detection routines to probe monitors.
*/
@@ -1209,7 +1211,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
* CRTC1 -> FP/TMDS -> DVI port -> TMDS panel --> Primary or
* CRTC1 -> FP/LVDS -> Int. LCD -> LVDS panel --> Primary or
* CRTC1 -> TV DAC -> DVI port -> CRT monitor --> Primary
- *
+ *
* Only VGA (can be DVI on some dual-DVI boards) connected:
* CRTC1 -> CRT DAC -> VGA port -> CRT monitor --> Primary or
* CRTC1 -> FP2/Ext. -> DVI port -> TMDS panel --> Primary (not supported)
@@ -1219,19 +1221,19 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
* otherwise, VGA port will be treated as 1st port
*
* Here we always treat DVI port as primary if both ports are connected.
- * When only one port is connected, it will be treated as
- * primary regardless which port or what type of display is involved.
+ * When only one port is connected, it will be treated as
+ * primary regardless which port or what type of display is involved.
*/
if ((s = xf86GetOptValString(info->Options, OPTION_MONITOR_LAYOUT))) {
char s1[5], s2[5];
int i = 0, second = 0;
-
+
/* When using user specified monitor types, we will not do DDC detection
- *
+ *
*/
do {
- switch(*s)
+ switch(*s)
{
case ',':
s1[i] = '\0';
@@ -1262,9 +1264,9 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
pRADEONEnt->MonType1 = MT_DFP;
else if (strcmp(s1, "LVDS") == 0)
pRADEONEnt->MonType1 = MT_LCD;
- else
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Invalid Monitor type specified for 1st port \n");
+ else
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Invalid Monitor type specified for 1st port \n");
if (strcmp(s2, "NONE") == 0)
pRADEONEnt->MonType2 = MT_NONE;
else if (strcmp(s2, "CRT") == 0)
@@ -1273,20 +1275,20 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
pRADEONEnt->MonType2 = MT_DFP;
else if (strcmp(s2, "LVDS") == 0)
pRADEONEnt->MonType2 = MT_LCD;
- else
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Invalid Monitor type specified for 2nd port \n");
+ else
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Invalid Monitor type specified for 2nd port \n");
if (!ignore_edid) {
if (pRADEONEnt->MonType1) /* assuming the first port using DDC_DVI */
- if(!RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)) {
+ if(!RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)) {
RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1);
ddc_crt2_used = TRUE;
- }
+ }
if (pRADEONEnt->MonType2) { /* assuming the second port using DDC_VGA/DDC_CRT2 */
if(!RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2))
if (!ddc_crt2_used)
- RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2);
+ RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2);
}
}
@@ -1296,8 +1298,8 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2;
} else {
pRADEONEnt->MonType1 = MT_CRT;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No valid monitor specified, force to CRT on 1st port\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "No valid monitor specified, force to CRT on 1st port\n");
}
pRADEONEnt->MonType2 = MT_NONE;
pRADEONEnt->MonInfo2 = NULL;
@@ -1344,8 +1346,8 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
* If that's the case, we need also reverse the port arrangement.
* BIOS settings are supposed report this correctly, work fine for all cards tested.
* But there may be some exceptions, in that case, user can reverse their monitor
- * definition in config file to correct the problem.
- */
+ * definition in config file to correct the problem.
+ */
if (info->VBIOS && (tmp = RADEON_BIOS16(info->FPBIOSstart + 0x50))) {
for (i = 1; i < 4; i++) {
unsigned int tmp0;
@@ -1357,7 +1359,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
}
if ((((tmp0 >> 8) & 0x0f) == DDC_DVI ) && ((tmp0 >> 4) & 0x1)) {
pRADEONEnt->ReversedTMDS = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed TMDS detected\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed TMDS detected\n");
}
}
}
@@ -1365,10 +1367,10 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
/* Primary Head (DVI or Laptop Int. panel)*/
/* A ddc capable display connected on DVI port */
if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)));
- else if((pRADEONEnt->MonType1 =
+ else if((pRADEONEnt->MonType1 =
RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1))) {
ddc_crt2_used = TRUE;
- } else if ((info->IsMobility) &&
+ } else if ((info->IsMobility) &&
(info->VBIOS && (INREG(RADEON_BIOS_4_SCRATCH) & 4))) {
/* non-DDC laptop panel connected on primary */
pRADEONEnt->MonType1 = MT_LCD;
@@ -1379,17 +1381,17 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
}
/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
- if((pRADEONEnt->MonType2 =
+ if((pRADEONEnt->MonType2 =
RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2)));
- else if(!ddc_crt2_used)
- pRADEONEnt->MonType2 =
+ else if(!ddc_crt2_used)
+ pRADEONEnt->MonType2 =
RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2);
if (!pRADEONEnt->MonType2)
pRADEONEnt->MonType2 = RADEONCrtIsPhysicallyConnected(pScrn, !pRADEONEnt->ReversedDAC);
if(pRADEONEnt->ReversedTMDS) {
/* always keep internal TMDS as primary head */
- if (pRADEONEnt->MonType1 == MT_DFP ||
+ if (pRADEONEnt->MonType1 == MT_DFP ||
pRADEONEnt->MonType2 == MT_DFP) {
int tmp1 = pRADEONEnt->MonType1;
xf86MonPtr MonInfo = pRADEONEnt->MonInfo1;
@@ -1397,7 +1399,7 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
pRADEONEnt->MonInfo2 = MonInfo;
pRADEONEnt->MonType1 = pRADEONEnt->MonType2;
pRADEONEnt->MonType2 = tmp1;
- if ((pRADEONEnt->MonType1 == MT_CRT) ||
+ if ((pRADEONEnt->MonType1 == MT_CRT) ||
(pRADEONEnt->MonType2 == MT_CRT)) {
pRADEONEnt->ReversedDAC ^= 1;
}
@@ -1420,12 +1422,12 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
}
if(s) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Displays Configured by MonitorLayout: \n\tMonitor1--Type %d, Monitor2--Type %d\n\n",
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Displays Configured by MonitorLayout: \n\tMonitor1--Type %d, Monitor2--Type %d\n\n",
pRADEONEnt->MonType1, pRADEONEnt->MonType2);
} else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Displays Detected: Monitor1--Type %d, Monitor2--Type %d\n\n",
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Displays Detected: Monitor1--Type %d, Monitor2--Type %d\n\n",
pRADEONEnt->MonType1, pRADEONEnt->MonType2);
}
@@ -1446,12 +1448,12 @@ static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pIn
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor2 EDID data --------------------\n");
}
}
-
+
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n");
info->OverlayOnCRTC2 = FALSE;
- if (pRADEONEnt->MonType2 == MT_NONE)
+ if (pRADEONEnt->MonType2 == MT_NONE)
pRADEONEnt->HasSecondary = FALSE;
}
@@ -1461,7 +1463,6 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned long tmp, i;
- unsigned char *RADEONMMIO;
if (!(info->VBIOS = xalloc(RADEON_VBIOS_SIZE))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -1503,29 +1504,29 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- RADEONMMIO = info->MMIO;
/* info->MergedFB = FALSE; */
info->MergeType = MT_NONE;
- if(info->HasCRTC2) {
- if(info->IsSecondary) {
- if(!(info->DisplayType = pRADEONEnt->MonType2)) return FALSE;
+ if(info->HasCRTC2) {
+ if(info->IsSecondary) {
+ info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2;
+ if(info->DisplayType == MT_NONE) return FALSE;
} else {
- info->DisplayType = pRADEONEnt->MonType1;
+ info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1;
if(!pRADEONEnt->HasSecondary) {
if ((info->MergeType = pRADEONEnt->MonType2)) {
/* info->MergedFB = TRUE; */
}
- }
+ }
}
} else {
- info->DisplayType = pRADEONEnt->MonType1;
+ info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s Display == Type %d\n",
- (info->IsSecondary ? "Secondary" : "Primary"),
+ (info->IsSecondary ? "Secondary" : "Primary"),
info->DisplayType);
if (info->MergedFB)
@@ -1563,7 +1564,7 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->PanelYRes = RADEON_BIOS16(tmp+27);
xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n",
info->PanelXRes, info->PanelYRes);
-
+
info->PanelPwrDly = RADEON_BIOS16(tmp+44);
if (info->PanelPwrDly > 2000 || info->PanelPwrDly < 0)
info->PanelPwrDly = 2000;
@@ -1573,7 +1574,7 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->RefDivider = RADEON_BIOS16(tmp+46);
info->PostDivider = RADEON_BIOS8(tmp+48);
info->FeedbackDivider = RADEON_BIOS16(tmp+49);
- if ((info->RefDivider != 0) &&
+ if ((info->RefDivider != 0) &&
(info->FeedbackDivider > 3)) {
info->UseBiosDividers = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -1608,15 +1609,15 @@ static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
DisplayModePtr tmp_mode = NULL;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"No valid timing info from BIOS.\n");
- /* No timing information for the native mode,
+ /* No timing information for the native mode,
use whatever specified in the Modeline.
- If no Modeline specified, we'll just pick
- the VESA mode at 60Hz refresh rate which
+ If no Modeline specified, we'll just pick
+ the VESA mode at 60Hz refresh rate which
is likely to be the best for a flat panel.
- */
+ */
tmp_mode = pScrn->monitor->Modes;
while(tmp_mode) {
- if ((tmp_mode->HDisplay == info->PanelXRes) &&
+ if ((tmp_mode->HDisplay == info->PanelXRes) &&
(tmp_mode->VDisplay == info->PanelYRes)) {
float refresh =
@@ -1673,27 +1674,25 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs;
int i;
- tmp = INREG(RADEON_DEVICE_ID);
-
for(i=0; i<1000000; i++)
if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
break;
-
+
xf86getsecs(&start_secs, &start_usecs);
-
+
for(i=0; i<1000000; i++)
if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
break;
-
+
for(i=0; i<1000000; i++)
if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
break;
-
+
xf86getsecs(&stop_secs, &stop_usecs);
-
+
total_usecs = abs(stop_usecs - start_usecs);
hz = 1000000/total_usecs;
-
+
hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
vclk = (float)(hTotal * (float)(vTotal * hz));
@@ -1717,7 +1716,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
denom = 2*m;
break;
}
-
+
OUTREG(RADEON_CLOCK_CNTL_INDEX, 1);
ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_DATA + 1) & 0x3;
@@ -1726,7 +1725,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
num *= n;
denom *= m;
-
+
switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
case 1:
denom *= 2;
@@ -1741,7 +1740,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
denom *= 3;
break;
case 6:
- denom *= 6;
+ denom *= 6;
break;
case 7:
denom *= 12;
@@ -1800,8 +1799,8 @@ static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn)
return;
}
- /* revision 4 has some problem as it appears in RV280,
- comment it off for new, use default instead */
+ /* revision 4 has some problem as it appears in RV280,
+ comment it off for new, use default instead */
/*
else if (RADEON_BIOS8(tmp) == 4) {
int stride = 0;
@@ -1834,16 +1833,17 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn)
RADEONPLLPtr pll = &info->pll;
CARD16 bios_header;
CARD16 pll_info_block;
+ double min_dotclock;
if (!info->VBIOS) {
pll->min_pll_freq = 12500;
pll->max_pll_freq = 35000;
-
+
if (!RADEONProbePLLParameters(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected, using default PLL parameters!\n");
+ "Video BIOS not detected, using default PLL parameters!\n");
switch (info->Chipset) {
case PCI_CHIP_R200_QL:
@@ -1870,7 +1870,7 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn)
default:
pll->reference_freq = 2700;
pll->reference_div = 67;
- pll->xclk = 16615;
+ pll->xclk = 16615;
break;
}
}
@@ -1887,6 +1887,26 @@ static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn)
pll->xclk = RADEON_BIOS16(pll_info_block + 0x08);
}
+ /* (Some?) Radeon BIOSes seem too lie about their minimum dot
+ * clocks. Allow users to override the detected minimum dot clock
+ * value (e.g., and allow it to be suitable for TV sets).
+ */
+ if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK,
+ OPTUNITS_MHZ, &min_dotclock)) {
+ if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Illegal minimum dotclock specified %.2f MHz "
+ "(option ignored)\n",
+ min_dotclock);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Forced minimum dotclock to %.2f MHz "
+ "(instead of detected %.2f MHz)\n",
+ min_dotclock, ((double)pll->min_pll_freq/1000));
+ pll->min_pll_freq = min_dotclock * 1000;
+ }
+ }
+
return TRUE;
}
@@ -2274,7 +2294,7 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
"BIOS at 0x%08lx\n", info->BIOSAddr);
}
- /* Read registers used to determine options */
+ /* Read registers used to determine options */
from = X_PROBED;
if (info->FBDev)
pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
@@ -2334,6 +2354,67 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
#ifdef XF86DRI
/* AGP/PCI */
+ /* Proper autodetection of an AGP capable device requires examining
+ * PCI config registers to determine if the device implements extended
+ * PCI capabilities, and then walking the capability list as indicated
+ * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP
+ * capability is present. The procedure is outlined as follows:
+ *
+ * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device
+ * to determine wether or not this device implements any extended
+ * capabilities. If this bit is zero, then the device is a PCI 2.1
+ * or earlier device and is not AGP capable, and we can conclude it
+ * to be a PCI device.
+ *
+ * 2) If bit 4 of the status register is set, then the device implements
+ * extended capabilities. There is an 8 bit wide capabilities pointer
+ * register located at offset 0x34 in PCI config space which points to
+ * the first capability in a linked list of extended capabilities that
+ * this device implements. The lower two bits of this register are
+ * reserved and MBZ so must be masked out.
+ *
+ * 3) The extended capabilities list is formed by one or more extended
+ * capabilities structures which are aligned on DWORD boundaries.
+ * The first byte of the structure is the capability ID (CAP_ID)
+ * indicating what extended capability this structure refers to. The
+ * second byte of the structure is an offset from the beginning of
+ * PCI config space pointing to the next capability in the linked
+ * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower
+ * two bits of this pointer are reserved and MBZ. By examining the
+ * CAP_ID of each capability and walking through the list, we will
+ * either find the AGP_CAP_ID (0x02) indicating this device is an
+ * AGP device, or we'll reach the end of the list, indicating it is
+ * a PCI device.
+ *
+ * Mike A. Harris <mharris@redhat.com>
+ *
+ * References:
+ * - PCI Local Bus Specification Revision 2.2, Chapter 6
+ * - AGP Interface Specification Revision 2.0, Section 6.1.5
+ */
+
+ info->IsPCI = TRUE;
+
+ if (pciReadLong(info->PciTag, PCI_CMD_STAT_REG) & RADEON_CAP_LIST) {
+ CARD32 cap_ptr, cap_id;
+
+ cap_ptr = pciReadLong(info->PciTag,
+ RADEON_CAPABILITIES_PTR_PCI_CONFIG)
+ & RADEON_CAP_PTR_MASK;
+
+ while(cap_ptr != RADEON_CAP_ID_NULL) {
+ cap_id = pciReadLong(info->PciTag, cap_ptr);
+ if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
+ info->IsPCI = FALSE;
+ break;
+ }
+ cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
+ }
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n",
+ (info->IsPCI) ? "PCI" : "AGP");
+
if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) {
if (strcmp(s, "AGP") == 0) {
info->IsPCI = FALSE;
@@ -2343,30 +2424,12 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n");
} else if (strcmp(s, "PCIE") == 0) {
info->IsPCI = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "PCI Express not supported yet, use PCI mode\n");
- } else {
- s = NULL;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Invalid BusType option, use detected type\n");
- }
- }
-
- if (!s) {
- CARD32 tmp = pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG);
- /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
- Following detection method works for all cards tested so far.
- Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
- However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
- restarts next time.
- */
- pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, tmp | RADEON_AGP_ENABLE);
- if (pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG) & RADEON_AGP_ENABLE) {
- info->IsPCI = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AGP card detected\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "PCI Express not supported yet, using PCI mode\n");
} else {
- info->IsPCI = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PCI card detected\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Invalid BusType option, using detected type\n");
}
- pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, tmp);
}
#endif
@@ -2530,7 +2593,7 @@ static void RADEONSortModes(DisplayModePtr *new, DisplayModePtr *first,
p = *last;
while (p) {
- if ((((*new)->HDisplay < p->HDisplay) &&
+ if ((((*new)->HDisplay < p->HDisplay) &&
((*new)->VDisplay < p->VDisplay)) ||
(((*new)->HDisplay == p->HDisplay) &&
((*new)->VDisplay == p->VDisplay) &&
@@ -2549,7 +2612,7 @@ static void RADEONSortModes(DisplayModePtr *new, DisplayModePtr *first,
p->prev = *new;
*first = *new;
break;
- }
+ }
p = p->prev;
}
@@ -2575,7 +2638,7 @@ static void RADEONSetPitch (ScrnInfoPtr pScrn)
pScrn->displayWidth = dummy;
}
-/* When no mode provided in config file, this will add all modes supported in
+/* When no mode provided in config file, this will add all modes supported in
* DDC date the pScrn->modes list
*/
static DisplayModePtr RADEONDDCModes(ScrnInfoPtr pScrn)
@@ -2685,7 +2748,7 @@ static DisplayModePtr RADEONDDCModes(ScrnInfoPtr pScrn)
strcpy(new->name, p->name);
new->status = MODE_OK;
new->type = M_T_DEFAULT;
-
+
count++;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -2817,7 +2880,7 @@ static int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
}
}
- /*
+ /*
* Add remaining DDC modes if they're smaller than the user
* specified modes
*/
@@ -2975,7 +3038,7 @@ static int RADEONValidateFPModes(ScrnInfoPtr pScrn, char **ppModeName)
new->HSyncEnd = new->HSyncStart + info->HSyncWidth;
new->VTotal = info->PanelYRes + info->VBlank;
new->VSyncStart = info->PanelYRes + info->VOverPlus;
- new->VSyncEnd = new->VSyncStart + info->VSyncWidth;
+ new->VSyncEnd = new->VSyncStart + info->VSyncWidth;
new->Clock = info->DotClock;
new->Flags |= RADEON_USE_RMX;
@@ -3026,7 +3089,7 @@ static int RADEONValidateFPModes(ScrnInfoPtr pScrn, char **ppModeName)
new->HSyncEnd = new->HSyncStart + info->HSyncWidth;
new->VTotal = info->PanelYRes + info->VBlank;
new->VSyncStart = info->PanelYRes + info->VOverPlus;
- new->VSyncEnd = new->VSyncStart + info->VSyncWidth;
+ new->VSyncEnd = new->VSyncStart + info->VSyncWidth;
new->Clock = info->DotClock;
new->Flags |= RADEON_USE_RMX;
@@ -3366,7 +3429,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->ddc_mode = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Validating modes on %s head ---------\n",
+ "Validating modes on %s head ---------\n",
info->IsSecondary ? "Secondary" : "Primary");
if (info->IsSecondary)
@@ -3511,14 +3574,14 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
* add the flat panel modes
*/
if (info->DisplayType != MT_CRT) {
-
+
/* some panels have DDC, but don't have internal scaler.
* in this case, we need to validate additional modes
* by using on-chip RMX.
*/
int user_modes_asked = 0, user_modes_found = 0, i;
DisplayModePtr tmp_mode = pScrn->modes;
- while (pScrn->display->modes[user_modes_asked]) user_modes_asked++;
+ while (pScrn->display->modes[user_modes_asked]) user_modes_asked++;
if (tmp_mode) {
for (i = 0; i < modesFound; i++) {
if (tmp_mode->type & M_T_USERDEF) user_modes_found++;
@@ -3526,8 +3589,8 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
}
}
- if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) {
- /* when panel size is not valid, try to validate
+ if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) {
+ /* when panel size is not valid, try to validate
* mode using xf86ValidateModes routine
* This can happen when DDC is disabled.
*/
@@ -3549,7 +3612,7 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
LOOKUP_BEST_REFRESH);
else if (!info->IsSecondary)
modesFound = RADEONValidateFPModes(pScrn, pScrn->display->modes);
- }
+ }
}
/* Setup the screen's clockRanges for the VidMode extension */
@@ -3786,7 +3849,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Enabling AGP Fast Write\n");
} else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"AGP Fast Write disabled by default\n");
}
}
@@ -3867,7 +3930,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
* for dedicated 3d rendering boxes
*/
info->noBackBuffer = xf86ReturnOptValBool(info->Options,
- OPTION_NO_BACKBUFFER,
+ OPTION_NO_BACKBUFFER,
FALSE);
if (info->noBackBuffer) {
@@ -3910,7 +3973,6 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
void *int10_save = NULL;
const char *s;
-
RADEONTRACE(("RADEONPreInit\n"));
if (pScrn->numEntities != 1) return FALSE;
@@ -3944,7 +4006,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
"MMIO registers at 0x%08lx\n", info->MMIOAddr);
if(!RADEONMapMMIO(pScrn)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Memory map the MMIO region failed\n");
goto fail1;
}
@@ -3958,7 +4020,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
* going to run it again - so make sure to "fix up" the card
* so that (1) we can read the BIOS ROM and (2) the BIOS will
* get the memory config right.
- */
+ */
RADEONPreInt10Save(pScrn, &int10_save);
#endif
@@ -4097,6 +4159,9 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!info->IsSecondary)
RADEONGetMergedFBOptions(pScrn);
+ if (info->DisplayType == MT_DFP)
+ RADEONGetTMDSInfo(pScrn);
+
if (!RADEONGetPLLParameters(pScrn)) goto fail;
if (!RADEONPreInitGamma(pScrn)) goto fail;
@@ -4121,7 +4186,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (pInt10)
xf86FreeInt10(pInt10);
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
+ if(info->MMIO) RADEONUnmapMMIO(pScrn);
info->MMIO = NULL;
xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
@@ -4149,7 +4214,7 @@ fail:
vgaHWFreeHWRec(pScrn);
fail2:
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
+ if(info->MMIO) RADEONUnmapMMIO(pScrn);
info->MMIO = NULL;
fail1:
RADEONFreeRec(pScrn);
@@ -4256,7 +4321,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
g = colors[idx].green;
b = colors[idx / 2].blue;
OUTPAL(idx * 4, r, g, b);
-
+
/* AH - Added to write extra green data - How come
* this isn't needed on R128? We didn't load the
* extra green data in the other routine.
@@ -4519,7 +4584,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
}
if (info->textureSize < (int)info->FbMapSize / 2) {
- info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
+ info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
}
/* If there's still no space for textures, try without pixmap cache */
if (info->textureSize < 0) {
@@ -4993,11 +5058,11 @@ static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);
OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
- /* old AIW Radeon has some BIOS initialization problem
+ /* old AIW Radeon has some BIOS initialization problem
* with display buffer underflow, only occurs to DFP
- */
+ */
if (!info->HasCRTC2)
- OUTREG(RADEON_GRPH_BUFFER_CNTL,
+ OUTREG(RADEON_GRPH_BUFFER_CNTL,
INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
if (info->DisplayType != MT_DFP) {
@@ -5010,7 +5075,7 @@ static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
*/
if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
+ }
}
tmp = INREG(RADEON_LVDS_GEN_CNTL);
@@ -5097,10 +5162,10 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
unsigned char *RADEONMMIO = info->MMIO;
if (info->IsMobility) {
- /* A temporal workaround for the occational blanking on certain laptop panels.
- This appears to related to the PLL divider registers (fail to lock?).
- It occurs even when all dividers are the same with their old settings.
- In this case we really don't need to fiddle with PLL registers.
+ /* A temporal workaround for the occational blanking on certain laptop panels.
+ This appears to related to the PLL divider registers (fail to lock?).
+ It occurs even when all dividers are the same with their old settings.
+ In this case we really don't need to fiddle with PLL registers.
By doing this we can avoid the blanking problem with some panels.
*/
if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
@@ -5139,7 +5204,7 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
} else {
/* R300 uses ref_div_acc field as real ref divider */
OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
- (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
+ (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
~R300_PPLL_REF_DIV_ACC_MASK);
}
} else {
@@ -5524,12 +5589,12 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONTRACE(("RADEONSaveMode(%p)\n", save));
+ RADEONSaveCommonRegisters(pScrn, save);
if (info->IsSecondary) {
RADEONSaveCrtc2Registers(pScrn, save);
RADEONSavePLL2Registers(pScrn, save);
} else {
RADEONSavePLLRegisters(pScrn, save);
- RADEONSaveCommonRegisters(pScrn, save);
RADEONSaveCrtcRegisters(pScrn, save);
RADEONSaveFPRegisters(pScrn, save);
@@ -5679,6 +5744,7 @@ static void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
}
+
/* Calculate display buffer watermark to prevent buffer underflow */
static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
{
@@ -6008,24 +6074,22 @@ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
int hsync_wid;
int hsync_fudge;
int vsync_wid;
- int bytpp;
int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
int hsync_fudge_fp[] = { 0x02, 0x02, 0x00, 0x00, 0x05, 0x05 };
switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; bytpp = 0; break;
- case 8: format = 2; bytpp = 1; break;
- case 15: format = 3; bytpp = 2; break; /* 555 */
- case 16: format = 4; bytpp = 2; break; /* 565 */
- case 24: format = 5; bytpp = 3; break; /* RGB */
- case 32: format = 6; bytpp = 4; break; /* xRGB */
+ case 4: format = 1; break;
+ case 8: format = 2; break;
+ case 15: format = 3; break; /* 555 */
+ case 16: format = 4; break; /* 565 */
+ case 24: format = 5; break; /* RGB */
+ case 32: format = 6; break; /* xRGB */
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Unsupported pixel depth (%d)\n",
info->CurrentLayout.bitsPerPixel);
return FALSE;
}
- RADEONTRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp));
if ((info->DisplayType == MT_DFP) ||
(info->DisplayType == MT_LCD)) {
@@ -6132,18 +6196,31 @@ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
else
save->crtc_more_cntl = info->SavedReg.crtc_more_cntl;
+ /* Some versions of BIOS setup CRTC_MORE_CNTL for a DFP, if we
+ have a CRT here, it should be cleared to avoild a blank screen.
+ */
+ if (info->DisplayType == MT_CRT)
+ save->crtc_more_cntl = (info->SavedReg.crtc_more_cntl &
+ ~(RADEON_CRTC_H_CUTOFF_ACTIVE_EN |
+ RADEON_CRTC_V_CUTOFF_ACTIVE_EN));
+ else
+ save->crtc_more_cntl = info->SavedReg.crtc_more_cntl;
+
save->surface_cntl = 0;
save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
#if X_BYTE_ORDER == X_BIG_ENDIAN
+ /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
switch (pScrn->bitsPerPixel) {
case 16:
save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
break;
case 32:
save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
break;
}
#endif
@@ -6166,23 +6243,21 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
int hsync_wid;
int hsync_fudge;
int vsync_wid;
- int bytpp;
int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; bytpp = 0; break;
- case 8: format = 2; bytpp = 1; break;
- case 15: format = 3; bytpp = 2; break; /* 555 */
- case 16: format = 4; bytpp = 2; break; /* 565 */
- case 24: format = 5; bytpp = 3; break; /* RGB */
- case 32: format = 6; bytpp = 4; break; /* xRGB */
+ case 4: format = 1; break;
+ case 8: format = 2; break;
+ case 15: format = 3; break; /* 555 */
+ case 16: format = 4; break; /* 565 */
+ case 24: format = 5; break; /* RGB */
+ case 32: format = 6; break; /* xRGB */
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Unsupported pixel depth (%d)\n",
info->CurrentLayout.bitsPerPixel);
return FALSE;
}
- RADEONTRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp));
hsync_fudge = hsync_fudge_default[format-1];
@@ -6212,10 +6287,10 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK |
RADEON_DISP_DAC2_SOURCE_MASK);
if (pRADEONEnt->MonType1 != MT_CRT) {
- save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 |
+ save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 |
RADEON_DISP_DAC2_SOURCE_CRTC2);
} else {
- if (pRADEONEnt->ReversedDAC) {
+ if (pRADEONEnt->ReversedDAC) {
save->disp_output_cntl |= RADEON_DISP_DAC2_SOURCE_CRTC2;
} else {
save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
@@ -6233,7 +6308,7 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
} else {
- if (pRADEONEnt->ReversedDAC) {
+ if (pRADEONEnt->ReversedDAC) {
save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
} else {
@@ -6319,7 +6394,7 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
}
- if (pScrn->rgbBits == 8)
+ if (pScrn->rgbBits == 8)
save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format */
else
save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format */
@@ -6352,8 +6427,8 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
int yres = mode->VDisplay;
float Hratio, Vratio;
- /* If the FP registers have been initialized before for a panel,
- * but the primary port is a CRT, we need to reinitialize
+ /* If the FP registers have been initialized before for a panel,
+ * but the primary port is a CRT, we need to reinitialize
* FP registers in order for CRT to work properly
*/
@@ -6391,7 +6466,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
save->fp_horz_stretch = orig->fp_horz_stretch;
save->fp_horz_stretch &= ~(RADEON_HORZ_STRETCH_BLEND |
- RADEON_HORZ_STRETCH_ENABLE);
+ RADEON_HORZ_STRETCH_ENABLE);
save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
RADEON_HORZ_PANEL_SIZE);
save->fp_horz_stretch |= ((xres/8-1)<<16);
@@ -6446,7 +6521,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
RADEON_FP_CRTC_DONT_SHADOW_HEND );
- if (pScrn->rgbBits == 8)
+ if (pScrn->rgbBits == 8)
save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
else
save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
@@ -6523,7 +6598,7 @@ static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
else /* weird, RV chips got this bit reversed? */
save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
}
}
@@ -6716,6 +6791,7 @@ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode,
info->Flags = mode->Flags;
+ RADEONInitCommonRegisters(save, info);
if (info->IsSecondary) {
if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
return FALSE;
@@ -6738,7 +6814,6 @@ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode,
dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;
RADEONInitPLL2Registers(save, &info->pll, dot_clock);
} else {
- RADEONInitCommonRegisters(save, info);
if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
return FALSE;
dot_clock = mode->Clock/1000.0;
@@ -6877,8 +6952,8 @@ Bool RADEONHandleMessage(int scrnIndex, const char* msgtype,
#endif
/* Used to disallow modes that are not supported by the hardware */
-int RADEONValidMode(int scrnIndex, DisplayModePtr mode,
- Bool verbose, int flag)
+ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode,
+ Bool verbose, int flag)
{
/* There are problems with double scan mode at high clocks
* They're likely related PLL and display buffer settings.
@@ -6922,7 +6997,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, int clone)
#ifdef XF86DRI
if (info->directRenderingEnabled) {
- pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
+ pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
if (clone || info->IsSecondary) {
pSAREAPriv->crtc2_base = Base;
@@ -6987,7 +7062,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONDRIResume(pScrn->pScreen);
}
#endif
- /* this will get XVideo going again, but only if XVideo was initialised
+ /* this will get XVideo going again, but only if XVideo was initialised
during server startup (hence the info->adaptor if). */
if (info->adaptor)
RADEONResetVideo(pScrn);
@@ -7127,12 +7202,79 @@ void RADEONFreeScreen(int scrnIndex, int flags)
RADEONFreeRec(pScrn);
}
+/*
+ * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant).
+ *
+ * Note for current DAC mapping when calling this function:
+ * For most of cards:
+ * single CRT: Driver doesn't change the existing CRTC->DAC mapping,
+ * CRTC1 could be driving either DAC or both DACs.
+ * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC
+ * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC.
+ * Some boards have two DACs reversed or don't even have a primary DAC,
+ * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't
+ * have a second DAC.
+ * It's kind of messy, we'll need to redo DAC mapping part some day.
+ */
+static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (IsPrimaryDAC) {
+ CARD32 dac_cntl;
+ CARD32 dac_macro_cntl = 0;
+ dac_cntl = INREG(RADEON_DAC_CNTL);
+ if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350))
+ dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
+ if (IsOn) {
+ dac_cntl &= ~RADEON_DAC_PDWN;
+ dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
+ RADEON_DAC_PDWN_G |
+ RADEON_DAC_PDWN_B);
+ } else {
+ dac_cntl |= RADEON_DAC_PDWN;
+ dac_macro_cntl |= (RADEON_DAC_PDWN_R |
+ RADEON_DAC_PDWN_G |
+ RADEON_DAC_PDWN_B);
+ }
+ OUTREG(RADEON_DAC_CNTL, dac_cntl);
+ if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350))
+ OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
+ } else {
+ if (info->ChipFamily != CHIP_FAMILY_R200) {
+ CARD32 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
+ if (IsOn) {
+ tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ } else {
+ tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ }
+ OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ } else {
+ CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
+ if (IsOn) {
+ fp2_gen_cntl |= RADEON_FP2_DV0_EN;
+ } else {
+ fp2_gen_cntl &= ~RADEON_FP2_DV0_EN;
+ }
+ OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+ }
+ }
+}
+
/* Sets VESA Display Power Management Signaling (DPMS) Mode */
static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode,
int flags)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
#ifdef XF86DRI
@@ -7151,8 +7293,6 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
RADEON_CRTC2_VSYNC_DIS |
RADEON_CRTC2_HSYNC_DIS);
- /* TODO: additional handling for LCD ? */
-
switch (PowerManagementMode) {
case DPMSModeOn:
/* Screen: On; HSync: On, VSync: On */
@@ -7219,6 +7359,8 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
if (info->ChipFamily >= CHIP_FAMILY_R200) {
OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN);
}
+ } else if (info->DisplayType == MT_CRT) {
+ RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC);
}
} else {
if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
@@ -7229,13 +7371,21 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
}
}
if (info->DisplayType == MT_DFP) {
- OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
+ OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
} else if (info->DisplayType == MT_LCD) {
OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON);
usleep (info->PanelPwrDly * 1000);
OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON);
+ } else if (info->DisplayType == MT_CRT) {
+ if ((pRADEONEnt->HasSecondary) || info->MergedFB) {
+ RADEONDacPowerSet(pScrn, TRUE, pRADEONEnt->ReversedDAC);
+ } else {
+ RADEONDacPowerSet(pScrn, TRUE, TRUE);
+ if (info->HasCRTC2)
+ RADEONDacPowerSet(pScrn, TRUE, FALSE);
+ }
}
}
} else if ((PowerManagementMode == DPMSModeOff) ||
@@ -7248,6 +7398,8 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
if (info->ChipFamily >= CHIP_FAMILY_R200) {
OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN);
}
+ } else if (info->DisplayType == MT_CRT) {
+ RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC);
}
} else {
if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
@@ -7269,12 +7421,23 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
}
- OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
+ OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
~(RADEON_LVDS_BLON | RADEON_LVDS_ON));
if (info->IsMobility || info->IsIGP) {
OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
}
+ } else if (info->DisplayType == MT_CRT) {
+ if ((pRADEONEnt->HasSecondary) || info->MergedFB) {
+ RADEONDacPowerSet(pScrn, FALSE, pRADEONEnt->ReversedDAC);
+ } else {
+ /* single CRT, turning both DACs off, we don't really know
+ * which DAC is actually connected.
+ */
+ RADEONDacPowerSet(pScrn, FALSE, TRUE);
+ if (info->HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */
+ RADEONDacPowerSet(pScrn, FALSE, FALSE);
+ }
}
}
}
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 4bd4d14..4488ec4 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.31 2003/11/10 18:41:23 tsi Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -65,6 +65,12 @@
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
+#define RADEON_STATUS_PCI_CONFIG 0x06
+# define RADEON_CAP_LIST 0x100000
+#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
+# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
+# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
+# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
# define RADEON_AGP_ENABLE (1<<8)
@@ -401,11 +407,16 @@
# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
# define RADEON_DAC_FORCE_DATA_SHIFT 8
+#define RADEON_DAC_MACRO_CNTL 0x0d04
+# define RADEON_DAC_PDWN_R (1 << 16)
+# define RADEON_DAC_PDWN_G (1 << 17)
+# define RADEON_DAC_PDWN_B (1 << 18)
#define RADEON_TV_DAC_CNTL 0x088c
# define RADEON_TV_DAC_STD_MASK 0x0300
# define RADEON_TV_DAC_RDACPD (1 << 24)
# define RADEON_TV_DAC_GDACPD (1 << 25)
# define RADEON_TV_DAC_BDACPD (1 << 26)
+# define RADEON_TV_DAC_BGSLEEP (1 << 26)
#define RADEON_DISP_HW_DEBUG 0x0d14
# define RADEON_CRT2_DISP1_SEL (1 << 5)
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
@@ -430,7 +441,7 @@
#define RADEON_DEVICE_ID 0x0f02 /* PCI */
#define RADEON_DISP_MISC_CNTL 0x0d00
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
-#define RADEON_DISP_MERGE_CNTL 0x0d60
+#define RADEON_DISP_MERGE_CNTL 0x0d60
# define RADEON_DISP_ALPHA_MODE_MASK 0x03
# define RADEON_DISP_ALPHA_MODE_KEY 0
# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
@@ -439,7 +450,7 @@
# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
-#define RADEON_DISP2_MERGE_CNTL 0x0d68
+#define RADEON_DISP2_MERGE_CNTL 0x0d68
# define RADEON_DISP2_RGB_OFFSET_EN (1<<8)
#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
@@ -1064,6 +1075,8 @@
# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
+# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
+# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_INFO 0x0b0c
#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f47e49..7654f10 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.28 2003/07/02 17:31:30 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.30 2003/11/10 18:22:18 tsi Exp $ */
#include "radeon.h"
#include "radeon_macros.h"
@@ -56,7 +56,7 @@ typedef struct {
int red_intensity;
int green_intensity;
int blue_intensity;
- int ecp_div;
+ int ecp_div;
Bool doubleBuffer;
unsigned char currentBuffer;
@@ -179,7 +179,7 @@ REF_TRANSFORM trans[2] =
/* Gamma curve definition */
-typedef struct
+typedef struct
{
unsigned int gammaReg;
unsigned int gammaSlope;
@@ -187,7 +187,7 @@ typedef struct
} GAMMA_SETTINGS;
/* Recommended gamma curve parameters */
-GAMMA_SETTINGS def_gamma[18] =
+GAMMA_SETTINGS def_gamma[18] =
{
{RADEON_OV0_GAMMA_000_00F, 0x100, 0x0000},
{RADEON_OV0_GAMMA_010_01F, 0x100, 0x0020},
@@ -228,10 +228,10 @@ GAMMA_SETTINGS def_gamma[18] =
static void RADEONSetTransform (ScrnInfoPtr pScrn,
float bright,
float cont,
- float sat,
+ float sat,
float hue,
- float red_intensity,
- float green_intensity,
+ float red_intensity,
+ float green_intensity,
float blue_intensity,
CARD32 ref)
{
@@ -255,7 +255,7 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn,
CARD32 dwOvGCb, dwOvGCr;
CARD32 dwOvBCb, dwOvBCr;
- if (ref >= 2)
+ if (ref >= 2)
return;
OvHueSin = sin(hue);
@@ -293,23 +293,23 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn,
OvBCr = CAdjBCr;
OvROff = RedAdj + CAdjOff -
OvLuma * Loff - (OvRCb + OvRCr) * Coff;
- OvGOff = GreenAdj + CAdjOff -
+ OvGOff = GreenAdj + CAdjOff -
OvLuma * Loff - (OvGCb + OvGCr) * Coff;
- OvBOff = BlueAdj + CAdjOff -
+ OvBOff = BlueAdj + CAdjOff -
OvLuma * Loff - (OvBCb + OvBCr) * Coff;
#if 0 /* default constants */
OvROff = -888.5;
OvGOff = 545;
OvBOff = -1104;
-#endif
+#endif
dwOvROff = ((INT32)(OvROff * 2.0)) & 0x1fff;
dwOvGOff = ((INT32)(OvGOff * 2.0)) & 0x1fff;
dwOvBOff = ((INT32)(OvBOff * 2.0)) & 0x1fff;
/*
* Whatever docs say about R200 having 3.8 format instead of 3.11
- * as in Radeon is a lie
- * Or more precisely the location of bit fields is a lie
+ * as in Radeon is a lie
+ * Or more precisely the location of bit fields is a lie
*/
if(1 || info->ChipFamily < CHIP_FAMILY_R200)
{
@@ -396,11 +396,11 @@ RADEONResetVideo(ScrnInfoPtr pScrn)
OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
OUTREG(RADEON_CAP0_TRIG_CNTL, 0);
RADEONSetColorKey(pScrn, pPriv->colorKey);
-
+
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350) ||
(info->ChipFamily == CHIP_FAMILY_RV350) ||
- (info->ChipFamily == CHIP_FAMILY_R200) ||
+ (info->ChipFamily == CHIP_FAMILY_R200) ||
(info->ChipFamily == CHIP_FAMILY_RADEON)) {
int i;
@@ -473,9 +473,9 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
pPriv->crt2 = FALSE;
/*
- * Unlike older Mach64 chips, RADEON has only two ECP settings:
+ * Unlike older Mach64 chips, RADEON has only two ECP settings:
* 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
- * for higher clocks, sure makes life nicer
+ * for higher clocks, sure makes life nicer
*/
/* Figure out which head we are on */
@@ -493,8 +493,8 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
#if 0
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dotclock is %g Mhz, setting ecp_div to %d\n", info->ModeReg.dot_clock_freq/100.0, pPriv->ecp_div);
#endif
-
- OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) &
+
+ OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) &
0xfffffCff) | (pPriv->ecp_div << 8));
/* I suspect we may need a usleep after writing to the PLL. if you play a video too soon
@@ -506,7 +506,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
(info->ChipFamily == CHIP_FAMILY_RS200) ||
(info->ChipFamily == CHIP_FAMILY_RS300)) {
/* Force the overlay clock on for integrated chips
- */
+ */
OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) | (1<<18)));
}
@@ -549,8 +549,8 @@ RADEONSetupImageVideo(ScreenPtr pScreen)
adapt->QueryImageAttributes = RADEONQueryImageAttributes;
pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr);
- REGION_INIT(pScreen, &(pPriv->clip), NullBox, 0);
-
+ REGION_NULL(pScreen, &(pPriv->clip));
+
xvBrightness = MAKE_ATOM("XV_BRIGHTNESS");
xvSaturation = MAKE_ATOM("XV_SATURATION");
xvColor = MAKE_ATOM("XV_COLOR");
@@ -617,11 +617,11 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
#define RTFHue(a) (((a)*3.1416)/1000.0)
#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v))
- if(attribute == xvAutopaintColorkey)
+ if(attribute == xvAutopaintColorkey)
{
pPriv->autopaint_colorkey = ClipValue (value, 0, 1);
}
- else if(attribute == xvSetDefaults)
+ else if(attribute == xvSetDefaults)
{
pPriv->autopaint_colorkey = TRUE;
pPriv->brightness = 0;
@@ -633,48 +633,48 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
pPriv->blue_intensity = 0;
pPriv->doubleBuffer = FALSE;
setTransform = TRUE;
- }
- else if(attribute == xvBrightness)
+ }
+ else if(attribute == xvBrightness)
{
pPriv->brightness = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if((attribute == xvSaturation) || (attribute == xvColor))
+ }
+ else if((attribute == xvSaturation) || (attribute == xvColor))
{
pPriv->saturation = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvContrast)
+ }
+ else if(attribute == xvContrast)
{
pPriv->contrast = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvHue)
+ }
+ else if(attribute == xvHue)
{
pPriv->hue = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvRedIntensity)
+ }
+ else if(attribute == xvRedIntensity)
{
pPriv->red_intensity = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvGreenIntensity)
+ }
+ else if(attribute == xvGreenIntensity)
{
pPriv->green_intensity = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvBlueIntensity)
+ }
+ else if(attribute == xvBlueIntensity)
{
pPriv->blue_intensity = ClipValue (value, -1000, 1000);
setTransform = TRUE;
- }
- else if(attribute == xvDoubleBuffer)
+ }
+ else if(attribute == xvDoubleBuffer)
{
pPriv->doubleBuffer = ClipValue (value, 0, 1);
pPriv->doubleBuffer = value;
- }
- else if(attribute == xvColorKey)
+ }
+ else if(attribute == xvColorKey)
{
pPriv->colorKey = value;
RADEONSetColorKey (pScrn, pPriv->colorKey);
@@ -694,17 +694,17 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
if (setTransform)
{
- RADEONSetTransform(pScrn,
- RTFBrightness(pPriv->brightness),
- RTFContrast(pPriv->contrast),
- RTFSaturation(pPriv->saturation),
+ RADEONSetTransform(pScrn,
+ RTFBrightness(pPriv->brightness),
+ RTFContrast(pPriv->contrast),
+ RTFSaturation(pPriv->saturation),
RTFHue(pPriv->hue),
RTFIntensity(pPriv->red_intensity),
RTFIntensity(pPriv->green_intensity),
RTFIntensity(pPriv->blue_intensity),
pPriv->transform_index);
}
-
+
return Success;
}
@@ -896,10 +896,9 @@ RADEONDisplayVideo(
DisplayModePtr overlay_mode;
/* Unlike older Mach64 chips, RADEON has only two ECP settings: 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
- for higher clocks, sure makes life nicer
-
- Here we need to find ecp_div again, as the user may have switched resolutions */
+ for higher clocks, sure makes life nicer
+ Here we need to find ecp_div again, as the user may have switched resolutions */
/* Figure out which head we are on for dot clock */
if ((info->MergedFB && info->OverlayOnCRTC2) || info->IsSecondary)
@@ -1016,7 +1015,7 @@ RADEONDisplayVideo(
/* Put the hardware overlay on CRTC2:
*
- * Since one hardware overlay can not be displayed on two heads
+ * Since one hardware overlay can not be displayed on two heads
* at the same time, we might need to consider using software
* rendering for the second head.
*/
@@ -1098,7 +1097,7 @@ RADEONPutImage(
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
INT32 xa, xb, ya, yb;
unsigned char *dst_start;
- int pitch, new_size, offset, s2offset, s3offset;
+ int new_size, offset, s2offset, s3offset;
int srcPitch, srcPitch2, dstPitch;
int top, left, npixels, nlines, bpp;
BoxRec dstBox;
@@ -1107,7 +1106,7 @@ RADEONPutImage(
unsigned char *RADEONMMIO = info->MMIO;
CARD32 surface_cntl = INREG(RADEON_SURFACE_CNTL);
- OUTREG(RADEON_SURFACE_CNTL, (surface_cntl |
+ OUTREG(RADEON_SURFACE_CNTL, (surface_cntl |
RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -1161,7 +1160,6 @@ RADEONPutImage(
}
bpp = pScrn->bitsPerPixel >> 3;
- pitch = bpp * pScrn->displayWidth;
switch(id) {
case FOURCC_YV12:
@@ -1244,7 +1242,7 @@ RADEONPutImage(
#endif
/* update cliplist */
- if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes))
+ if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes))
{
REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
/* draw these */
@@ -1339,16 +1337,16 @@ typedef struct {
Bool isOn;
} OffscreenPrivRec, * OffscreenPrivPtr;
-static int
+static int
RADEONAllocateSurface(
ScrnInfoPtr pScrn,
int id,
- unsigned short w,
+ unsigned short w,
unsigned short h,
XF86SurfacePtr surface
){
FBLinearPtr linear;
- int pitch, fbpitch, size, bpp;
+ int pitch, size, bpp;
OffscreenPrivPtr pPriv;
if((w > 1024) || (h > 1024))
return BadAlloc;
@@ -1356,7 +1354,6 @@ RADEONAllocateSurface(
w = (w + 1) & ~1;
pitch = ((w << 1) + 15) & ~15;
bpp = pScrn->bitsPerPixel >> 3;
- fbpitch = bpp * pScrn->displayWidth;
size = ((pitch * h) + bpp - 1) / bpp;
if(!(linear = RADEONAllocateMemory(pScrn, NULL, size)))
@@ -1385,7 +1382,7 @@ RADEONAllocateSurface(
pPriv->isOn = FALSE;
surface->pScrn = pScrn;
- surface->id = id;
+ surface->id = id;
surface->pitches[0] = pitch;
surface->offsets[0] = linear->offset * bpp;
surface->devPrivate.ptr = (pointer)pPriv;
@@ -1393,7 +1390,7 @@ RADEONAllocateSurface(
return Success;
}
-static int
+static int
RADEONStopSurface(
XF86SurfacePtr surface
){
@@ -1409,7 +1406,7 @@ RADEONStopSurface(
}
-static int
+static int
RADEONFreeSurface(
XF86SurfacePtr surface
){
@@ -1431,8 +1428,8 @@ RADEONGetSurfaceAttribute(
Atom attribute,
INT32 *value
){
- return RADEONGetPortAttribute(pScrn, attribute, value,
- (pointer)(GET_PORT_PRIVATE(pScrn)));
+ return RADEONGetPortAttribute(pScrn, attribute, value,
+ (pointer)(GET_PORT_PRIVATE(pScrn)));
}
static int
@@ -1441,17 +1438,17 @@ RADEONSetSurfaceAttribute(
Atom attribute,
INT32 value
){
- return RADEONSetPortAttribute(pScrn, attribute, value,
- (pointer)(GET_PORT_PRIVATE(pScrn)));
+ return RADEONSetPortAttribute(pScrn, attribute, value,
+ (pointer)(GET_PORT_PRIVATE(pScrn)));
}
-static int
+static int
RADEONDisplaySurface(
XF86SurfacePtr surface,
- short src_x, short src_y,
+ short src_x, short src_y,
short drw_x, short drw_y,
- short src_w, short src_h,
+ short src_w, short src_h,
short drw_w, short drw_h,
RegionPtr clipBoxes
){
@@ -1463,7 +1460,7 @@ RADEONDisplaySurface(
INT32 xa, ya, xb, yb;
BoxRec dstBox;
-
+
if (src_w > (drw_w << 4))
drw_w = src_w >> 4;
if (src_h > (drw_h << 4))
@@ -1511,7 +1508,7 @@ RADEONDisplaySurface(
pPriv->isOn = TRUE;
/* we've prempted the XvImage stream so set its free timer */
if (portPriv->videoStatus & CLIENT_VIDEO_ON) {
- REGION_EMPTY(pScrn->pScreen, &portPriv->clip);
+ REGION_EMPTY(pScrn->pScreen, &portPriv->clip);
UpdateCurrentTime();
portPriv->videoStatus = FREE_TIMER;
portPriv->freeTime = currentTime.milliseconds + FREE_DELAY;
@@ -1522,7 +1519,7 @@ RADEONDisplaySurface(
}
-static void
+static void
RADEONInitOffscreenImages(ScreenPtr pScreen)
{
/* ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
@@ -1534,7 +1531,7 @@ RADEONInitOffscreenImages(ScreenPtr pScreen)
return;
offscreenImages[0].image = &Images[0];
- offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES |
+ offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES |
VIDEO_CLIP_TO_VIEWPORT;
offscreenImages[0].alloc_surface = RADEONAllocateSurface;
offscreenImages[0].free_surface = RADEONFreeSurface;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 17:41:46 +0000