diff options
| -rw-r--r-- | src/atombios_crtc.c | 43 | ||||
| -rw-r--r-- | src/radeon.h | 172 | ||||
| -rw-r--r-- | src/radeon_crtc.c | 3 | ||||
| -rw-r--r-- | src/radeon_cursor.c | 24 | ||||
| -rw-r--r-- | src/radeon_driver.c | 494 | ||||
| -rw-r--r-- | src/radeon_reg.h | 418 |
6 files changed, 807 insertions, 347 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 38450bb..34dd65c 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -104,9 +104,7 @@ atombios_crtc_enable(xf86CrtcPtr crtc, int enable) { RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - int scan_enable, cntl; - AtomBiosResult res; + atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable); //TODOavivo_wait_idle(avivo); @@ -465,55 +463,46 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4; switch (crtc->scrn->bitsPerPixel) { case 15: - radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB15; + radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; break; case 16: - radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB16; + radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; break; case 24: case 32: - radeon_crtc->fb_format = AVIVO_CRTC_FORMAT_ARGB32; + radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; break; default: FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); } if (info->tilingEnabled) { - radeon_crtc->fb_format |= AVIVO_CRTC_MACRO_ADDRESS_MODE; + radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; } if (radeon_crtc->crtc_id == 0) - OUTREG(AVIVO_VGA1_CONTROL, 0); + OUTREG(AVIVO_D1VGA_CONTROL, 0); else - OUTREG(AVIVO_VGA2_CONTROL, 0); + OUTREG(AVIVO_D1VGA_CONTROL, 0); /* setup fb format and location */ - OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); + OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay); - OUTREG(AVIVO_CRTC1_FB_LOCATION + radeon_crtc->crtc_offset, fb_location); - OUTREG(AVIVO_CRTC1_FB_END + radeon_crtc->crtc_offset, fb_location); - OUTREG(AVIVO_CRTC1_FB_FORMAT + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, radeon_crtc->fb_format); - OUTREG(AVIVO_CRTC1_X_LENGTH + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->scrn->virtualX); - OUTREG(AVIVO_CRTC1_Y_LENGTH + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->scrn->virtualY); - OUTREG(AVIVO_CRTC1_PITCH + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, crtc->scrn->displayWidth); - /* avivo can only shift offset by 4 pixel in x if you program somethings - * not multiple of 4 you gonna drive the GPU crazy and likely won't - * be able to restore it without cold reboot (vbe post not enough) - */ - x = x & ~3; - OUTREG(AVIVO_CRTC1_OFFSET_END + radeon_crtc->crtc_offset, - ((mode->HDisplay + x -128) << 16) | (mode->VDisplay + y - 128)); - OUTREG(AVIVO_CRTC1_OFFSET_START + radeon_crtc->crtc_offset, (x << 16) | y); - - OUTREG(AVIVO_CRTC1_SCAN_ENABLE + radeon_crtc->crtc_offset, 1); - + OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); } atombios_set_crtc_source(crtc); diff --git a/src/radeon.h b/src/radeon.h index 766c174..7c32693 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -198,6 +198,70 @@ typedef struct { CARD16 rr4_offset; } RADEONBIOSInitTable; +struct avivo_pll_state { + CARD32 ref_div_src; + CARD32 ref_div; + CARD32 fb_div; + CARD32 post_div_src; + CARD32 post_div; + CARD32 ext_ppll_cntl; + CARD32 pll_cntl; + CARD32 int_ss_cntl; +}; + +struct avivo_crtc_state { + CARD32 pll_source; + CARD32 h_total; + CARD32 h_blank_start_end; + CARD32 h_sync_a; + CARD32 h_sync_a_cntl; + CARD32 h_sync_b; + CARD32 h_sync_b_cntl; + CARD32 v_total; + CARD32 v_blank_start_end; + CARD32 v_sync_a; + CARD32 v_sync_a_cntl; + CARD32 v_sync_b; + CARD32 v_sync_b_cntl; + CARD32 control; + CARD32 blank_control; + CARD32 interlace_control; + CARD32 stereo_control; +}; + +struct avivo_grph_state { + CARD32 enable; + CARD32 control; + CARD32 prim_surf_addr; + CARD32 sec_surf_addr; + CARD32 pitch; + CARD32 x_offset; + CARD32 y_offset; + CARD32 x_start; + CARD32 y_start; + CARD32 x_end; + CARD32 y_end; + + CARD32 viewport_start; + CARD32 viewport_size; + CARD32 scl_enable; +}; + +struct avivo_dac_state { + CARD32 enable; + CARD32 source_select; + CARD32 force_output_cntl; + CARD32 powerdown; +}; + +struct avivo_dig_state { + CARD32 cntl; + CARD32 bit_depth_cntl; + CARD32 data_sync; + CARD32 transmitter_enable; + CARD32 transmitter_cntl; +}; + struct avivo_state { CARD32 hdp_fb_location; @@ -208,96 +272,24 @@ struct avivo_state CARD32 vga1_cntl; CARD32 vga2_cntl; - CARD32 pll1_post_div_cntl; - CARD32 pll1_post_div; - CARD32 pll1_post_div_mystery; - CARD32 pll1_post_mul; - CARD32 pll1_divider_cntl; - CARD32 pll1_divider; - CARD32 pll1_mystery0; - CARD32 pll1_mystery1; - - CARD32 pll2_post_div_cntl; - CARD32 pll2_post_div; - CARD32 pll2_post_div_mystery; - CARD32 pll2_post_mul; - CARD32 pll2_divider_cntl; - CARD32 pll2_divider; - CARD32 pll2_mystery0; - CARD32 pll2_mystery1; - - CARD32 crtc_pll_source; - CARD32 crtc1_h_total; - CARD32 crtc1_h_blank; - CARD32 crtc1_h_sync_wid; - CARD32 crtc1_h_sync_pol; - CARD32 crtc1_v_total; - CARD32 crtc1_v_blank; - CARD32 crtc1_v_sync_wid; - CARD32 crtc1_v_sync_pol; - CARD32 crtc1_cntl; - CARD32 crtc1_blank_status; - CARD32 crtc1_stereo_status; - CARD32 crtc1_scan_enable; - CARD32 crtc1_fb_format; - CARD32 crtc1_fb_location; - CARD32 crtc1_fb_end; - CARD32 crtc1_pitch; - CARD32 crtc1_x_length; - CARD32 crtc1_y_length; - CARD32 crtc1_fb_height; - CARD32 crtc1_offset_start; - CARD32 crtc1_offset_end; - CARD32 crtc1_expn_size; - CARD32 crtc1_expn_cntl; - CARD32 crtc1_6594; - CARD32 crtc1_659c; - CARD32 crtc1_65a4; - CARD32 crtc1_65a8; - CARD32 crtc1_65ac; - CARD32 crtc1_65b0; - CARD32 crtc1_65b8; - CARD32 crtc1_65bc; - CARD32 crtc1_65c0; - CARD32 crtc1_65c8; - - CARD32 crtc2_h_total; - CARD32 crtc2_h_blank; - CARD32 crtc2_h_sync_wid; - CARD32 crtc2_h_sync_pol; - CARD32 crtc2_v_total; - CARD32 crtc2_v_blank; - CARD32 crtc2_v_sync_wid; - CARD32 crtc2_v_sync_pol; - CARD32 crtc2_cntl; - CARD32 crtc2_blank_status; - CARD32 crtc2_scan_enable; - CARD32 crtc2_fb_format; - CARD32 crtc2_fb_location; - CARD32 crtc2_fb_end; - CARD32 crtc2_pitch; - CARD32 crtc2_x_length; - CARD32 crtc2_y_length; - - CARD32 dac1_cntl; - CARD32 dac1_force_output_cntl; - CARD32 dac1_powerdown; - - CARD32 tmds1_cntl; - CARD32 tmds1_bit_depth_cntl; - CARD32 tmds1_data_sync; - CARD32 tmds1_transmitter_enable; - CARD32 tmds1_transmitter_cntl; - - CARD32 dac2_cntl; - CARD32 dac2_force_output_cntl; - CARD32 dac2_powerdown; - - CARD32 tmds2_cntl; - CARD32 tmds2_bit_depth_cntl; - CARD32 tmds2_data_sync; - CARD32 tmds2_transmitter_enable; - CARD32 tmds2_transmitter_cntl; + CARD32 crtc_master_en; + CARD32 crtc_tv_control; + + struct avivo_pll_state pll1; + struct avivo_pll_state pll2; + + struct avivo_crtc_state crtc1; + struct avivo_crtc_state crtc2; + + struct avivo_grph_state grph1; + struct avivo_grph_state grph2; + + struct avivo_dac_state daca; + struct avivo_dac_state dacb; + + struct avivo_dig_state tmds1; + struct avivo_dig_state tmds2; + }; typedef struct { diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 64f8037..9192a9e 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -1280,7 +1280,8 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; pRADEONEnt->Controller[1]->crtc_id = 1; - pRADEONEnt->Controller[1]->crtc_offset = AVIVO_CRTC2_H_TOTAL - AVIVO_CRTC1_H_TOTAL; + pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; + return TRUE; } diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index d46c098..948ecd4 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -96,15 +96,15 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) RADEONInfoPtr info = RADEONPTR(crtc->scrn); unsigned char *RADEONMMIO = info->MMIO; - OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset, 0); + OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0); if (enable) { - OUTREG(AVIVO_CURSOR1_LOCATION + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, info->fbLocation + info->cursor_offset); - OUTREG(AVIVO_CURSOR1_SIZE + radeon_crtc->crtc_offset, + OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((info->cursor_width -1) << 16) | (info->cursor_height-1)); - OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset, - AVIVO_CURSOR_EN | (AVIVO_CURSOR_FORMAT_ARGB << AVIVO_CURSOR_FORMAT_SHIFT)); + OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, + AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); } } @@ -124,9 +124,9 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc) RADEON_SYNC(info, pScrn); if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset, - INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset) - | AVIVO_CURSOR_EN); + OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, + INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) + | AVIVO_D1CURSOR_EN); avivo_setup_cursor(crtc, TRUE); } else { if (crtc_id == 0) @@ -158,9 +158,9 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc) RADEON_SYNC(info, pScrn); if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_CURSOR1_CNTL+ radeon_crtc->crtc_offset, - INREG(AVIVO_CURSOR1_CNTL + radeon_crtc->crtc_offset) - & ~(AVIVO_CURSOR_EN)); + OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset, + INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) + & ~(AVIVO_D1CURSOR_EN)); avivo_setup_cursor(crtc, FALSE); } else { if (crtc_id == 0) @@ -202,7 +202,7 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) if (y < 0) y = 0; - OUTREG(AVIVO_CURSOR1_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); + OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); radeon_crtc->cursor_x = x; radeon_crtc->cursor_y = y; } else { diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 02e38bd..cabc539 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1273,13 +1273,11 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) if (IS_AVIVO_VARIANT) { if (info->ChipFamily == CHIP_FAMILY_RV515) { - info->mc_fb_location = INMC(pScrn, MC01); - ErrorF("mc fb is %08X\n", info->mc_fb_location); - info->mc_agp_location = INMC(pScrn, MC02); + info->mc_fb_location = INMC(pScrn, RV515_MC_FB_LOCATION); + info->mc_agp_location = INMC(pScrn, RV515_MC_AGP_LOCATION); } else { - info->mc_fb_location = INMC(pScrn, AVIVO_MC_MEMORY_MAP); - ErrorF("mc fb is %08X\n", info->mc_fb_location); - info->mc_agp_location = INMC(pScrn, MC05); + info->mc_fb_location = INMC(pScrn, R520_MC_FB_LOCATION); + info->mc_agp_location = INMC(pScrn, R520_MC_AGP_LOCATION); } } else { /* Default to existing values */ @@ -3922,17 +3920,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, if (IS_AVIVO_VARIANT) { CARD32 mc_fb_loc, mc_agp_loc; if (info->ChipFamily == CHIP_FAMILY_RV515) { - mc_fb_loc = INMC(pScrn, MC01); - ErrorF("%s: save mc is %08x\n", __func__, mc_fb_loc); - mc_agp_loc = INMC(pScrn, MC02); + mc_fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); + mc_agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); } else { - mc_fb_loc = INMC(pScrn, AVIVO_MC_MEMORY_MAP); - mc_agp_loc = INMC(pScrn, MC05); + mc_fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); + mc_agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); } #if 1 /* disable VGA CTRL */ - OUTREG(AVIVO_D1VGA_CTRL, INREG(AVIVO_D1VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE); - OUTREG(AVIVO_D2VGA_CTRL, INREG(AVIVO_D2VGA_CTRL) & ~AVIVO_DVGA_MODE_ENABLE); + OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); + OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); #endif if (mc_fb_loc != info->mc_fb_location || mc_agp_loc != info->mc_agp_location) { @@ -3941,14 +3938,13 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONWaitForIdleMMIO(pScrn); /* Stop display & memory access */ - tmp = INREG(AVIVO_CRTC1_CNTL); - OUTREG(AVIVO_CRTC1_CNTL, tmp & ~AVIVO_CRTC_EN); + tmp = INREG(AVIVO_D1CRTC_CONTROL); + OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); - tmp = INREG(AVIVO_CRTC2_CNTL); - tmp &= ~AVIVO_CRTC_EN; - OUTREG(AVIVO_CRTC2_CNTL, tmp); + tmp = INREG(AVIVO_D2CRTC_CONTROL); + OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); - tmp = INREG(AVIVO_CRTC2_CNTL); + tmp = INREG(AVIVO_D2CRTC_CONTROL); usleep(10000); timeout = 0; @@ -3969,13 +3965,13 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, } if (info->ChipFamily == CHIP_FAMILY_RV515) { - OUTMC(pScrn, MC01, info->mc_fb_location); - OUTMC(pScrn, MC02, 0x003f0000); - (void)INMC(pScrn, MC02); + OUTMC(pScrn, RV515_MC_FB_LOCATION, info->mc_fb_location); + OUTMC(pScrn, RV515_MC_AGP_LOCATION, 0x003f0000); + (void)INMC(pScrn, RV515_MC_AGP_LOCATION); } else { - OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, info->mc_fb_location); - OUTMC(pScrn, MC05, 0x003f0000); - (void)INMC(pScrn, AVIVO_MC_MEMORY_MAP); + OUTMC(pScrn, R520_MC_FB_LOCATION, info->mc_fb_location); + OUTMC(pScrn, R520_MC_AGP_LOCATION, 0x003f0000); + (void)INMC(pScrn, R520_MC_FB_LOCATION); } OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); @@ -4132,11 +4128,11 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) if (IS_AVIVO_VARIANT) { if (info->ChipFamily == CHIP_FAMILY_RV515) { - fb = INMC(pScrn, MC01); - agp = INMC(pScrn, MC02); + fb = INMC(pScrn, RV515_MC_FB_LOCATION); + agp = INMC(pScrn, RV515_MC_AGP_LOCATION); } else { - fb = INMC(pScrn, AVIVO_MC_MEMORY_MAP); - agp = INMC(pScrn, MC05); + fb = INMC(pScrn, R520_MC_FB_LOCATION); + agp = INMC(pScrn, RV515_MC_AGP_LOCATION); } fb_loc_changed = (fb != info->mc_fb_location); @@ -5524,101 +5520,129 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) unsigned char *RADEONMMIO = info->MMIO; struct avivo_state *state = &save->avivo; - state->mc_memory_map = INMC(pScrn, AVIVO_MC_MEMORY_MAP); - state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); - state->vga_fb_start = INREG(AVIVO_VGA_FB_START); - state->vga1_cntl = INREG(AVIVO_VGA1_CONTROL); - state->vga2_cntl = INREG(AVIVO_VGA2_CONTROL); - - state->pll1_post_div_cntl = INREG(AVIVO_PLL1_POST_DIV_CNTL); - state->pll1_post_div = INREG(AVIVO_PLL1_POST_DIV); - state->pll1_post_div_mystery = INREG(AVIVO_PLL1_POST_DIV_MYSTERY); - state->pll1_post_mul = INREG(AVIVO_PLL1_POST_MUL); - state->pll1_divider_cntl = INREG(AVIVO_PLL1_DIVIDER_CNTL); - state->pll1_divider = INREG(AVIVO_PLL1_DIVIDER); - state->pll1_mystery0 = INREG(AVIVO_PLL1_MYSTERY0); - state->pll1_mystery1 = INREG(AVIVO_PLL1_MYSTERY1); - state->pll2_post_div_cntl = INREG(AVIVO_PLL2_POST_DIV_CNTL); - state->pll2_post_div = INREG(AVIVO_PLL2_POST_DIV); - state->pll2_post_div_mystery = INREG(AVIVO_PLL2_POST_DIV_MYSTERY); - state->pll2_post_mul = INREG(AVIVO_PLL2_POST_MUL); - state->pll2_divider_cntl = INREG(AVIVO_PLL2_DIVIDER_CNTL); - state->pll2_divider = INREG(AVIVO_PLL2_DIVIDER); - state->pll2_mystery0 = INREG(AVIVO_PLL2_MYSTERY0); - state->pll2_mystery1 = INREG(AVIVO_PLL2_MYSTERY1); - state->crtc_pll_source = INREG(AVIVO_CRTC_PLL_SOURCE); - - state->crtc1_h_total = INREG(AVIVO_CRTC1_H_TOTAL); - state->crtc1_h_blank = INREG(AVIVO_CRTC1_H_BLANK); - state->crtc1_h_sync_wid = INREG(AVIVO_CRTC1_H_SYNC_WID); - state->crtc1_h_sync_pol = INREG(AVIVO_CRTC1_H_SYNC_POL); - state->crtc1_v_total = INREG(AVIVO_CRTC1_V_TOTAL); - state->crtc1_v_blank = INREG(AVIVO_CRTC1_V_BLANK); - state->crtc1_v_sync_wid = INREG(AVIVO_CRTC1_V_SYNC_WID); - state->crtc1_v_sync_pol = INREG(AVIVO_CRTC1_V_SYNC_POL); - state->crtc1_cntl = INREG(AVIVO_CRTC1_CNTL); - state->crtc1_blank_status = INREG(AVIVO_CRTC1_BLANK_STATUS); - state->crtc1_stereo_status = INREG(AVIVO_CRTC1_STEREO_STATUS); - state->crtc1_scan_enable = INREG(AVIVO_CRTC1_SCAN_ENABLE); - state->crtc1_fb_format = INREG(AVIVO_CRTC1_FB_FORMAT); - state->crtc1_fb_location = INREG(AVIVO_CRTC1_FB_LOCATION); - state->crtc1_fb_end = INREG(AVIVO_CRTC1_FB_END); - state->crtc1_pitch = INREG(AVIVO_CRTC1_PITCH); - state->crtc1_x_length = INREG(AVIVO_CRTC1_X_LENGTH); - state->crtc1_y_length = INREG(AVIVO_CRTC1_Y_LENGTH); - state->crtc1_fb_height = INREG(AVIVO_CRTC1_FB_HEIGHT); - state->crtc1_offset_start = INREG(AVIVO_CRTC1_OFFSET_START); - state->crtc1_offset_end = INREG(AVIVO_CRTC1_OFFSET_END); - state->crtc1_expn_size = INREG(AVIVO_CRTC1_EXPANSION_SOURCE); - state->crtc1_expn_cntl = INREG(AVIVO_CRTC1_EXPANSION_CNTL); - state->crtc1_6594 = INREG(AVIVO_CRTC1_6594); - state->crtc1_659c = INREG(AVIVO_CRTC1_659C); - state->crtc1_65a4 = INREG(AVIVO_CRTC1_65A4); - state->crtc1_65a8 = INREG(AVIVO_CRTC1_65A8); - state->crtc1_65ac = INREG(AVIVO_CRTC1_65AC); - state->crtc1_65b0 = INREG(AVIVO_CRTC1_65B0); - state->crtc1_65b8 = INREG(AVIVO_CRTC1_65B8); - state->crtc1_65bc = INREG(AVIVO_CRTC1_65BC); - state->crtc1_65c0 = INREG(AVIVO_CRTC1_65C0); - state->crtc1_65c8 = INREG(AVIVO_CRTC1_65C8); - - state->crtc2_h_total = INREG(AVIVO_CRTC2_H_TOTAL); - state->crtc2_h_blank = INREG(AVIVO_CRTC2_H_BLANK); - state->crtc2_h_sync_wid = INREG(AVIVO_CRTC2_H_SYNC_WID); - state->crtc2_h_sync_pol = INREG(AVIVO_CRTC2_H_SYNC_POL); - state->crtc2_v_total = INREG(AVIVO_CRTC2_V_TOTAL); - state->crtc2_v_blank = INREG(AVIVO_CRTC2_V_BLANK); - state->crtc2_v_sync_wid = INREG(AVIVO_CRTC2_V_SYNC_WID); - state->crtc2_v_sync_pol = INREG(AVIVO_CRTC2_V_SYNC_POL); - state->crtc2_cntl = INREG(AVIVO_CRTC2_CNTL); - state->crtc2_blank_status = INREG(AVIVO_CRTC2_BLANK_STATUS); - state->crtc2_scan_enable = INREG(AVIVO_CRTC2_SCAN_ENABLE); - state->crtc2_fb_format = INREG(AVIVO_CRTC2_FB_FORMAT); - state->crtc2_fb_location = INREG(AVIVO_CRTC2_FB_LOCATION); - state->crtc2_fb_end = INREG(AVIVO_CRTC2_FB_END); - state->crtc2_pitch = INREG(AVIVO_CRTC2_PITCH); - state->crtc2_x_length = INREG(AVIVO_CRTC2_X_LENGTH); - state->crtc2_y_length = INREG(AVIVO_CRTC2_Y_LENGTH); - - state->dac1_cntl = INREG(AVIVO_DACA_CNTL); - state->dac1_force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL); - state->dac1_powerdown = INREG(AVIVO_DACA_POWERDOWN); - - state->tmds1_cntl = INREG(AVIVO_TMDSA_CNTL); - state->tmds1_bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL); - state->tmds1_data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION); - state->tmds1_transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE); - state->tmds1_transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL); - - state->dac2_cntl = INREG(AVIVO_DACB_CNTL); - state->dac2_force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL); - state->dac2_powerdown = INREG(AVIVO_DACB_POWERDOWN); - - state->tmds2_cntl = INREG(AVIVO_LVTMA_CNTL); - state->tmds2_bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); - state->tmds2_data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); - state->tmds2_transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE); - state->tmds2_transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL); + // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); + // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); + state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); + state->vga2_cntl = INREG(AVIVO_D1VGA_CONTROL); + + state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); + state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); + + state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); + state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); + state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); + state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); + state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); + state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); + state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); + state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); + + state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); + state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); + state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); + state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); + state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); + state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); + state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); + state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); + + state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); + + state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); + state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); + state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); + state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); + state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); + state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); + + state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); + state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); + state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); + state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); + state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); + state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); + + state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); + state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); + state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); + state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); + + state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); + state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); + state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); + state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); + state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); + state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); + state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); + state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); + state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); + state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); + state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); + state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); + + state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); + state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); + state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE); + + state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); + + state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); + state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); + state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); + state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); + state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); + state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); + + state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); + state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); + state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); + state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); + state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); + state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); + + state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); + state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); + state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); + state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); + + state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); + state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); + state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); + state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); + state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); + state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); + state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); + state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); + state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); + state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); + state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); + state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); + + state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); + state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); + state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE); + + state->daca.enable = INREG(AVIVO_DACA_ENABLE); + state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT); + state->daca.force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL); + state->daca.powerdown = INREG(AVIVO_DACA_POWERDOWN); + + state->dacb.enable = INREG(AVIVO_DACB_ENABLE); + state->dacb.source_select = INREG(AVIVO_DACB_SOURCE_SELECT); + state->dacb.force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL); + state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN); + + state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL); + state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL); + state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION); + state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE); + state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL); + + state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL); + state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); + state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); + state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE); + state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL); } @@ -5628,36 +5652,45 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) unsigned char *RADEONMMIO = info->MMIO; struct avivo_state *state = &restore->avivo; - OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); - OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); - OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); - OUTREG(AVIVO_VGA1_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_VGA2_CONTROL, state->vga2_cntl); - - OUTREG(AVIVO_PLL1_POST_DIV_CNTL, state->pll1_post_div_cntl); - OUTREG(AVIVO_PLL1_POST_DIV, state->pll1_post_div); - OUTREG(AVIVO_PLL1_POST_DIV_MYSTERY, state->pll1_post_div_mystery); - OUTREG(AVIVO_PLL1_POST_MUL, state->pll1_post_mul); - OUTREG(AVIVO_PLL1_DIVIDER_CNTL, state->pll1_divider_cntl); - OUTREG(AVIVO_PLL1_DIVIDER, state->pll1_divider); - OUTREG(AVIVO_PLL1_MYSTERY0, state->pll1_mystery0); - OUTREG(AVIVO_PLL1_MYSTERY1, state->pll1_mystery1); - OUTREG(AVIVO_PLL2_POST_DIV_CNTL, state->pll2_post_div_cntl); - OUTREG(AVIVO_PLL2_POST_DIV, state->pll2_post_div); - OUTREG(AVIVO_PLL2_POST_DIV_MYSTERY, state->pll2_post_div_mystery); - OUTREG(AVIVO_PLL2_POST_MUL, state->pll2_post_mul); - OUTREG(AVIVO_PLL2_DIVIDER_CNTL, state->pll2_divider_cntl); - OUTREG(AVIVO_PLL2_DIVIDER, state->pll2_divider); - OUTREG(AVIVO_PLL2_MYSTERY0, state->pll2_mystery0); - OUTREG(AVIVO_PLL2_MYSTERY1, state->pll2_mystery1); - OUTREG(AVIVO_CRTC_PLL_SOURCE, state->crtc_pll_source); - - OUTREG(AVIVO_CRTC1_H_TOTAL, state->crtc1_h_total); - OUTREG(AVIVO_CRTC1_H_BLANK, state->crtc1_h_blank); - OUTREG(AVIVO_CRTC1_H_SYNC_WID, state->crtc1_h_sync_wid); - OUTREG(AVIVO_CRTC1_H_SYNC_POL, state->crtc1_h_sync_pol); - OUTREG(AVIVO_CRTC1_V_TOTAL, state->crtc1_v_total); - OUTREG(AVIVO_CRTC1_V_BLANK, state->crtc1_v_blank); + // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); + // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); + // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); + + OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); + OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); + + OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en); + OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); + + OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); + OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); + OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); + OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); + OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); + OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); + OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); + OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); + + OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); + OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); + OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); + OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); + OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); + OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); + OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); + OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); + + OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); + + OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); + OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); + OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); + OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); + OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); + OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); + + OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); + OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); /* * Weird we shouldn't restore sync width when going back to text * mode, it must not be a 0 value, i guess a deeper look in cold @@ -5665,71 +5698,100 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) * truely needed to do. */ #if 0 - OUTREG(AVIVO_CRTC1_V_SYNC_WID, state->crtc1_v_sync_wid); + OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1_v_sync_a); #endif - OUTREG(AVIVO_CRTC1_V_SYNC_POL, state->crtc1_v_sync_pol); - OUTREG(AVIVO_CRTC1_CNTL, state->crtc1_cntl); - OUTREG(AVIVO_CRTC1_SCAN_ENABLE, state->crtc1_scan_enable); - OUTREG(AVIVO_CRTC1_FB_FORMAT, state->crtc1_fb_format); - OUTREG(AVIVO_CRTC1_FB_LOCATION, state->crtc1_fb_location); - OUTREG(AVIVO_CRTC1_FB_END, state->crtc1_fb_end); - OUTREG(AVIVO_CRTC1_PITCH, state->crtc1_pitch); - OUTREG(AVIVO_CRTC1_X_LENGTH, state->crtc1_x_length); - OUTREG(AVIVO_CRTC1_Y_LENGTH, state->crtc1_y_length); - OUTREG(AVIVO_CRTC1_FB_HEIGHT, state->crtc1_fb_height); - OUTREG(AVIVO_CRTC1_OFFSET_START, state->crtc1_offset_start); - OUTREG(AVIVO_CRTC1_OFFSET_END, state->crtc1_offset_end); - OUTREG(AVIVO_CRTC1_EXPANSION_SOURCE, state->crtc1_expn_size); - OUTREG(AVIVO_CRTC1_EXPANSION_CNTL, state->crtc1_expn_cntl); - OUTREG(AVIVO_CRTC1_6594, state->crtc1_6594); - OUTREG(AVIVO_CRTC1_659C, state->crtc1_659c); - OUTREG(AVIVO_CRTC1_65A4, state->crtc1_65a4); - OUTREG(AVIVO_CRTC1_65A8, state->crtc1_65a8); - OUTREG(AVIVO_CRTC1_65AC, state->crtc1_65ac); - OUTREG(AVIVO_CRTC1_65B0, state->crtc1_65b0); - OUTREG(AVIVO_CRTC1_65B8, state->crtc1_65b8); - OUTREG(AVIVO_CRTC1_65BC, state->crtc1_65bc); - OUTREG(AVIVO_CRTC1_65C0, state->crtc1_65c0); - OUTREG(AVIVO_CRTC1_65C8, state->crtc1_65c8); - OUTREG(AVIVO_CRTC2_H_TOTAL, state->crtc2_h_total); - OUTREG(AVIVO_CRTC2_H_BLANK, state->crtc2_h_blank); + OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); + OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); + OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); + + OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control); + OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); + OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); + OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); + + OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); + OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); + OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); + OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); + OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); + OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); + OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); + OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); + OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); + OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); + OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); + + OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); + OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); + OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable); + + OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); + + OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); + OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); + OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); + OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); + OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); + OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); + + OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); + OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); + /* + * Weird we shouldn't restore sync width when going back to text + * mode, it must not be a 0 value, i guess a deeper look in cold + * text mode register value would help to understand what is + * truely needed to do. + */ #if 0 - OUTREG(AVIVO_CRTC2_H_SYNC_WID, state->crtc2_h_sync_wid); + OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2_v_sync_a); #endif - OUTREG(AVIVO_CRTC2_H_SYNC_POL, state->crtc2_h_sync_pol); - OUTREG(AVIVO_CRTC2_V_TOTAL, state->crtc2_v_total); - OUTREG(AVIVO_CRTC2_V_BLANK, state->crtc2_v_blank); - OUTREG(AVIVO_CRTC2_V_SYNC_WID, state->crtc2_v_sync_wid); - OUTREG(AVIVO_CRTC2_V_SYNC_POL, state->crtc2_v_sync_pol); - OUTREG(AVIVO_CRTC2_CNTL, state->crtc2_cntl); - OUTREG(AVIVO_CRTC2_BLANK_STATUS, state->crtc2_blank_status); - OUTREG(AVIVO_CRTC2_SCAN_ENABLE, state->crtc2_scan_enable); - OUTREG(AVIVO_CRTC2_FB_FORMAT, state->crtc2_fb_format); - OUTREG(AVIVO_CRTC2_FB_LOCATION, state->crtc2_fb_location); - OUTREG(AVIVO_CRTC2_FB_END, state->crtc2_fb_end); - OUTREG(AVIVO_CRTC2_PITCH, state->crtc2_pitch); - OUTREG(AVIVO_CRTC2_X_LENGTH, state->crtc2_x_length); - OUTREG(AVIVO_CRTC2_Y_LENGTH, state->crtc2_y_length); - - OUTREG(AVIVO_DACA_CNTL, state->dac1_cntl); - OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->dac1_force_output_cntl); - OUTREG(AVIVO_DACA_POWERDOWN, state->dac1_powerdown); - - OUTREG(AVIVO_TMDSA_CNTL, state->tmds1_cntl); - OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1_bit_depth_cntl); - OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1_data_sync); - OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1_transmitter_enable); - OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1_transmitter_cntl); - - OUTREG(AVIVO_DACB_CNTL, state->dac2_cntl); - OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dac2_force_output_cntl); - OUTREG(AVIVO_DACB_POWERDOWN, state->dac2_powerdown); - - OUTREG(AVIVO_LVTMA_CNTL, state->tmds2_cntl); - OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2_bit_depth_cntl); - OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2_data_sync); - OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2_transmitter_enable); - OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2_transmitter_cntl); + OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); + OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); + OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); + + OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control); + OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); + OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); + OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); + + OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); + OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); + OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); + OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); + OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); + OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); + OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); + OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); + OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); + OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); + OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); + + OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); + OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); + OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable); + + + OUTREG(AVIVO_DACA_ENABLE, state->daca.enable); + OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select); + OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->daca.force_output_cntl); + OUTREG(AVIVO_DACA_POWERDOWN, state->daca.powerdown); + + OUTREG(AVIVO_TMDSA_CNTL, state->tmds1.cntl); + OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1.bit_depth_cntl); + OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync); + OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable); + OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl); + + OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable); + OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select); + OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dacb.force_output_cntl); + OUTREG(AVIVO_DACB_POWERDOWN, state->dacb.powerdown); + + OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl); + OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl); + OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync); + OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); + OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); } diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 1122f13..e299481 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3271,6 +3271,422 @@ #define RADEON_RS480_UNK_e38 0xe38 #define RADEON_RS480_UNK_e3c 0xe3c -#include "avivo_reg.h" + +#define AVIVO_MC_INDEX 0x0070 +#define R520_MC_STATUS 0x00 +#define R520_MC_STATUS_IDLE (1<<1) +#define RV515_MC_STATUS 0x08 +#define RV515_MC_STATUS_IDLE (1<<4) +#define AVIVO_MC_DATA 0x0074 + +#define RV515_MC_FB_LOCATION 0x1 +#define RV515_MC_AGP_LOCATION 0x2 +#define R520_MC_FB_LOCATION 0x4 +#define R520_MC_AGP_LOCATION 0x5 + +#define AVIVO_HDP_FB_LOCATION 0x134 + +#define AVIVO_D1VGA_CONTROL 0x0330 +# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) +# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) +# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) +# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) +# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) +# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) +#define AVIVO_D2VGA_CONTROL 0x0338 + +#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 +#define AVIVO_EXT1_PPLL_REF_DIV 0x404 +#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 +#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c + +#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 +#define AVIVO_EXT2_PPLL_REF_DIV 0x414 +#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 +#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c + +#define AVIVO_EXT1_PPLL_FB_DIV 0x430 +#define AVIVO_EXT2_PPLL_FB_DIV 0x434 + +#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 +#define AVIVO_EXT1_PPLL_POST_DIV 0x43c + +#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 +#define AVIVO_EXT2_PPLL_POST_DIV 0x444 + +#define AVIVO_EXT1_PPLL_CNTL 0x448 +#define AVIVO_EXT2_PPLL_CNTL 0x44c + +#define AVIVO_P1PLL_CNTL 0x450 +#define AVIVO_P2PLL_CNTL 0x454 +#define AVIVO_P1PLL_INT_SS_CNTL 0x458 +#define AVIVO_P2PLL_INT_SS_CNTL 0x45c +#define AVIVO_P1PLL_TMDSA_CNTL 0x460 +#define AVIVO_P2PLL_LVTMA_CNTL 0x464 + +#define AVIVO_PCLK_CRTC1_CNTL 0x480 +#define AVIVO_PCLK_CRTC2_CNTL 0x484 + +#define AVIVO_D1CRTC_H_TOTAL 0x6000 +#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 +#define AVIVO_D1CRTC_H_SYNC_A 0x6008 +#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c +#define AVIVO_D1CRTC_H_SYNC_B 0x6010 +#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 + +#define AVIVO_D1CRTC_V_TOTAL 0x6020 +#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 +#define AVIVO_D1CRTC_V_SYNC_A 0x6028 +#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c +#define AVIVO_D1CRTC_V_SYNC_B 0x6030 +#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 + +#define AVIVO_D1CRTC_CONTROL 0x6080 +# define AVIVO_CRTC_EN (1<<0) +#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 +#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 +#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c +#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 + +/* master controls */ +#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 +#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc + +#define AVIVO_D1GRPH_ENABLE 0x6100 +#define AVIVO_D1GRPH_CONTROL 0x6104 +# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) + +# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) + +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) + +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) + + +# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) + +# define AVIVO_D1GRPH_SWAP_RB (1<<16) +# define AVIVO_D1GRPH_TILED (1<<20) +# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) + +#define AVIVO_D1GRPH_LUT_SEL 0x6108 +#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define AVIVO_D1GRPH_PITCH 0x6120 +#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 +#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 +#define AVIVO_D1GRPH_X_START 0x612c +#define AVIVO_D1GRPH_Y_START 0x6130 +#define AVIVO_D1GRPH_X_END 0x6134 +#define AVIVO_D1GRPH_Y_END 0x6138 +#define AVIVO_D1GRPH_UPDATE 0x6144 +#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 + +#define AVIVO_D1CUR_CONTROL 0x6400 +# define AVIVO_D1CURSOR_EN (1<<0) +# define AVIVO_D1CURSOR_MODE_SHIFT 8 +# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) +# define AVIVO_D1CURSOR_MODE_24BPP (0x2) +#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 +#define AVIVO_D1CUR_SIZE 0x6410 +#define AVIVO_D1CUR_POSITION 0x6414 + +#define AVIVO_D1MODE_VIEWPORT_START 0x6580 +#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 +#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c + +#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 + +/* second crtc */ +#define AVIVO_D2CRTC_H_TOTAL 0x6800 +#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 +#define AVIVO_D2CRTC_H_SYNC_A 0x6808 +#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c +#define AVIVO_D2CRTC_H_SYNC_B 0x6810 +#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 + +#define AVIVO_D2CRTC_V_TOTAL 0x6820 +#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 +#define AVIVO_D2CRTC_V_SYNC_A 0x6828 +#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c +#define AVIVO_D2CRTC_V_SYNC_B 0x6830 +#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 + +#define AVIVO_D2CRTC_CONTROL 0x6880 +#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 +#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 +#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c +#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 + +#define AVIVO_D2GRPH_ENABLE 0x6900 +#define AVIVO_D2GRPH_CONTROL 0x6904 +#define AVIVO_D2GRPH_LUT_SEL 0x6908 +#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 +#define AVIVO_D2GRPH_PITCH 0x6920 +#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 +#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 +#define AVIVO_D2GRPH_X_START 0x692c +#define AVIVO_D2GRPH_Y_START 0x6930 +#define AVIVO_D2GRPH_X_END 0x6934 +#define AVIVO_D2GRPH_Y_END 0x6938 +#define AVIVO_D2GRPH_UPDATE 0x6944 +#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 + +#define AVIVO_D2CUR_CONTROL 0x6c00 +#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 +#define AVIVO_D2CUR_SIZE 0x6c10 +#define AVIVO_D2CUR_POSITION 0x6c14 + +#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 +#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 +#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c + +#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 + +#define AVIVO_DACA_ENABLE 0x7800 +# define AVIVO_DAC_ENABLE (1 << 0) +#define AVIVO_DACA_SOURCE_SELECT 0x7804 +# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) +# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) +# define AVIVO_DAC_SOURCE_TV (2 << 0) + +#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACA_POWERDOWN 0x7850 +# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACA_POWERDOWN_RED (1 << 24) + +#define AVIVO_DACB_ENABLE 0x7a00 +#define AVIVO_DACB_SOURCE_SELECT 0x7a04 +#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACB_POWERDOWN 0x7a50 +# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACB_POWERDOWN_RED + +#define AVIVO_TMDSA_CNTL 0x7880 +# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) +# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) +#define AVIVO_TMDSA_CRTC_SOURCE 0x7884 +/* 78a8 appears to be some kind of (reasonably tolerant) clock? + * 78d0 definitely hits the transmitter, definitely clock. */ +/* MYSTERY1 This appears to control dithering? */ +#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) +#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 +# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_CNTL 0x7a80 +# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) +# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) +#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 +#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) + + + +#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 +# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) + +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00 + +#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0 +# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) +# define AVIVO_LVTMA_SYNCEN (1 << 8) +# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) +# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) +# define AVIVO_LVTMA_DIGON (1 << 16) +# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) +# define AVIVO_LVTMA_DIGON_POL (1 << 18) +# define AVIVO_LVTMA_BLON (1 << 24) +# define AVIVO_LVTMA_BLON_OVRD (1 << 25) +# define AVIVO_LVTMA_BLON_POL (1 << 26) + +#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4 +# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) +# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) + +#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 +# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) +# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 +# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 + +#define AVIVO_GPIO_0 0x7e30 +#define AVIVO_GPIO_1 0x7e40 +#define AVIVO_GPIO_2 0x7e50 +#define AVIVO_GPIO_3 0x7e60 + +#define R520_PCLK_HDCP_CNTL 0x494 + +#define AVIVO_I2C_STATUS 0x7d30 +# define AVIVO_I2C_STATUS_DONE (1 << 0) +# define AVIVO_I2C_STATUS_NACK (1 << 1) +# define AVIVO_I2C_STATUS_HALT (1 << 2) +# define AVIVO_I2C_STATUS_GO (1 << 3) +# define AVIVO_I2C_STATUS_MASK 0x7 +/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe + * DONE? */ +# define AVIVO_I2C_STATUS_CMD_RESET 0x7 +# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) +#define AVIVO_I2C_STOP 0x7d34 +#define AVIVO_I2C_START_CNTL 0x7d38 +# define AVIVO_I2C_START (1 << 8) +# define AVIVO_I2C_CONNECTOR0 (0 << 16) +# define AVIVO_I2C_CONNECTOR1 (1 << 16) +#define R520_I2C_START (1<<0) +#define R520_I2C_STOP (1<<1) +#define R520_I2C_RX (1<<2) +#define R520_I2C_EN (1<<8) +#define R520_I2C_DDC1 (0<<16) +#define R520_I2C_DDC2 (1<<16) +#define R520_I2C_DDC3 (2<<16) +#define R520_I2C_DDC_MASK (3<<16) +#define AVIVO_I2C_CONTROL2 0x7d3c +# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 +# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) +#define AVIVO_I2C_CONTROL3 0x7d40 +/* Reading is done 4 bytes at a time: read the bottom 8 bits from + * 7d44, four times in a row. + * Writing is a little more complex. First write DATA with + * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic + * magic number, zz is, I think, the slave address, and yy is the byte + * you want to write. */ +#define AVIVO_I2C_DATA 0x7d44 +#define R520_I2C_ADDR_COUNT_MASK (0x7) +#define R520_I2C_DATA_COUNT_SHIFT (8) +#define R520_I2C_DATA_COUNT_MASK (0xF00) +#define AVIVO_I2C_CNTL 0x7d50 +# define AVIVO_I2C_EN (1 << 0) +# define AVIVO_I2C_RESET (1 << 8) #endif |