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-rw-r--r--src/radeon_bios.c20
-rw-r--r--src/radeon_output.c14
-rw-r--r--src/radeon_tv.c6
-rw-r--r--src/radeon_video.c15
4 files changed, 19 insertions, 36 deletions
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 975fc07..7dcb5d5 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -619,8 +619,7 @@ Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) {
ErrorF("\n");
return TRUE;
- } else
- return FALSE;
+ }
}
}
return FALSE;
@@ -1077,7 +1076,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
case RADEON_TABLE_FLAG_WRITE_INDEXED:
val = RADEON_BIOS32(offset);
ErrorF("WRITE INDEXED: 0x%x 0x%x\n",
- index, val);
+ index, (unsigned)val);
OUTREG(RADEON_MM_INDEX, index);
OUTREG(RADEON_MM_DATA, val);
offset += 4;
@@ -1085,7 +1084,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
case RADEON_TABLE_FLAG_WRITE_DIRECT:
val = RADEON_BIOS32(offset);
- ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, val);
+ ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val);
OUTREG(index, val);
offset += 4;
break;
@@ -1096,7 +1095,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
ormask = RADEON_BIOS32(offset);
offset += 4;
ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n",
- index, andmask, ormask);
+ index, (unsigned)andmask, (unsigned)ormask);
OUTREG(RADEON_MM_INDEX, index);
val = INREG(RADEON_MM_DATA);
val = (val & andmask) | ormask;
@@ -1109,7 +1108,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
ormask = RADEON_BIOS32(offset);
offset += 4;
ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n",
- index, andmask, ormask);
+ index, (unsigned)andmask, (unsigned)ormask);
val = INREG(index);
val = (val & andmask) | ormask;
OUTREG(index, val);
@@ -1198,7 +1197,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
offset += 2;
ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n",
- RADEON_SDRAM_MODE_MASK, ormask);
+ RADEON_SDRAM_MODE_MASK, (unsigned)ormask);
/* can this use direct access? */
OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG);
@@ -1209,7 +1208,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
ormask = (CARD32)index << 24;
ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n",
- RADEON_B3MEM_RESET_MASK, ormask);
+ RADEON_B3MEM_RESET_MASK, (unsigned)ormask);
/* can this use direct access? */
OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG);
@@ -1224,7 +1223,6 @@ static void
RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
CARD16 offset = table_offset;
CARD8 index, shift;
CARD32 andmask, ormask, val, clk_pwrmgt_cntl;
@@ -1298,7 +1296,7 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
offset++;
ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n",
- index, shift, andmask, ormask);
+ index, shift, (unsigned)andmask, (unsigned)ormask);
val = INPLL(pScrn, index);
val = (val & andmask) | ormask;
OUTPLL(pScrn, index, val);
@@ -1306,7 +1304,7 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
case RADEON_PLL_FLAG_WRITE:
val = RADEON_BIOS32(offset);
- ErrorF("PLL_WRITE 0x%x 0x%x\n", index, val);
+ ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val);
OUTPLL(pScrn, index, val);
offset += 4;
break;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 940bb01..b9e01a1 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -654,8 +654,6 @@ static Bool
radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) {
@@ -1229,12 +1227,9 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color)
/* save the regs we need */
pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (IS_R300_VARIANT) {
- gpiopad_a = INREG(RADEON_GPIOPAD_A);
- disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
- } else {
- disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG);
- }
+ gpiopad_a = IS_R300_VARIANT ? INREG(RADEON_GPIOPAD_A) : 0;
+ disp_output_cntl = IS_R300_VARIANT ? INREG(RADEON_DISP_OUTPUT_CNTL) : 0;
+ disp_hw_debug = !IS_R300_VARIANT ? INREG(RADEON_DISP_HW_DEBUG) : 0;
crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
@@ -2286,10 +2281,7 @@ RADEONGetTMDSInfo(xf86OutputPtr output)
static void
RADEONGetTVInfo(xf86OutputPtr output)
{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i;
radeon_output->hPos = 0;
radeon_output->vPos = 0;
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 522f7ed..bc2905a 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -187,9 +187,7 @@ static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode)
{
- ScrnInfoPtr pScrn = output->scrn;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
int restart;
unsigned hTotal;
unsigned vTotal;
@@ -274,7 +272,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
save->tv_frestart = restart % fTotal;
ErrorF("computeRestarts: F/H/V=%u,%u,%u\n",
- save->tv_frestart , save->tv_vrestart , save->tv_hrestart);
+ (unsigned)save->tv_frestart, (unsigned)save->tv_vrestart,
+ (unsigned)save->tv_hrestart);
/* Compute H_INC from hSize */
if (radeon_output->tvStd == TV_STD_NTSC ||
@@ -570,7 +569,6 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
Bool reloadTable;
RADEONSavePtr restore = &info->ModeReg;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 15e2101..7231c1e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -2587,20 +2587,19 @@ RADEONDisplayVideo(
y_mult = 2;
}
+ v_inc = (src_h << v_inc_shift) / drw_h;
+
for (i = 0; i < xf86_config->num_output; i++) {
output = xf86_config->output[i];
if (output->crtc == crtc) {
radeon_output = output->driver_private;
+ if (radeon_output->Flags & RADEON_USE_RMX)
+ v_inc = ((src_h * mode->CrtcVDisplay /
+ radeon_output->PanelYRes) << v_inc_shift) / drw_h;
break;
}
}
- if (radeon_output->Flags & RADEON_USE_RMX) {
- v_inc = ((src_h * mode->CrtcVDisplay / radeon_output->PanelYRes) << v_inc_shift) / drw_h;
- } else {
- v_inc = (src_h << v_inc_shift) / drw_h;
- }
-
h_inc = (1 << (12 + ecp_div));
step_by_y = 1;
@@ -2860,7 +2859,6 @@ RADEONPutImage(
DrawablePtr pDraw
){
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
INT32 xa, xb, ya, yb;
unsigned char *dst_start;
@@ -3259,7 +3257,6 @@ RADEONDisplaySurface(
){
OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr;
ScrnInfoPtr pScrn = surface->pScrn;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr;
@@ -3362,7 +3359,6 @@ RADEONPutVideo(
){
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
INT32 xa, xb, ya, yb, top;
unsigned int pitch, new_size, alloc_size;
@@ -3376,7 +3372,6 @@ RADEONPutVideo(
int mult;
int vbi_line_width, vbi_start, vbi_end;
xf86CrtcPtr crtc;
- RADEONCrtcPrivatePtr radeon_crtc;
RADEON_SYNC(info, pScrn);
/*
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:11:18 +0000