diff options
Diffstat (limited to 'src/r128_reg.h')
| -rw-r--r-- | src/r128_reg.h | 65 |
1 files changed, 64 insertions, 1 deletions
diff --git a/src/r128_reg.h b/src/r128_reg.h index 98b89bf..31883e3 100644 --- a/src/r128_reg.h +++ b/src/r128_reg.h @@ -76,7 +76,7 @@ #define OUTPLL(addr, val) \ do { \ - OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ + OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \ OUTREG(R128_CLOCK_CNTL_DATA, val); \ } while (0) @@ -189,6 +189,9 @@ # define R128_BIOS_DISPLAY_FP (1 << 0) # define R128_BIOS_DISPLAY_CRT (2 << 0) # define R128_BIOS_DISPLAY_FP_CRT (3 << 0) +/* R128_DUALHEAD is just a flag for the driver; + it doesn't actually correspond to any bits */ +# define R128_DUALHEAD 4 #define R128_BIOS_6_SCRATCH 0x0028 #define R128_BIOS_7_SCRATCH 0x002c #define R128_BIOS_ROM 0x0f30 /* PCI */ @@ -284,6 +287,7 @@ #define R128_CLOCK_CNTL_INDEX 0x0008 # define R128_PLL_WR_EN (1 << 7) # define R128_PLL_DIV_SEL (3 << 8) +# define R128_PLL2_DIV_SEL_MASK ~(3 << 8) #define R128_CLR_CMP_CLR_3D 0x1a24 #define R128_CLR_CMP_CLR_DST 0x15c8 #define R128_CLR_CMP_CLR_SRC 0x15c4 @@ -374,15 +378,41 @@ #define R128_CRTC2_CRNT_FRAME 0x0314 #define R128_CRTC2_DEBUG 0x031c #define R128_CRTC2_GEN_CNTL 0x03f8 +# define R128_CRTC2_DBL_SCAN_EN (1 << 0) +# define R128_CRTC2_CUR_EN (1 << 16) +# define R128_CRTC2_ICON_EN (1 << 20) +# define R128_CRTC2_DISP_DIS (1 << 23) +# define R128_CRTC2_EN (1 << 25) +# define R128_CRTC2_DISP_REQ_EN_B (1 << 26) #define R128_CRTC2_GUI_TRIG_VLINE 0x0318 #define R128_CRTC2_H_SYNC_STRT_WID 0x0304 +# define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3) +# define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define R128_CRTC2_H_SYNC_WID (0x3f << 16) +# define R128_CRTC2_H_SYNC_WID_SHIFT 16 +# define R128_CRTC2_H_SYNC_POL (1 << 23) #define R128_CRTC2_H_TOTAL_DISP 0x0300 +# define R128_CRTC2_H_TOTAL (0x01ff << 0) +# define R128_CRTC2_H_TOTAL_SHIFT 0 +# define R128_CRTC2_H_DISP (0x00ff << 16) +# define R128_CRTC2_H_DISP_SHIFT 16 #define R128_CRTC2_OFFSET 0x0324 #define R128_CRTC2_OFFSET_CNTL 0x0328 +# define R128_CRTC2_TILE_EN (1 << 15) #define R128_CRTC2_PITCH 0x032c #define R128_CRTC2_STATUS 0x03fc #define R128_CRTC2_V_SYNC_STRT_WID 0x030c +# define R128_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define R128_CRTC2_V_SYNC_STRT_SHIFT 0 +# define R128_CRTC2_V_SYNC_WID (0x1f << 16) +# define R128_CRTC2_V_SYNC_WID_SHIFT 16 +# define R128_CRTC2_V_SYNC_POL (1 << 23) #define R128_CRTC2_V_TOTAL_DISP 0x0308 +# define R128_CRTC2_V_TOTAL (0x07ff << 0) +# define R128_CRTC2_V_TOTAL_SHIFT 0 +# define R128_CRTC2_V_DISP (0x07ff << 16) +# define R128_CRTC2_V_DISP_SHIFT 16 #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 #define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ #define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ @@ -392,12 +422,19 @@ #define R128_CUR_HORZ_VERT_POSN 0x0264 #define R128_CUR_OFFSET 0x0260 # define R128_CUR_LOCK (1 << 31) +#define R128_CUR2_CLR0 0x036c +#define R128_CUR2_CLR1 0x0370 +#define R128_CUR2_HORZ_VERT_OFF 0x0368 +#define R128_CUR2_HORZ_VERT_POSN 0x0364 +#define R128_CUR2_OFFSET 0x0360 +# define R128_CUR2_LOCK (1 << 31) #define R128_DAC_CNTL 0x0058 # define R128_DAC_RANGE_CNTL (3 << 0) # define R128_DAC_BLANKING (1 << 2) # define R128_DAC_CRT_SEL_CRTC2 (1 << 4) # define R128_DAC_PALETTE_ACC_CTL (1 << 5) +# define R128_DAC_PALETTE2_SNOOP_EN (1 << 6) # define R128_DAC_8BIT_EN (1 << 8) # define R128_DAC_VGA_ADR_EN (1 << 13) # define R128_DAC_MASK_ALL (0xff << 24) @@ -408,11 +445,16 @@ #define R128_DAC_W_INDEX 0x03c8 /* VGA */ #define R128_DDA_CONFIG 0x02e0 #define R128_DDA_ON_OFF 0x02e4 +#define R128_DDA2_CONFIG 0x03e0 +#define R128_DDA2_ON_OFF 0x03e4 #define R128_DEFAULT_OFFSET 0x16e0 #define R128_DEFAULT_PITCH 0x16e4 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define R128_DEFAULT2_OFFSET 0x16f8 +#define R128_DEFAULT2_PITCH 0x16fc +#define R128_DEFAULT2_SC_BOTTOM_RIGHT 0x16dc #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define R128_DEVICE_ID 0x0f02 /* PCI */ @@ -670,6 +712,7 @@ #define R128_HOST_DATA_LAST 0x17e0 #define R128_HOST_PATH_CNTL 0x0130 #define R128_HTOTAL_CNTL 0x0009 /* PLL */ +#define R128_HTOTAL2_CNTL 0x002e /* PLL */ #define R128_HW_DEBUG 0x0128 #define R128_HW_DEBUG2 0x011c @@ -875,6 +918,19 @@ # define R128_PPLL_REF_DIV_MASK 0x03ff # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define R128_P2PLL_CNTL 0x002a /* P2PLL */ +# define R128_P2PLL_RESET (1 << 0) +# define R128_P2PLL_SLEEP (1 << 1) +# define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define R128_P2PLL_DIV_0 0x002c +# define R128_P2PLL_FB0_DIV_MASK 0x07ff +# define R128_P2PLL_POST0_DIV_MASK 0x00070000 +#define R128_P2PLL_REF_DIV 0x002B /* PLL */ +# define R128_P2PLL_REF_DIV_MASK 0x03ff +# define R128_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define R128_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ #define R128_REG_BASE 0x0f18 /* PCI */ #define R128_REGPROG_INF 0x0f09 /* PCI */ @@ -935,7 +991,14 @@ #define R128_TRAIL_X_SUB 0x1620 #define R128_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define R128_VCLK_SRC_SEL_MASK 0x03 +# define R128_VCLK_SRC_SEL_CPUCLK 0x00 +# define R128_VCLK_SRC_SEL_PPLLCLK 0x03 # define R128_ECP_DIV_MASK (3 << 8) +#define R128_V2CLK_VCLKTV_CNTL 0x002d /* PLL */ +# define R128_V2CLK_SRC_SEL_MASK 0x03 +# define R128_V2CLK_SRC_SEL_CPUCLK 0x00 +# define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03 #define R128_VENDOR_ID 0x0f00 /* PCI */ #define R128_VGA_DDA_CONFIG 0x02e8 #define R128_VGA_DDA_ON_OFF 0x02ec |