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use xf86_crtc_clip_video_helper() from the server if available.
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The old code would attempt to limit the maximum pixel size of the screen
by limiting the maximum PLL frequency. This ends up confusing the PLL
computation code since sometimes your maximum freq can be lower than your
minimum freq. More to the point it's just wrong, maximum PLL frequency
isn't the same thing as maximum pixel clock, and even that isn't the same
thing as maximum scanout pixels per second.
The correct thing to do is filter by the mode's effective memory bandwidth.
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ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati
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add output enable masks for outputs that drive
more than one connector. Make sure we don't turn off
an output that's driving another connector.
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- reduce the calculation accuracy
- certain LVDS panels seem to only like certain ref_divs
- add pll flags to handle special cases
- adjust the pll limits on legacy cards
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Seems more reliable in general than what was set up by firmware - fingers
crossed...
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The lid detection code probably wouldn't work on other non-x86 platforms
though...
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This partially fixes transformed pictures on R100/R200 based
cards. The texture still doesn't appear to be clamped correctly,
but since that doesn't matter for rotations at perpendicular
angles, I'm committing this now so randr rotation and reflection
will work properly.
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Some LVDS panels require specific PLL dividers as
specified in the bios tables. Make sure to use them
if the output is LVDS.
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Fixes bug 8038
I wonder if desktop RV410 need a similar fix.
If your x700 laptop panel has problems after this let me know.
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should fix bug 13610
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Linux only
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allocate separate cursor buffers for each crtc
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Algorithm adapted from BeOS radeon driver with some tweaks by me.
Actually calulate and use the reference divider rather than using the bios default.
Also, always calculate the PLL, rather than falling back to bios dividers.
This should fix bugs 12913, 13590, 13533, possibly others.
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Thanks to Étienne Bersac for helping to figure this out.
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* Make sure pitch constraints are always met for DMA upload blits.
* RGB24 is not affected by endianness.
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See https://bugs.freedesktop.org/show_bug.cgi?id=13274 .
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(DE)ALLOCATE_LOCAL are gone.
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Also fix a typo in internal tv-out parsing
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this brings in some previous research from Michel Dänzer,
Sjoerd Simons, and myself. Hopefully, the driver will pick
the correct MacModel in more cases. This also changes the
default connector table for desktop Macs to dual DVI rather
than DVI+VGA as that seems to be the case more often than not.
External TMDS chips are handled separately now as well.
Eventually we should add an option to allow the user to specify
what external TMDS chip they need, but we don't have enough info
yet, so we'll rely on OF to init the external chip in most cases
for now.
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Some macs (minis and powerbooks) use internal tmds, others use external tmds
and not just for dual-link TMDS, it shows up with single-link as well.
Unforunately, there doesn't seem to be any good way to figure it out.
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It seems the bios scratch regs are involved in backlight control
on some laptops. This patch fixes the problematic laptops and doesn't
seem to break the previous bios lid and output control fixes.
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this seems to cause more issues than it attempted to fix
so limit it to XPRESS chips for now.
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This reverts commit 145da701bf4fb9c0ad9f95620b20914ae0126852.
pull in fix from ajax next commit
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Novell Bug #341699: Render acceleration is known to be broken
on at least "Radeon 7500 QW" and "Radeon Mobility M7 LW".
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fix the if condition testing for these chips...
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This uses a single file with all the pciids and parameters for radeon
family and setup in it. I don't run the perl script at build time to avoid
a perl dependency on build but adding pci ids should be done via the csv file
with openoffice or gnumeric if possible.
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we should get these values from the bios tables, but for now use
some reasonable defaults. This should fix the washed out color
problems on bugs 1082 and 12844.
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bit is wrong on at least X700 cards with rialto pcie-agp bridge chip,
should be safe to use just the bit from the bridge hopefully to make
agp setup work on these cards and not adversely affect others.
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This avoids hangs that occur when touching these registers while the card is
busy with some cards.
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This reverts commit 0241cac643fa1c08a45ea44f5c670b290e760ad8.
Taking the DRI lock in paths called from the SIGIO handler isn't safe. For
example, the SIGIO handler may be called while the lock is held by an AIGLX
context, resulting in deadlock. See e.g.
https://bugs.freedesktop.org/show_bug.cgi?id=13005 .
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Bug #12984.
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These bits don't seem to be reliable or routed right
in all cases.
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