From 1c7c3372776d6d116facabbf055f27af3e96f59f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 1 Jul 2005 04:16:42 +0000 Subject: - fix depth tiling for r3/4xx chips (Aapo Tahkola) - adjust limits for tiled surfaces on r3/4xx --- man/radeon.man | 3 ++- src/radeon.h | 3 +++ src/radeon_driver.c | 51 ++++++++++++++++++++++++--------------------------- src/radeon_reg.h | 3 +++ 4 files changed, 32 insertions(+), 28 deletions(-) diff --git a/man/radeon.man b/man/radeon.man index 6cca630..b08ba06 100644 --- a/man/radeon.man +++ b/man/radeon.man @@ -439,7 +439,8 @@ The default value is .BI "Option \*qColorTiling\*q \*q" "boolean" \*q Frame buffer can be addressed either in linear or tiled mode. Tiled mode can provide significant performance benefits with 3D applications, for 2D it shouldn't matter -much. Tiling will be disabled if the virtual x resolution exceeds 2048, if option +much. Tiling will be disabled if the virtual x resolution exceeds 2048 (3968 for R300 +and above), if option .B UseFBDev is used, or (if DRI is enabled) the drm module is too old. .br diff --git a/src/radeon.h b/src/radeon.h index 593baf2..814db80 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -654,6 +654,9 @@ typedef struct { Bool VGAAccess; + int MaxSurfaceWidth; + int MaxLines; + } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 571709e..55d9b8b 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -3687,7 +3687,7 @@ static int RADEONValidateMergeModes(ScrnInfoPtr pScrn1) NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - info->allowColorTiling ? 2048 : + info->allowColorTiling ? info->MaxSurfaceWidth : 64 * pScrn1->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ 8 * 1024, /*2048,*/ /* maxHeight */ @@ -3750,7 +3750,7 @@ static int RADEONValidateMergeModes(ScrnInfoPtr pScrn1) NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - info->allowColorTiling ? 2048 : + info->allowColorTiling ? info->MaxSurfaceWidth : 64 * pScrn1->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ 8 * 1024, /*2048,*/ /* maxHeight */ @@ -3952,10 +3952,10 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - info->allowColorTiling ? 2048 : + info->allowColorTiling ? info->MaxSurfaceWidth : 64 * pScrn->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ - 2048, /* maxHeight */ + info->MaxLines, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, info->FbMapSize, @@ -4021,10 +4021,10 @@ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - info->allowColorTiling ? 2048 : + info->allowColorTiling ? info->MaxSurfaceWidth : 64 * pScrn->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ - 2048, /* maxHeight */ + info->MaxLines, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, info->FbMapSize, @@ -4749,9 +4749,13 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) /* false by default on R3/4xx */ info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, FALSE); + info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ + info->MaxLines = 4096; } else { info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, TRUE); + info->MaxSurfaceWidth = 2048; + info->MaxLines = 2048; } if ((info->allowColorTiling) && (info->IsSecondary)) { @@ -5045,9 +5049,10 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } - if (info->allowColorTiling && (pScrn->virtualX > 2048)) { + if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Color tiling not supported with virtual x resolutions larger than 2048, disabling\n"); + "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", + info->MaxSurfaceWidth); info->allowColorTiling = FALSE; } if (info->allowColorTiling) { @@ -5146,20 +5151,6 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "DRI at present.\n" "Please use the radeon MergedFB option if you " "want Dual-head with DRI.\n"); -#if 0 - } else if ( pScrn->virtualX > 2048 || pScrn->virtualY > 2048 ) { - if (info->No2048Limit) { - info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "DRI forced on with virtual screen of greater than 2048.\n"); - } else { - info->directRenderingEnabled = FALSE; - xf86DrvMsg(scrnIndex, X_WARNING, - "Direct Rendering Disabled -- " - "Virtual resolution exceeds 2048 " - "(hardware limitation)\n"); - } -#endif } else { info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); } @@ -6110,10 +6101,13 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; else depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; - } - else { - /* no idea about R300, just set it up the same as r200 - if someone is crazy enough to try... */ + } else if (IS_R300_VARIANT) { + color_pattern = R300_SURF_TILE_COLOR_MACRO; + if (cpp == 2) + depth_pattern = R300_SURF_TILE_COLOR_MACRO; + else + depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; + } else { color_pattern = R200_SURF_TILE_COLOR_MACRO; if (cpp == 2) depth_pattern = R200_SURF_TILE_DEPTH_16BPP; @@ -6175,7 +6169,10 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) drmRadeonSurfaceAlloc drmsurfalloc; drmsurfalloc.size = bufferSize; drmsurfalloc.address = info->depthOffset; - drmsurfalloc.flags = swap_pattern | (width_bytes / 16) | depth_pattern; + if (IS_R300_VARIANT) + drmsurfalloc.flags = swap_pattern | (width_bytes / 8) | depth_pattern; + else + drmsurfalloc.flags = swap_pattern | (width_bytes / 16) | depth_pattern; retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, &drmsurfalloc, sizeof(drmsurfalloc)); if (retvalue < 0) diff --git a/src/radeon_reg.h b/src/radeon_reg.h index c4228e5..92418e6 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -1314,6 +1314,9 @@ # define R200_SURF_TILE_COLOR_BOTH (3 << 16) # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define R300_SURF_TILE_NONE (0 << 16) +# define R300_SURF_TILE_COLOR_MACRO (1 << 16) +# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) -- cgit v1.2.3