From bb5ede557bf32a42eef158ff0fbcfe1c6ede098a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 7 Dec 2007 14:30:32 +1000 Subject: radeon: move savedreg/modereg into entity instead of info --- src/radeon.h | 168 +------------------------------------------------ src/radeon_accel.c | 2 +- src/radeon_crtc.c | 72 ++++++++++----------- src/radeon_display.c | 8 +-- src/radeon_dri.c | 4 +- src/radeon_driver.c | 21 +++++-- src/radeon_output.c | 68 ++++++++++---------- src/radeon_probe.h | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/radeon_tv.c | 4 +- src/radeon_tv.h | 5 -- src/radeon_video.c | 6 +- 11 files changed, 274 insertions(+), 258 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index fe491e8..529374e 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -200,169 +200,7 @@ typedef struct { CARD16 rr4_offset; } RADEONBIOSInitTable; -typedef struct { - /* Common registers */ - CARD32 ovr_clr; - CARD32 ovr_wid_left_right; - CARD32 ovr_wid_top_bottom; - CARD32 ov0_scale_cntl; - CARD32 mpp_tb_config; - CARD32 mpp_gp_config; - CARD32 subpic_cntl; - CARD32 viph_control; - CARD32 i2c_cntl_1; - CARD32 gen_int_cntl; - CARD32 cap0_trig_cntl; - CARD32 cap1_trig_cntl; - CARD32 bus_cntl; - CARD32 bios_4_scratch; - CARD32 bios_5_scratch; - CARD32 bios_6_scratch; - CARD32 surface_cntl; - CARD32 surfaces[8][3]; - CARD32 mc_agp_location; - CARD32 mc_fb_location; - CARD32 display_base_addr; - CARD32 display2_base_addr; - CARD32 ov0_base_addr; - - /* Other registers to save for VT switches */ - CARD32 dp_datatype; - CARD32 rbbm_soft_reset; - CARD32 clock_cntl_index; - CARD32 amcgpio_en_reg; - CARD32 amcgpio_mask; - - /* CRTC registers */ - CARD32 crtc_gen_cntl; - CARD32 crtc_ext_cntl; - CARD32 dac_cntl; - CARD32 crtc_h_total_disp; - CARD32 crtc_h_sync_strt_wid; - CARD32 crtc_v_total_disp; - CARD32 crtc_v_sync_strt_wid; - CARD32 crtc_offset; - CARD32 crtc_offset_cntl; - CARD32 crtc_pitch; - CARD32 disp_merge_cntl; - CARD32 grph_buffer_cntl; - CARD32 crtc_more_cntl; - CARD32 crtc_tile_x0_y0; - - /* CRTC2 registers */ - CARD32 crtc2_gen_cntl; - CARD32 dac_macro_cntl; - CARD32 dac2_cntl; - CARD32 disp_output_cntl; - CARD32 disp_tv_out_cntl; - CARD32 disp_hw_debug; - CARD32 disp2_merge_cntl; - CARD32 grph2_buffer_cntl; - CARD32 crtc2_h_total_disp; - CARD32 crtc2_h_sync_strt_wid; - CARD32 crtc2_v_total_disp; - CARD32 crtc2_v_sync_strt_wid; - CARD32 crtc2_offset; - CARD32 crtc2_offset_cntl; - CARD32 crtc2_pitch; - CARD32 crtc2_tile_x0_y0; - - /* Flat panel registers */ - CARD32 fp_crtc_h_total_disp; - CARD32 fp_crtc_v_total_disp; - CARD32 fp_gen_cntl; - CARD32 fp2_gen_cntl; - CARD32 fp_h_sync_strt_wid; - CARD32 fp_h2_sync_strt_wid; - CARD32 fp_horz_stretch; - CARD32 fp_panel_cntl; - CARD32 fp_v_sync_strt_wid; - CARD32 fp_v2_sync_strt_wid; - CARD32 fp_vert_stretch; - CARD32 lvds_gen_cntl; - CARD32 lvds_pll_cntl; - CARD32 tmds_pll_cntl; - CARD32 tmds_transmitter_cntl; - - /* Computed values for PLL */ - CARD32 dot_clock_freq; - CARD32 pll_output_freq; - int feedback_div; - int post_div; - - /* PLL registers */ - unsigned ppll_ref_div; - unsigned ppll_div_3; - CARD32 htotal_cntl; - CARD32 vclk_ecp_cntl; - - /* Computed values for PLL2 */ - CARD32 dot_clock_freq_2; - CARD32 pll_output_freq_2; - int feedback_div_2; - int post_div_2; - - /* PLL2 registers */ - CARD32 p2pll_ref_div; - CARD32 p2pll_div_0; - CARD32 htotal_cntl2; - CARD32 pixclks_cntl; - - /* Pallet */ - Bool palette_valid; - CARD32 palette[256]; - CARD32 palette2[256]; - - CARD32 rs480_unk_e30; - CARD32 rs480_unk_e34; - CARD32 rs480_unk_e38; - CARD32 rs480_unk_e3c; - - /* TV out registers */ - CARD32 tv_master_cntl; - CARD32 tv_htotal; - CARD32 tv_hsize; - CARD32 tv_hdisp; - CARD32 tv_hstart; - CARD32 tv_vtotal; - CARD32 tv_vdisp; - CARD32 tv_timing_cntl; - CARD32 tv_vscaler_cntl1; - CARD32 tv_vscaler_cntl2; - CARD32 tv_sync_size; - CARD32 tv_vrestart; - CARD32 tv_hrestart; - CARD32 tv_frestart; - CARD32 tv_ftotal; - CARD32 tv_clock_sel_cntl; - CARD32 tv_clkout_cntl; - CARD32 tv_data_delay_a; - CARD32 tv_data_delay_b; - CARD32 tv_dac_cntl; - CARD32 tv_pll_cntl; - CARD32 tv_pll_cntl1; - CARD32 tv_pll_fine_cntl; - CARD32 tv_modulator_cntl1; - CARD32 tv_modulator_cntl2; - CARD32 tv_frame_lock_cntl; - CARD32 tv_pre_dac_mux_cntl; - CARD32 tv_rgb_cntl; - CARD32 tv_y_saw_tooth_cntl; - CARD32 tv_y_rise_cntl; - CARD32 tv_y_fall_cntl; - CARD32 tv_uv_adr; - CARD32 tv_upsamp_and_gain_cntl; - CARD32 tv_gain_limit_settings; - CARD32 tv_linear_gain_settings; - CARD32 tv_crc_cntl; - CARD32 tv_sync_cntl; - CARD32 gpiopad_a; - CARD32 pll_test_cntl; - - CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; - CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; - -} RADEONSaveRec, *RADEONSavePtr; + typedef struct { CARD16 reference_freq; @@ -522,8 +360,8 @@ typedef struct { Bool IsDDR; int DispPriority; - RADEONSaveRec SavedReg; /* Original (text) mode */ - RADEONSaveRec ModeReg; /* Current mode */ + RADEONSavePtr SavedReg; /* Original (text) mode */ + RADEONSavePtr ModeReg; /* Current mode */ Bool (*CloseScreen)(int, ScreenPtr); void (*BlockHandler)(int, pointer, pointer, pointer); diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 6028aff..7f05578 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -322,7 +322,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) #endif /* Restore SURFACE_CNTL */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); RADEONWaitForFifo(pScrn, 1); OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index b1d216d..718073c 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -311,7 +311,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, return FALSE; } - /*save->bios_4_scratch = info->SavedReg.bios_4_scratch;*/ + /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN | (format << 8) @@ -330,7 +330,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS); - save->disp_merge_cntl = info->SavedReg.disp_merge_cntl; + save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; save->crtc_more_cntl = 0; @@ -380,10 +380,10 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, save->fp_crtc_v_total_disp = save->crtc_v_total_disp; if (info->IsDellServer) { - save->dac2_cntl = info->SavedReg.dac2_cntl; - save->tv_dac_cntl = info->SavedReg.tv_dac_cntl; - save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl; - save->disp_hw_debug = info->SavedReg.disp_hw_debug; + save->dac2_cntl = info->SavedReg->dac2_cntl; + save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; + save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; + save->disp_hw_debug = info->SavedReg->disp_hw_debug; save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; @@ -589,7 +589,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, ? RADEON_CRTC2_INTERLACE_EN : 0)); - save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl; + save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; @@ -687,7 +687,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, save->htotal_cntl = 0; - save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & + save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; } @@ -757,7 +757,7 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, (post_div->bitvalue << 16)); save->htotal_cntl2 = 0; - save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & + save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); @@ -770,8 +770,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) /* tell the bios not to muck with the hardware on events */ save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */ - save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ - save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000; + save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ + save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000; } @@ -823,38 +823,38 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, } if (info->IsMobility) - RADEONInitBIOSRegisters(pScrn, &info->ModeReg); + RADEONInitBIOSRegisters(pScrn, info->ModeReg); ErrorF("init memmap\n"); - RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info); + RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); ErrorF("init common\n"); - RADEONInitCommonRegisters(&info->ModeReg, info); + RADEONInitCommonRegisters(info->ModeReg, info); - RADEONInitSurfaceCntl(crtc, &info->ModeReg); + RADEONInitSurfaceCntl(crtc, info->ModeReg); switch (radeon_crtc->crtc_id) { case 0: ErrorF("init crtc1\n"); - RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode); - RADEONInitCrtcBase(crtc, &info->ModeReg, x, y); + RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); + RADEONInitCrtcBase(crtc, info->ModeReg, x, y); dot_clock = adjusted_mode->Clock / 1000.0; if (dot_clock) { ErrorF("init pll1\n"); - RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock); + RADEONInitPLLRegisters(pScrn, info, info->ModeReg, &info->pll, dot_clock); } else { - info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; - info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; - info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; + info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; + info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; + info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; } break; case 1: ErrorF("init crtc2\n"); - RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); - RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y); + RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); + RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); dot_clock = adjusted_mode->Clock / 1000.0; if (dot_clock) { ErrorF("init pll2\n"); - RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div); + RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, dot_clock, no_odd_post_div); } break; } @@ -867,13 +867,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { switch (radeon_crtc->crtc_id) { case 0: - RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); - RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); + RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); update_tv_routing = TRUE; break; case 1: - RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); - RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); + RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); break; } } @@ -881,31 +881,31 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, } if (info->IsMobility) - RADEONRestoreBIOSRegisters(pScrn, &info->ModeReg); + RADEONRestoreBIOSRegisters(pScrn, info->ModeReg); ErrorF("restore memmap\n"); - RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg); + RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); ErrorF("restore common\n"); - RADEONRestoreCommonRegisters(pScrn, &info->ModeReg); + RADEONRestoreCommonRegisters(pScrn, info->ModeReg); switch (radeon_crtc->crtc_id) { case 0: ErrorF("restore crtc1\n"); - RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg); + RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); ErrorF("restore pll1\n"); - RADEONRestorePLLRegisters(pScrn, &info->ModeReg); + RADEONRestorePLLRegisters(pScrn, info->ModeReg); break; case 1: ErrorF("restore crtc2\n"); - RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg); + RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); ErrorF("restore pll2\n"); - RADEONRestorePLL2Registers(pScrn, &info->ModeReg); + RADEONRestorePLL2Registers(pScrn, info->ModeReg); break; } /* pixclks_cntl handles tv-out clock routing */ if (update_tv_routing) - radeon_update_tv_routing(pScrn, &info->ModeReg); + radeon_update_tv_routing(pScrn, info->ModeReg); if (info->DispPriority) RADEONInitDispBandwidth(pScrn); diff --git a/src/radeon_display.c b/src/radeon_display.c index 5c4fbfa..f678dda 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -689,7 +689,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b critical_point = 0x10; } - temp = info->SavedReg.grph_buffer_cntl; + temp = info->SavedReg->grph_buffer_cntl; temp &= ~(RADEON_GRPH_STOP_REQ_MASK); temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); temp &= ~(RADEON_GRPH_START_REQ_MASK); @@ -711,7 +711,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph_buffer_cntl, + (unsigned int)info->SavedReg->grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)); if (mode2) { @@ -719,7 +719,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b if (stop_req > max_stop_req) stop_req = max_stop_req; - temp = info->SavedReg.grph2_buffer_cntl; + temp = info->SavedReg->grph2_buffer_cntl; temp &= ~(RADEON_GRPH_STOP_REQ_MASK); temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); temp &= ~(RADEON_GRPH_START_REQ_MASK); @@ -761,7 +761,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH2_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph2_buffer_cntl, + (unsigned int)info->SavedReg->grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL)); } } diff --git a/src/radeon_dri.c b/src/radeon_dri.c index 7136e4e..dbfa8d9 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1197,7 +1197,7 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) info->irq = 0; } else { unsigned char *RADEONMMIO = info->MMIO; - info->ModeReg.gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); + info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); } } @@ -1774,7 +1774,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) RADEONDRISetVBlankInterrupt (pScrn, FALSE); drmCtlUninstHandler(info->drmFD); info->irq = 0; - info->ModeReg.gen_int_cntl = 0; + info->ModeReg->gen_int_cntl = 0; } /* De-allocate vertex buffers */ diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 3422b66..f01c9aa 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -2370,6 +2370,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) void *int10_save = NULL; const char *s; int crtc_max_X, crtc_max_Y; + RADEONEntPtr pRADEONEnt; + DevUnion* pPriv; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONPreInit\n"); @@ -2383,6 +2385,13 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); if (info->pEnt->location.type != BUS_PCI) goto fail; + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + getRADEONEntityIndex()); + pRADEONEnt = pPriv->ptr; + + info->SavedReg = &pRADEONEnt->SavedReg; + info->ModeReg = &pRADEONEnt->ModeReg; + info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), PCI_DEV_DEV(info->PciInfo), @@ -3469,7 +3478,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, * our local image to make sure we restore them properly on mode * changes or VT switches */ - RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); + RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) { /* we need to re-calculate bandwidth because of AGPMode difference. */ @@ -4801,7 +4810,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) } /* Update surface images */ - RADEONSaveSurfaces(pScrn, &info->ModeReg); + RADEONSaveSurfaces(pScrn, info->ModeReg); } /* Read memory map */ @@ -5129,7 +5138,7 @@ static void RADEONSave(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = &info->SavedReg; + RADEONSavePtr save = info->SavedReg; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONSave\n"); @@ -5181,7 +5190,7 @@ void RADEONRestore(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr restore = &info->SavedReg; + RADEONSavePtr restore = info->SavedReg; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); xf86CrtcPtr crtc; @@ -5585,7 +5594,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) } - RADEONRestoreSurfaces(pScrn, &info->ModeReg); + RADEONRestoreSurfaces(pScrn, info->ModeReg); #ifdef XF86DRI if (info->directRenderingEnabled) { if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) @@ -5597,7 +5606,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) /* get the DRI back into shape after resume */ RADEONDRISetVBlankInterrupt (pScrn, TRUE); RADEONDRIResume(pScrn->pScreen); - RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); + RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); } #endif diff --git a/src/radeon_output.c b/src/radeon_output.c index 11a2a8a..ecff799 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -837,7 +837,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; int i; - CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff; + CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; for (i=0; i<4; i++) { if (radeon_output->tmds_pll[i].freq == 0) break; @@ -851,12 +851,12 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, if (tmp & 0xfff00000) save->tmds_pll_cntl = tmp; else { - save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl & 0xfff00000; + save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000; save->tmds_pll_cntl |= tmp; } } else save->tmds_pll_cntl = tmp; - save->tmds_transmitter_cntl = info->SavedReg.tmds_transmitter_cntl & + save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl & ~(RADEON_TMDS_TRANSMITTER_PLLRST); if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2) @@ -864,7 +864,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, else /* weird, RV chips got this bit reversed? */ save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); - save->fp_gen_cntl = info->SavedReg.fp_gen_cntl | + save->fp_gen_cntl = info->SavedReg->fp_gen_cntl | (RADEON_FP_CRTC_DONT_SHADOW_VPAR | RADEON_FP_CRTC_DONT_SHADOW_HEND ); @@ -903,10 +903,10 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, if (pScrn->rgbBits == 8) - save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl | + save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl | RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ else - save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & + save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | @@ -948,12 +948,12 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); - save->lvds_pll_cntl = (info->SavedReg.lvds_pll_cntl | + save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl | RADEON_LVDS_PLL_EN); save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; - save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; + save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl; save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); @@ -985,9 +985,9 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, int yres = mode->VDisplay; float Hratio, Vratio; - save->fp_vert_stretch = info->SavedReg.fp_vert_stretch & + save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & RADEON_VERT_STRETCH_RESERVED; - save->fp_horz_stretch = info->SavedReg.fp_horz_stretch & + save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & (RADEON_HORZ_FP_LOOP_STRETCH | RADEON_HORZ_AUTO_RATIO_INC); @@ -1036,25 +1036,25 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, if (IsPrimary) { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg.disp_output_cntl & + save->disp_output_cntl = info->SavedReg->disp_output_cntl & ~RADEON_DISP_DAC_SOURCE_MASK; } else { - save->dac2_cntl = info->SavedReg.dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); + save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); } } else { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg.disp_output_cntl & + save->disp_output_cntl = info->SavedReg->disp_output_cntl & ~RADEON_DISP_DAC_SOURCE_MASK; save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; } else { - save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; + save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; } } save->dac_cntl = (RADEON_DAC_MASK_ALL | RADEON_DAC_VGA_ADR_EN | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN)); - save->dac_macro_cntl = info->SavedReg.dac_macro_cntl; + save->dac_macro_cntl = info->SavedReg->dac_macro_cntl; } static void @@ -1066,7 +1066,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { - save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & + save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & ~(RADEON_TV_DAC_STD_MASK | RADEON_TV_DAC_BGADJ_MASK | R420_TV_DAC_DACADJ_MASK | @@ -1075,7 +1075,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) R420_TV_DAC_GDACPD | R420_TV_DAC_TVENABLE); } else { - save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & + save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & ~(RADEON_TV_DAC_STD_MASK | RADEON_TV_DAC_BGADJ_MASK | RADEON_TV_DAC_DACADJ_MASK | @@ -1101,34 +1101,34 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, RADEONInitTvDacCntl(output, save); if (IS_R300_VARIANT) - save->gpiopad_a = info->SavedReg.gpiopad_a | 1; + save->gpiopad_a = info->SavedReg->gpiopad_a | 1; - save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; + save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; if (IsPrimary) { if (IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg.disp_output_cntl & + save->disp_output_cntl = info->SavedReg->disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; } else if (info->ChipFamily == CHIP_FAMILY_R200) { - save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & + save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & ~(R200_FP2_SOURCE_SEL_MASK | RADEON_FP2_DVO_RATE_SEL_SDR); } else { - save->disp_hw_debug = info->SavedReg.disp_hw_debug | RADEON_CRT2_DISP1_SEL; + save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL; } } else { if (IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg.disp_output_cntl & + save->disp_output_cntl = info->SavedReg->disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; } else if (info->ChipFamily == CHIP_FAMILY_R200) { - save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & + save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & ~(R200_FP2_SOURCE_SEL_MASK | RADEON_FP2_DVO_RATE_SEL_SDR); save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; } else { - save->disp_hw_debug = info->SavedReg.disp_hw_debug & + save->disp_hw_debug = info->SavedReg->disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; } } @@ -1175,35 +1175,35 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, xf86CrtcPtr crtc = output->crtc; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); + RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); if (radeon_crtc->crtc_id == 0) - RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); + RADEONRestoreRMXRegisters(pScrn, info->ModeReg); switch(radeon_output->MonType) { case MT_LCD: ErrorF("restore LVDS\n"); - RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg); + RADEONRestoreLVDSRegisters(pScrn, info->ModeReg); break; case MT_DFP: if (radeon_output->TMDSType == TMDS_INT) { ErrorF("restore FP\n"); - RADEONRestoreFPRegisters(pScrn, &info->ModeReg); + RADEONRestoreFPRegisters(pScrn, info->ModeReg); } else { ErrorF("restore FP2\n"); RADEONRestoreDVOChip(pScrn, output); - RADEONRestoreFP2Registers(pScrn, &info->ModeReg); + RADEONRestoreFP2Registers(pScrn, info->ModeReg); } break; case MT_STV: case MT_CTV: ErrorF("restore tv\n"); - RADEONRestoreDACRegisters(pScrn, &info->ModeReg); - RADEONRestoreTVRegisters(pScrn, &info->ModeReg); + RADEONRestoreDACRegisters(pScrn, info->ModeReg); + RADEONRestoreTVRegisters(pScrn, info->ModeReg); break; default: ErrorF("restore dac\n"); - RADEONRestoreDACRegisters(pScrn, &info->ModeReg); + RADEONRestoreDACRegisters(pScrn, info->ModeReg); } } @@ -1781,7 +1781,7 @@ radeon_create_resources(xf86OutputPtr output) "RRConfigureOutputProperty error, %d\n", err); } /* Set the current value of the backlight property */ - //data = (info->SavedReg.lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; + //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; data = RADEON_MAX_BACKLIGHT_LEVEL; err = RRChangeOutputProperty(output->randr_output, backlight_atom, XA_INTEGER, 32, PropModeReplace, 1, &data, diff --git a/src/radeon_probe.h b/src/radeon_probe.h index 66ece94..cdefdf5 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -223,6 +223,177 @@ typedef struct _RADEONOutputPrivateRec { int load_detection; } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; + +/* + * Maximum length of horizontal/vertical code timing tables for state storage + */ +#define MAX_H_CODE_TIMING_LEN 32 +#define MAX_V_CODE_TIMING_LEN 32 + +typedef struct { + /* Common registers */ + CARD32 ovr_clr; + CARD32 ovr_wid_left_right; + CARD32 ovr_wid_top_bottom; + CARD32 ov0_scale_cntl; + CARD32 mpp_tb_config; + CARD32 mpp_gp_config; + CARD32 subpic_cntl; + CARD32 viph_control; + CARD32 i2c_cntl_1; + CARD32 gen_int_cntl; + CARD32 cap0_trig_cntl; + CARD32 cap1_trig_cntl; + CARD32 bus_cntl; + CARD32 bios_4_scratch; + CARD32 bios_5_scratch; + CARD32 bios_6_scratch; + CARD32 surface_cntl; + CARD32 surfaces[8][3]; + CARD32 mc_agp_location; + CARD32 mc_fb_location; + CARD32 display_base_addr; + CARD32 display2_base_addr; + CARD32 ov0_base_addr; + + /* Other registers to save for VT switches */ + CARD32 dp_datatype; + CARD32 rbbm_soft_reset; + CARD32 clock_cntl_index; + CARD32 amcgpio_en_reg; + CARD32 amcgpio_mask; + + /* CRTC registers */ + CARD32 crtc_gen_cntl; + CARD32 crtc_ext_cntl; + CARD32 dac_cntl; + CARD32 crtc_h_total_disp; + CARD32 crtc_h_sync_strt_wid; + CARD32 crtc_v_total_disp; + CARD32 crtc_v_sync_strt_wid; + CARD32 crtc_offset; + CARD32 crtc_offset_cntl; + CARD32 crtc_pitch; + CARD32 disp_merge_cntl; + CARD32 grph_buffer_cntl; + CARD32 crtc_more_cntl; + CARD32 crtc_tile_x0_y0; + + /* CRTC2 registers */ + CARD32 crtc2_gen_cntl; + CARD32 dac_macro_cntl; + CARD32 dac2_cntl; + CARD32 disp_output_cntl; + CARD32 disp_tv_out_cntl; + CARD32 disp_hw_debug; + CARD32 disp2_merge_cntl; + CARD32 grph2_buffer_cntl; + CARD32 crtc2_h_total_disp; + CARD32 crtc2_h_sync_strt_wid; + CARD32 crtc2_v_total_disp; + CARD32 crtc2_v_sync_strt_wid; + CARD32 crtc2_offset; + CARD32 crtc2_offset_cntl; + CARD32 crtc2_pitch; + CARD32 crtc2_tile_x0_y0; + + /* Flat panel registers */ + CARD32 fp_crtc_h_total_disp; + CARD32 fp_crtc_v_total_disp; + CARD32 fp_gen_cntl; + CARD32 fp2_gen_cntl; + CARD32 fp_h_sync_strt_wid; + CARD32 fp_h2_sync_strt_wid; + CARD32 fp_horz_stretch; + CARD32 fp_panel_cntl; + CARD32 fp_v_sync_strt_wid; + CARD32 fp_v2_sync_strt_wid; + CARD32 fp_vert_stretch; + CARD32 lvds_gen_cntl; + CARD32 lvds_pll_cntl; + CARD32 tmds_pll_cntl; + CARD32 tmds_transmitter_cntl; + + /* Computed values for PLL */ + CARD32 dot_clock_freq; + CARD32 pll_output_freq; + int feedback_div; + int post_div; + + /* PLL registers */ + unsigned ppll_ref_div; + unsigned ppll_div_3; + CARD32 htotal_cntl; + CARD32 vclk_ecp_cntl; + + /* Computed values for PLL2 */ + CARD32 dot_clock_freq_2; + CARD32 pll_output_freq_2; + int feedback_div_2; + int post_div_2; + + /* PLL2 registers */ + CARD32 p2pll_ref_div; + CARD32 p2pll_div_0; + CARD32 htotal_cntl2; + CARD32 pixclks_cntl; + + /* Pallet */ + Bool palette_valid; + CARD32 palette[256]; + CARD32 palette2[256]; + + CARD32 rs480_unk_e30; + CARD32 rs480_unk_e34; + CARD32 rs480_unk_e38; + CARD32 rs480_unk_e3c; + + /* TV out registers */ + CARD32 tv_master_cntl; + CARD32 tv_htotal; + CARD32 tv_hsize; + CARD32 tv_hdisp; + CARD32 tv_hstart; + CARD32 tv_vtotal; + CARD32 tv_vdisp; + CARD32 tv_timing_cntl; + CARD32 tv_vscaler_cntl1; + CARD32 tv_vscaler_cntl2; + CARD32 tv_sync_size; + CARD32 tv_vrestart; + CARD32 tv_hrestart; + CARD32 tv_frestart; + CARD32 tv_ftotal; + CARD32 tv_clock_sel_cntl; + CARD32 tv_clkout_cntl; + CARD32 tv_data_delay_a; + CARD32 tv_data_delay_b; + CARD32 tv_dac_cntl; + CARD32 tv_pll_cntl; + CARD32 tv_pll_cntl1; + CARD32 tv_pll_fine_cntl; + CARD32 tv_modulator_cntl1; + CARD32 tv_modulator_cntl2; + CARD32 tv_frame_lock_cntl; + CARD32 tv_pre_dac_mux_cntl; + CARD32 tv_rgb_cntl; + CARD32 tv_y_saw_tooth_cntl; + CARD32 tv_y_rise_cntl; + CARD32 tv_y_fall_cntl; + CARD32 tv_uv_adr; + CARD32 tv_upsamp_and_gain_cntl; + CARD32 tv_gain_limit_settings; + CARD32 tv_linear_gain_settings; + CARD32 tv_crc_cntl; + CARD32 tv_sync_cntl; + CARD32 gpiopad_a; + CARD32 pll_test_cntl; + + CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; + CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; + +} RADEONSaveRec, *RADEONSavePtr; + #define RADEON_MAX_CRTC 2 #define RADEON_MAX_BIOS_CONNECTOR 8 @@ -242,6 +413,9 @@ typedef struct xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; + RADEONSaveRec ModeReg; /* Current mode */ + RADEONSaveRec SavedReg; /* Original (text) mode */ + } RADEONEntRec, *RADEONEntPtr; /* radeon_probe.c */ diff --git a/src/radeon_tv.c b/src/radeon_tv.c index 2a8873c..5e9a9c8 100644 --- a/src/radeon_tv.c +++ b/src/radeon_tv.c @@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, save->dac_cntl &= ~RADEON_DAC_TVO_EN; if (IS_R300_VARIANT) - save->gpiopad_a = info->SavedReg.gpiopad_a & ~1; + save->gpiopad_a = info->SavedReg->gpiopad_a & ~1; if (IsPrimary) { save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; @@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; Bool reloadTable; - RADEONSavePtr restore = &info->ModeReg; + RADEONSavePtr restore = info->ModeReg; reloadTable = RADEONInitTVRestarts(output, restore, mode); diff --git a/src/radeon_tv.h b/src/radeon_tv.h index 5c8c8c9..c4b7838 100644 --- a/src/radeon_tv.h +++ b/src/radeon_tv.h @@ -3,11 +3,6 @@ * Federico Ulivi */ -/* - * Maximum length of horizontal/vertical code timing tables for state storage - */ -#define MAX_H_CODE_TIMING_LEN 32 -#define MAX_V_CODE_TIMING_LEN 32 /* * Limits of h/v positions (hPos & vPos) diff --git a/src/radeon_video.c b/src/radeon_video.c index 3f0209e..99b74eb 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) * for higher clocks, sure makes life nicer */ - dot_clock = info->ModeReg.dot_clock_freq; + dot_clock = info->ModeReg->dot_clock_freq; if (dot_clock < 17500) info->ecp_div = 0; @@ -2552,9 +2552,9 @@ RADEONDisplayVideo( /* Figure out which head we are on for dot clock */ if (radeon_crtc->crtc_id == 1) - dot_clock = info->ModeReg.dot_clock_freq_2; + dot_clock = info->ModeReg->dot_clock_freq_2; else - dot_clock = info->ModeReg.dot_clock_freq; + dot_clock = info->ModeReg->dot_clock_freq; if (dot_clock < 17500) ecp_div = 0; -- cgit v1.2.3 From 0dcd926d3092100854b3e362d6659d4950508aeb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 7 Dec 2007 14:45:04 +1000 Subject: radeon: bring back zaphod all is forgiven. You've whined, you've cried, you've nagged, and you're guilt trippin has made me do it... It actually wasn't as hard as I thought it would be. Still not perfect, couple of things to fix yet --- src/radeon.h | 6 +- src/radeon_crtc.c | 55 +++++++++-------- src/radeon_display.c | 7 ++- src/radeon_driver.c | 162 ++++++++++++++++++++++++++++++++++++++++----------- src/radeon_probe.c | 2 +- src/radeon_probe.h | 3 + 6 files changed, 173 insertions(+), 62 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index 529374e..5c3bf86 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -681,6 +681,10 @@ typedef struct { Rotation rotation; void (*PointerMoved)(int, int, int); CreateScreenResourcesProcPtr CreateScreenResources; + + + Bool IsSecondary; + Bool IsPrimary; } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ @@ -801,7 +805,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn); extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags); -extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn); +extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn); extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn); extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName, diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 718073c..f28bdf7 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -1203,40 +1203,45 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { .destroy = NULL, /* XXX */ }; -Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) +Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - if (pRADEONEnt->Controller[0]) - return TRUE; + if (mask & 1) { + if (pRADEONEnt->Controller[0]) + return TRUE; + + pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); + if (!pRADEONEnt->pCrtc[0]) + return FALSE; - pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[0]) - return FALSE; + pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); + if (!pRADEONEnt->Controller[0]) + return FALSE; - pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[0]) - return FALSE; + pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; + pRADEONEnt->Controller[0]->crtc_id = 0; - pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; - pRADEONEnt->Controller[0]->crtc_id = 0; - - if (!pRADEONEnt->HasCRTC2) - return TRUE; + } - pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[1]) - return FALSE; + if (mask & 2) { + if (!pRADEONEnt->HasCRTC2) + return TRUE; + + pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); + if (!pRADEONEnt->pCrtc[1]) + return FALSE; + + pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); + if (!pRADEONEnt->Controller[1]) + { + xfree(pRADEONEnt->Controller[0]); + return FALSE; + } - pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[1]) - { - xfree(pRADEONEnt->Controller[0]); - return FALSE; + pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; + pRADEONEnt->Controller[1]->crtc_id = 1; } - - pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; - pRADEONEnt->Controller[1]->crtc_id = 1; return TRUE; } diff --git a/src/radeon_display.c b/src/radeon_display.c index f678dda..07d633f 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -318,7 +318,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) { ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONSavePtr save = &info->ModeReg; + RADEONSavePtr save = info->ModeReg; unsigned char * RADEONMMIO = info->MMIO; unsigned long tmp; RADEONOutputPrivatePtr radeon_output; @@ -773,7 +773,10 @@ void RADEONInitDispBandwidth(ScrnInfoPtr pScrn) DisplayModePtr mode1, mode2; int pixel_bytes2 = 0; - mode1 = info->CurrentLayout.mode; + if (info->IsPrimary || info->IsSecondary) + mode1 = &xf86_config->crtc[0]->mode; + else + mode1 = info->CurrentLayout.mode; mode2 = NULL; pixel_bytes2 = info->CurrentLayout.pixel_bytes; diff --git a/src/radeon_driver.c b/src/radeon_driver.c index f01c9aa..6db1d96 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1446,6 +1446,21 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, from, "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); + if (info->IsPrimary) { + pScrn->videoRam /= 2; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for primary head\n", + pScrn->videoRam); + } + + if (info->IsSecondary) { + pScrn->videoRam /= 2; + info->LinearAddr += pScrn->videoRam * 1024; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for secondary head\n", + pScrn->videoRam); + } + pScrn->videoRam &= ~1023; info->FbMapSize = pScrn->videoRam * 1024; @@ -1881,6 +1896,18 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) info->pLibDRMVersion = NULL; info->pKernelDRMVersion = NULL; + if (xf86IsEntityShared(info->pEnt->index)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Direct Rendering Disabled -- " + "Dual-head configuration is not working with " + "DRI at present.\n" + "Please use the radeon MergedFB option if you " + "want Dual-head with DRI.\n"); + return FALSE; + } + if (info->IsSecondary) + return FALSE; + if (info->Chipset == PCI_CHIP_RN50_515E || info->Chipset == PCI_CHIP_RN50_5969 || info->Chipset == PCI_CHIP_RC410_5A61 || @@ -2311,12 +2338,41 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) #endif } +static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) +{ + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); + int i; + + if (info->IsPrimary) { + while(config->num_output > 1) { + xf86OutputDestroy(config->output[1]); + } + } else { + xf86OutputDestroy(config->output[0]); + while(config->num_output > 1) { + xf86OutputDestroy(config->output[1]); + } + } +} + static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) { xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); int i; + int mask; - if (!RADEONAllocateControllers(pScrn)) + if (!info->IsPrimary && !info->IsSecondary) + mask = 3; + else if (info->IsPrimary) + mask = 1; + else + mask = 2; + + if (!RADEONAllocateControllers(pScrn, mask)) return FALSE; RADEONGetClockInfo(pScrn); @@ -2324,6 +2380,11 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) if (!RADEONSetupConnectors(pScrn)) { return FALSE; } + + if (info->IsPrimary || info->IsSecondary) { + /* fixup outputs for zaphod */ + RADEONFixZaphodOutputs(pScrn); + } RADEONPrintPortMap(pScrn); @@ -2382,6 +2443,9 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info = RADEONPTR(pScrn); info->MMIO = NULL; + info->IsSecondary = FALSE; + info->IsPrimary = FALSE; + info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); if (info->pEnt->location.type != BUS_PCI) goto fail; @@ -2389,8 +2453,28 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) getRADEONEntityIndex()); pRADEONEnt = pPriv->ptr; - info->SavedReg = &pRADEONEnt->SavedReg; - info->ModeReg = &pRADEONEnt->ModeReg; + if(xf86IsEntityShared(pScrn->entityList[0])) + { + if(xf86IsPrimInitDone(pScrn->entityList[0])) + { + info->IsSecondary = TRUE; + pRADEONEnt->pSecondaryScrn = pScrn; + info->SavedReg = &pRADEONEnt->SavedReg; + info->ModeReg = &pRADEONEnt->ModeReg; + } + else + { + info->IsPrimary = TRUE; + xf86SetPrimInitDone(pScrn->entityList[0]); + pRADEONEnt->pPrimaryScrn = pScrn; + pRADEONEnt->HasSecondary = FALSE; + info->SavedReg = &pRADEONEnt->SavedReg; + info->ModeReg = &pRADEONEnt->ModeReg; + } + } else { + info->SavedReg = &pRADEONEnt->SavedReg; + info->ModeReg = &pRADEONEnt->ModeReg; + } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), @@ -2739,10 +2823,11 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, /* Make the change through RandR */ #ifdef RANDR_12_INTERFACE - RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); -#else - crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); + if (crtc->randr_crtc) + RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); + else #endif + crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); } } @@ -3153,15 +3238,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, char* s; #endif -#ifdef XF86DRI - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONScreenInit %lx %ld %d\n", - pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); -#else - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONScreenInit %lx %ld\n", - pScrn->memPhysBase, pScrn->fbOffset); -#endif info->accelOn = FALSE; #ifdef USE_XAA @@ -3171,6 +3247,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, pScrn->fbOffset = info->frontOffset; #endif + if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; +#ifdef XF86DRI + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONScreenInit %lx %ld %d\n", + pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); +#else + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit %lx %ld\n", + pScrn->memPhysBase, pScrn->fbOffset); +#endif if (!RADEONMapMem(pScrn)) return FALSE; #ifdef XF86DRI @@ -3621,6 +3707,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; int timeout; + if (info->IsSecondary) + return; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RADEONRestoreMemMapRegisters() : \n"); xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -3774,6 +3862,9 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) unsigned char *RADEONMMIO = info->MMIO; CARD32 fb, agp; + if (info->IsSecondary) + return; + fb = INREG(RADEON_MC_FB_LOCATION); agp = INREG(RADEON_MC_AGP_LOCATION); @@ -3832,6 +3923,9 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; + if (info->IsSecondary) + return; + OUTREG(RADEON_OVR_CLR, restore->ovr_clr); OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); @@ -5211,26 +5305,28 @@ void RADEONRestore(ScrnInfoPtr pScrn) OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); - RADEONRestoreMemMapRegisters(pScrn, restore); - RADEONRestoreCommonRegisters(pScrn, restore); + if (!info->IsSecondary) { + RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCommonRegisters(pScrn, restore); - if (pRADEONEnt->HasCRTC2) { - RADEONRestoreCrtc2Registers(pScrn, restore); - RADEONRestorePLL2Registers(pScrn, restore); - } + if (pRADEONEnt->HasCRTC2) { + RADEONRestoreCrtc2Registers(pScrn, restore); + RADEONRestorePLL2Registers(pScrn, restore); + } - RADEONRestoreBIOSRegisters(pScrn, restore); - RADEONRestoreCrtcRegisters(pScrn, restore); - RADEONRestorePLLRegisters(pScrn, restore); - RADEONRestoreRMXRegisters(pScrn, restore); - RADEONRestoreFPRegisters(pScrn, restore); - RADEONRestoreFP2Registers(pScrn, restore); - RADEONRestoreLVDSRegisters(pScrn, restore); + RADEONRestoreBIOSRegisters(pScrn, restore); + RADEONRestoreCrtcRegisters(pScrn, restore); + RADEONRestorePLLRegisters(pScrn, restore); + RADEONRestoreRMXRegisters(pScrn, restore); + RADEONRestoreFPRegisters(pScrn, restore); + RADEONRestoreFP2Registers(pScrn, restore); + RADEONRestoreLVDSRegisters(pScrn, restore); - if (info->InternalTVOut) - RADEONRestoreTVRegisters(pScrn, restore); + if (info->InternalTVOut) + RADEONRestoreTVRegisters(pScrn, restore); - RADEONRestoreSurfaces(pScrn, restore); + RADEONRestoreSurfaces(pScrn, restore); + } #if 1 /* Temp fix to "solve" VT switch problems. When switching VTs on @@ -5258,8 +5354,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) #endif /* need to make sure we don't enable a crtc by accident or we may get a hang */ - if (pRADEONEnt->HasCRTC2) { - if (info->crtc2_on) { + if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { + if (info->crtc2_on && xf86_config->num_crtc > 1) { crtc = xf86_config->crtc[1]; crtc->funcs->dpms(crtc, DPMSModeOn); } diff --git a/src/radeon_probe.c b/src/radeon_probe.c index baea47c..e0a77e6 100644 --- a/src/radeon_probe.c +++ b/src/radeon_probe.c @@ -175,7 +175,7 @@ RADEONProbe(DriverPtr drv, int flags) DevUnion *pPriv; RADEONEntPtr pRADEONEnt; - /*xf86SetEntitySharable(usedChips[i]);*/ + xf86SetEntitySharable(usedChips[i]); if (gRADEONEntityIndex == -1) gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); diff --git a/src/radeon_probe.h b/src/radeon_probe.h index cdefdf5..d1096fb 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -413,6 +413,9 @@ typedef struct xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; + ScrnInfoPtr pSecondaryScrn; + ScrnInfoPtr pPrimaryScrn; + RADEONSaveRec ModeReg; /* Current mode */ RADEONSaveRec SavedReg; /* Original (text) mode */ -- cgit v1.2.3 From 2ce8d192533a8c795714c5a9fb308ec74db40287 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 7 Dec 2007 15:35:21 +1000 Subject: don't add fboffset to info->FB it already is mapped at the offset --- src/radeon_cursor.c | 4 ++-- src/radeon_driver.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index b8cfffd..5004b64 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -189,7 +189,7 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); + CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset); int pixel, i; CURSOR_SWAPPING_DECL_MMIO @@ -231,7 +231,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); + CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset); RADEONCTRACE(("RADEONLoadCursorARGB\n")); diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 6db1d96..0632fd3 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -3474,7 +3474,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "Initializing fb layer\n"); /* Init fb layer */ - if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, + if (!fbScreenInit(pScreen, info->FB, pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -- cgit v1.2.3 From cc167b9bb7f1c3b8579e51e7bc2fca2f8eba6bd1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 7 Dec 2007 15:41:36 +1000 Subject: disable tiling for zaphod heads --- src/radeon_driver.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 0632fd3..35b9a47 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -2118,6 +2118,10 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) if (!info->allowColorTiling) return; + /* for zaphod disable tiling for now */ + if (info->IsPrimary || info->IsSecondary) + info->allowColorTiling = FALSE; + #ifdef XF86DRI if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor < 14) { -- cgit v1.2.3