From 1c7c3372776d6d116facabbf055f27af3e96f59f Mon Sep 17 00:00:00 2001
From: Alex Deucher <agd5f@yahoo.com>
Date: Fri, 1 Jul 2005 04:16:42 +0000
Subject: - fix depth tiling for r3/4xx chips (Aapo Tahkola) - adjust limits
 for tiled surfaces on r3/4xx

---
 src/radeon.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/radeon.h')

diff --git a/src/radeon.h b/src/radeon.h
index 593baf2..814db80 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -654,6 +654,9 @@ typedef struct {
 
     Bool               VGAAccess;
 
+    int                MaxSurfaceWidth;
+    int                MaxLines;
+
 } RADEONInfoRec, *RADEONInfoPtr;
 
 #define RADEONWaitForFifo(pScrn, entries)				\
-- 
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