From bb5ede557bf32a42eef158ff0fbcfe1c6ede098a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 7 Dec 2007 14:30:32 +1000 Subject: radeon: move savedreg/modereg into entity instead of info --- src/radeon_video.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/radeon_video.c') diff --git a/src/radeon_video.c b/src/radeon_video.c index 3f0209e..99b74eb 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) * for higher clocks, sure makes life nicer */ - dot_clock = info->ModeReg.dot_clock_freq; + dot_clock = info->ModeReg->dot_clock_freq; if (dot_clock < 17500) info->ecp_div = 0; @@ -2552,9 +2552,9 @@ RADEONDisplayVideo( /* Figure out which head we are on for dot clock */ if (radeon_crtc->crtc_id == 1) - dot_clock = info->ModeReg.dot_clock_freq_2; + dot_clock = info->ModeReg->dot_clock_freq_2; else - dot_clock = info->ModeReg.dot_clock_freq; + dot_clock = info->ModeReg->dot_clock_freq; if (dot_clock < 17500) ecp_div = 0; -- cgit v1.2.3 From f5e8c185001e62e744310667c2d1bd3fe6542a62 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 19 Dec 2007 10:38:58 +1000 Subject: more endian related fixage --- src/radeon_video.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/radeon_video.c') diff --git a/src/radeon_video.c b/src/radeon_video.c index 99b74eb..a84662e 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -2156,7 +2156,7 @@ RADEONCopyData( { #if X_BYTE_ORDER == X_BIG_ENDIAN unsigned char *RADEONMMIO = info->MMIO; - unsigned int swapper = info->ModeReg.surface_cntl & + unsigned int swapper = info->ModeReg->surface_cntl & ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); @@ -2182,7 +2182,7 @@ RADEONCopyData( #if X_BYTE_ORDER == X_BIG_ENDIAN /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); #endif } } @@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data( { #if X_BYTE_ORDER == X_BIG_ENDIAN unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl + OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl | RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); #endif @@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data( #if X_BYTE_ORDER == X_BIG_ENDIAN /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); #endif } } @@ -2333,7 +2333,7 @@ RADEONCopyMungedData( #if X_BYTE_ORDER == X_BIG_ENDIAN unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl + OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl | RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); #endif @@ -2371,7 +2371,7 @@ RADEONCopyMungedData( } #if X_BYTE_ORDER == X_BIG_ENDIAN /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); #endif } } -- cgit v1.2.3