From 5a6f74103f0ec0d451d0e2573442efe5922848af Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 20 Sep 2007 23:56:08 -0400 Subject: RADEON: fix video in on RV380 (tested on X600 VIVO) --- src/radeon_vip.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/radeon_vip.c') diff --git a/src/radeon_vip.c b/src/radeon_vip.c index abcba06..7ee4ab5 100644 --- a/src/radeon_vip.c +++ b/src/radeon_vip.c @@ -330,6 +330,13 @@ void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */ OUTREG(RADEON_VIPH_BM_CHUNK, 0x0); OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN)); + break; + case CHIP_FAMILY_RV380: + OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */ + OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); + OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */ + OUTREG(RADEON_VIPH_BM_CHUNK, 0x0); + OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN)); break; default: OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */ -- cgit v1.2.3