libpciaccess support.

10 files changed, 342 insertions, 118 deletions

diff --git a/src/g80_driver.c b/src/g80_driver.c
index 8a494b9..7223f56 100644
--- a/src/g80_driver.c
+++ b/src/g80_driver.c
@@ -188,8 +188,14 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
 {
     G80Ptr pNv;
     EntityInfoPtr pEnt;
+#if XSERVER_LIBPCIACCESS
+    struct pci_device *pPci;
+    int err;
+    void *p;
+#else
     pciVideoPtr pPci;
     PCITAG pcitag;
+#endif
     MessageType from;
     Bool primary;
     const rgb zeros = {0, 0, 0};
@@ -218,13 +224,22 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
     pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
     if(pEnt->location.type != BUS_PCI) goto fail;
     pPci = xf86GetPciInfoForEntity(pEnt->index);
-    pcitag = pciTag(pPci->bus, pPci->device, pPci->func);
+#if XSERVER_LIBPCIACCESS
+    /* Need this to unmap */
+    pNv->pPci = pPci;
+#endif
     primary = xf86IsPrimaryPci(pPci);
 
     /* The ROM size sometimes isn't read correctly, so fix it up here. */
+#if XSERVER_LIBPCIACCESS
+    if(pPci->rom_size == 0)
+        /* The BIOS is 64k */
+        pPci->rom_size = 64 * 1024;
+#else
     if(pPci->biosSize == 0)
         /* The BIOS is 64k */
         pPci->biosSize = 16;
+#endif
 
     pNv->int10 = NULL;
     pNv->int10Mode = 0;
@@ -324,16 +339,24 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
     if(!xf86SetGamma(pScrn, gzeros)) goto fail;
 
     /* Map memory */
-    xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MMIO registers at 0x%lx\n",
-               pPci->memBase[0]);
-    xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Linear framebuffer at 0x%lx\n",
-               pPci->memBase[1]);
-    pScrn->memPhysBase = pPci->memBase[1];
+    pScrn->memPhysBase = MEMBASE(pPci, 1);
     pScrn->fbOffset = 0;
 
+#if XSERVER_LIBPCIACCESS
+    err = pci_device_map_range(pPci, pPci->regions[0].base_addr, G80_REG_SIZE,
+                               PCI_DEV_MAP_FLAG_WRITABLE, &p);
+    if(err) {
+        xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+                   "Failed to map MMIO registers: %s\n", strerror(err));
+        goto fail;
+    }
+    pNv->reg = p;
+#else
+    pcitag = pciTag(pPci->bus, pPci->device, pPci->func);
     pNv->reg = xf86MapPciMem(pScrn->scrnIndex,
                              VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
                              pcitag, pPci->memBase[0], G80_REG_SIZE);
+#endif
     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MMIO registers mapped at %p\n",
                (void*)pNv->reg);
 
@@ -349,7 +372,11 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
 
     /* Determine the size of BAR1 */
     /* Some configs have BAR1 < total RAM < 256 MB */
+#if XSERVER_LIBPCIACCESS
+    BAR1sizeKB = pPci->regions[1].size / 1024;
+#else
     BAR1sizeKB = 1UL << (pPci->size[1] - 10);
+#endif
     if(BAR1sizeKB > 256 * 1024) {
         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "BAR1 is > 256 MB, which is "
                    "probably wrong.  Clamping to 256 MB.\n");
@@ -375,9 +402,23 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
     xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "  Mapped memory: %.1f MB\n",
                pScrn->videoRam / 1024.0);
 
+#if XSERVER_LIBPCIACCESS
+    err = pci_device_map_range(pPci, pPci->regions[1].base_addr,
+                               pScrn->videoRam * 1024,
+                               PCI_DEV_MAP_FLAG_WRITABLE |
+                               PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+                               &p);
+    if(err) {
+        xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+                   "Failed to map framebuffer: %s\n", strerror(err));
+        goto fail;
+    }
+    pNv->mem = p;
+#else
     pNv->mem = xf86MapPciMem(pScrn->scrnIndex,
                              VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
                              pcitag, pPci->memBase[1], pScrn->videoRam * 1024);
+#endif
     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Linear framebuffer mapped at %p\n",
                (void*)pNv->mem);
 
@@ -520,8 +561,13 @@ G80CloseScreen(int scrnIndex, ScreenPtr pScreen)
 
     if(xf86ServerIsExiting()) {
         if(pNv->int10) xf86FreeInt10(pNv->int10);
+#if XSERVER_LIBPCIACCESS
+        pci_device_unmap_range(pNv->pPci, pNv->mem, pNv->videoRam * 1024);
+        pci_device_unmap_range(pNv->pPci, (void*)pNv->reg, G80_REG_SIZE);
+#else
         xf86UnMapVidMem(pScrn->scrnIndex, pNv->mem, pNv->videoRam * 1024);
         xf86UnMapVidMem(pScrn->scrnIndex, (void*)pNv->reg, G80_REG_SIZE);
+#endif
         pNv->reg = NULL;
         pNv->mem = NULL;
     }
diff --git a/src/g80_type.h b/src/g80_type.h
index ecaedaa..41f170b 100644
--- a/src/g80_type.h
+++ b/src/g80_type.h
@@ -36,6 +36,9 @@ typedef enum AccelMethod {
 } AccelMethod;
 
 typedef struct G80Rec {
+#if XSERVER_LIBPCIACCESS
+    struct pci_device  *pPci;
+#endif
     volatile CARD32 *   reg;
     unsigned char *     mem;
 
diff --git a/src/nv_const.h b/src/nv_const.h
index b1285ba..141e0f3 100644
--- a/src/nv_const.h
+++ b/src/nv_const.h
@@ -5,4 +5,17 @@
 #define NV_NAME "NV"
 #define NV_DRIVER_NAME "nv"
 
+/* libpciaccess gratuitous API changes */
+#if XSERVER_LIBPCIACCESS
+ #define MEMBASE(p,n)     (p)->regions[n].base_addr
+ #define VENDOR_ID(p)     (p)->vendor_id
+ #define DEVICE_ID(p)     (p)->device_id
+ #define CHIP_REVISION(p) (p)->revision
+#else
+ #define MEMBASE(p,n)     (p)->memBase[n]
+ #define VENDOR_ID(p)     (p)->vendor
+ #define DEVICE_ID(p)     (p)->chipType
+ #define CHIP_REVISION(p) (p)->chipRev
+#endif
+
 #endif /* __NV_CONST_H__ */
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 07ca621..f925aed 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -42,7 +42,11 @@ Bool    G80GetScrnInfoRec(PciChipsets *chips, int chip);
 /* Mandatory functions */
 static const OptionInfoRec * NVAvailableOptions(int chipid, int busid);
 static void    NVIdentify(int flags);
+#if XSERVER_LIBPCIACCESS
+static Bool    NVPciProbe(DriverPtr, int entity, struct pci_device*, intptr_t data);
+#else
 static Bool    NVProbe(DriverPtr drv, int flags);
+#endif
 static Bool    NVPreInit(ScrnInfoPtr pScrn, int flags);
 static Bool    NVScreenInit(int Index, ScreenPtr pScreen, int argc,
                             char **argv);
@@ -72,6 +76,15 @@ static void	NVRestore(ScrnInfoPtr pScrn);
 static Bool	NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
 static Bool	NVSetModeVBE(ScrnInfoPtr pScrn, DisplayModePtr pMode);
 
+#if XSERVER_LIBPCIACCESS
+/* For now, just match any NVIDIA PCI device and sort through them in the probe
+ * routine */
+static const struct pci_id_match NVPciIdMatchList[] = {
+    { PCI_VENDOR_NVIDIA, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0 },
+    { PCI_VENDOR_NVIDIA_SGS, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0},
+    { 0, 0, 0 }
+};
+#endif
 
 /*
  * This contains the functions needed by the server after loading the
@@ -85,10 +98,19 @@ _X_EXPORT DriverRec NV = {
         NV_VERSION,
 	NV_DRIVER_NAME,
         NVIdentify,
+#if XSERVER_PCIACCESS
         NVProbe,
+#else
+        NULL,
+#endif
 	NVAvailableOptions,
         NULL,
-        0
+        0,
+        NULL,
+#if XSERVER_LIBPCIACCESS
+        NVPciIdMatchList,
+        NVPciProbe,
+#endif
 };
 
 /* Known cards as of 2007/07/24 */
@@ -574,7 +596,13 @@ nvSetup(pointer module, pointer opts, int *errmaj, int *errmin)
 
     if (!setupDone) {
         setupDone = TRUE;
-        xf86AddDriver(&NV, module, 0);
+        xf86AddDriver(&NV, module,
+#if XSERVER_LIBPCIACCESS
+            HaveDriverFuncs
+#else
+            0
+#endif
+        );
 
         /*
          * Modules that this driver always requires may be loaded here
@@ -637,7 +665,9 @@ NVGetScrnInfoRec(PciChipsets *chips, int chip)
     pScrn->driverName       = NV_DRIVER_NAME;
     pScrn->name             = NV_NAME;
 
+#if !XSERVER_LIBPCIACCESS
     pScrn->Probe            = NVProbe;
+#endif
     pScrn->PreInit          = NVPreInit;
     pScrn->ScreenInit       = NVScreenInit;
     pScrn->SwitchMode       = NVSwitchMode;
@@ -654,9 +684,29 @@ NVGetScrnInfoRec(PciChipsets *chips, int chip)
 
 
 static CARD32 
+#if XSERVER_LIBPCIACCESS
+NVGetPCIXpressChip (struct pci_device *dev)
+#else
 NVGetPCIXpressChip (pciVideoPtr pVideo)
+#endif
 {
     volatile CARD32 *regs;
+#if XSERVER_LIBPCIACCESS
+    uint32_t pciid, pcicmd;
+    void *tmp;
+
+    pci_device_cfg_read_u32(dev, &pcicmd, PCI_CMD_STAT_REG);
+    pci_device_cfg_write_u32(dev, pcicmd | PCI_CMD_MEM_ENABLE,
+                             PCI_CMD_STAT_REG);
+
+    pci_device_map_range(dev, dev->regions[0].base_addr, 0x2000,
+                         PCI_DEV_MAP_FLAG_WRITABLE, &tmp);
+    regs = tmp;
+    pciid = regs[0x1800/4];
+    pci_device_unmap_range(dev, tmp, 0x2000);
+
+    pci_device_cfg_write_u32(dev, pcicmd, PCI_CMD_STAT_REG);
+#else
     CARD32 pciid, pcicmd;
     PCITAG Tag = ((pciConfigPtr)(pVideo->thisCard))->tag;
 
@@ -670,6 +720,7 @@ NVGetPCIXpressChip (pciVideoPtr pVideo)
     xf86UnMapVidMem(-1, (pointer)regs, 0x2000);
 
     pciWriteLong(Tag, PCI_CMD_STAT_REG, pcicmd);
+#endif
 
     if((pciid & 0x0000ffff) == 0x000010DE) 
        pciid = 0x10DE0000 | (pciid >> 16);
@@ -694,7 +745,82 @@ NVIsG80(int chipType)
     return FALSE;
 }
 
+static Bool
+NVIsSupported(CARD32 id)
+{
+    /* look for a compatible devices which may be newer than
+       the NVKnownChipsets list above.  */
+    switch(id & 0xfff0) {
+    case 0x0170:
+    case 0x0180:
+    case 0x0250:
+    case 0x0280:
+    case 0x0300:
+    case 0x0310:
+    case 0x0320:
+    case 0x0330:
+    case 0x0340:
+    case 0x0040:
+    case 0x00C0:
+    case 0x0120:
+    case 0x0140:
+    case 0x0160:
+    case 0x01D0:
+    case 0x0090:
+    case 0x0210:
+    case 0x0220:
+    case 0x0240:
+    case 0x0290:
+    case 0x0390:
+    case 0x03D0:
+        return TRUE;
+    }
+
+    return FALSE;
+}
+
 /* Mandatory */
+#if XSERVER_LIBPCIACCESS
+static Bool
+NVPciProbe(DriverPtr drv, int entity, struct pci_device *dev, intptr_t data)
+{
+    const CARD32 id = ((dev->device_id & 0xfff0) == 0x00F0 ||
+                       (dev->device_id & 0xfff0) == 0x02E0) ?
+                      NVGetPCIXpressChip(dev) : dev->vendor_id << 16 | dev->device_id;
+    const char *name = xf86TokenToString(NVKnownChipsets, id);
+
+    if(dev->vendor_id == PCI_VENDOR_NVIDIA && !name &&
+       !NVIsSupported(id) && !NVIsG80(id)) {
+        /* See if pci.ids knows what the heck this thing is */
+        name = pci_device_get_device_name(dev);
+        if(name)
+            xf86DrvMsg(0, X_WARNING,
+                       NV_NAME ": Ignoring unsupported device 0x%x (%s) at %2.2x@%2.2x:%2.2x:%1.1x\n",
+                       id, name, dev->bus, dev->domain, dev->dev, dev->func);
+        else
+            xf86DrvMsg(0, X_WARNING,
+                       NV_NAME ": Ignoring unsupported device 0x%x at %2.2x@%2.2x:%2.2x:%1.1x\n",
+                       id, dev->bus, dev->domain, dev->dev, dev->func);
+        return FALSE;
+    }
+
+    if(!name)
+        name = pci_device_get_device_name(dev);
+    if(!name)
+        name = "Unknown GPU";
+
+    xf86DrvMsg(0, X_PROBED,
+               NV_NAME ": Found NVIDIA %s at %2.2x@%2.2x:%2.2x:%1.1x\n",
+               name, dev->bus, dev->domain, dev->dev, dev->func);
+
+    if(NVIsG80(dev->device_id))
+        return G80GetScrnInfoRec(NULL, entity);
+    else if(dev->vendor_id == PCI_VENDOR_NVIDIA_SGS)
+        return RivaGetScrnInfoRec(NULL, entity);
+    else
+        return NVGetScrnInfoRec(NULL, entity);
+}
+#else
 static Bool
 NVProbe(DriverPtr drv, int flags)
 {
@@ -738,57 +864,15 @@ NVProbe(DriverPtr drv, int flags)
                nvchips++;
             }
 
-            if(nvchips->name) { /* found one */
+            if(nvchips->name ||
+               ((*ppPci)->vendor == PCI_VENDOR_NVIDIA &&
+                (NVIsSupported(token) || NVIsG80((*ppPci)->chipType)))) {
                NVChipsets[numUsed].token = pciid;
-               NVChipsets[numUsed].name = nvchips->name;
-               NVPciChipsets[numUsed].numChipset = pciid; 
+               NVChipsets[numUsed].name = nvchips->name ? nvchips->name : "Unknown NVIDIA chip";
+               NVPciChipsets[numUsed].numChipset = pciid;
                NVPciChipsets[numUsed].PCIid = pciid;
                NVPciChipsets[numUsed].resList = RES_SHARED_VGA;
                numUsed++;
-            } else if ((*ppPci)->vendor == PCI_VENDOR_NVIDIA) {
-               Bool canHandle = FALSE;
-
-               /* look for a compatible devices which may be newer than 
-                  the NVKnownChipsets list above.  */
-               switch(token & 0xfff0) {
-               case 0x0170:   
-               case 0x0180:
-               case 0x0250:
-               case 0x0280:
-               case 0x0300:
-               case 0x0310:
-               case 0x0320:
-               case 0x0330:
-               case 0x0340:
-               case 0x0040:
-               case 0x00C0:
-               case 0x0120:
-               case 0x0140:
-               case 0x0160:
-               case 0x01D0:
-               case 0x0090:
-               case 0x0210:
-               case 0x0220:
-               case 0x0240:
-               case 0x0290:
-               case 0x0390:
-               case 0x03D0:
-                   canHandle = TRUE;
-                   break;
-               default:  break;  /* we don't recognize it */
-               }
-
-               if(NVIsG80((*ppPci)->chipType))
-                   canHandle = TRUE;
-
-               if(canHandle) {
-                   NVChipsets[numUsed].token = pciid;
-                   NVChipsets[numUsed].name = "Unknown NVIDIA chip";
-                   NVPciChipsets[numUsed].numChipset = pciid;
-                   NVPciChipsets[numUsed].PCIid = pciid;
-                   NVPciChipsets[numUsed].resList = RES_SHARED_VGA;
-                   numUsed++;
-               }
             }
         }
         ppPci++;
@@ -831,6 +915,7 @@ NVProbe(DriverPtr drv, int flags)
 
     return foundScreen;
 }
+#endif /* XSERVER_LIBPCIACCESS */
 
 /* Usually mandatory */
 Bool
@@ -1175,8 +1260,10 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
  
     /* Find the PCI info for this screen */
     pNv->PciInfo = xf86GetPciInfoForEntity(pNv->pEnt->index);
+#if !XSERVER_LIBPCIACCESS
     pNv->PciTag = pciTag(pNv->PciInfo->bus, pNv->PciInfo->device,
 			  pNv->PciInfo->func);
+#endif
 
     pNv->Primary = xf86IsPrimaryPci(pNv->PciInfo);
 
@@ -1212,7 +1299,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
 		   pNv->Chipset);
     } else {
 	from = X_PROBED;
-	pNv->Chipset = (pNv->PciInfo->vendor << 16) | pNv->PciInfo->chipType;
+	pNv->Chipset = VENDOR_ID(pNv->PciInfo) << 16 | DEVICE_ID(pNv->PciInfo);
 
         if(((pNv->Chipset & 0xfff0) == 0x00F0) ||
            ((pNv->Chipset & 0xfff0) == 0x02E0))
@@ -1231,7 +1318,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
 	xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
 		   pNv->ChipRev);
     } else {
-	pNv->ChipRev = pNv->PciInfo->chipRev;
+	pNv->ChipRev = CHIP_REVISION(pNv->PciInfo);
     }
 
     /*
@@ -1530,8 +1617,8 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
 	pNv->FbAddress = pNv->pEnt->device->MemBase;
 	from = X_CONFIG;
     } else {
-	if (pNv->PciInfo->memBase[1] != 0) {
-	    pNv->FbAddress = pNv->PciInfo->memBase[1] & 0xff800000;
+	if (MEMBASE(pNv->PciInfo, 1) != 0) {
+	    pNv->FbAddress = MEMBASE(pNv->PciInfo, 1) & 0xff800000;
 	    from = X_PROBED;
 	} else {
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -1557,8 +1644,8 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
 	pNv->IOAddress = pNv->pEnt->device->IOBase;
 	from = X_CONFIG;
     } else {
-	if (pNv->PciInfo->memBase[0] != 0) {
-	    pNv->IOAddress = pNv->PciInfo->memBase[0] & 0xffffc000;
+	if (MEMBASE(pNv->PciInfo, 0) != 0) {
+	    pNv->IOAddress = MEMBASE(pNv->PciInfo, 0) & 0xffffc000;
 	    from = X_PROBED;
 	} else {
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -1882,13 +1969,20 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
 static Bool
 NVMapMem(ScrnInfoPtr pScrn)
 {
-    NVPtr pNv;
-        
-    pNv = NVPTR(pScrn);
+    NVPtr pNv = NVPTR(pScrn);
+
+#if XSERVER_LIBPCIACCESS
+    void *tmp;
 
+    pci_device_map_range(pNv->PciInfo, pNv->FbAddress, pNv->FbMapSize,
+                         PCI_DEV_MAP_FLAG_WRITABLE |
+                         PCI_DEV_MAP_FLAG_WRITE_COMBINE, &tmp);
+    pNv->FbBase = tmp;
+#else
     pNv->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
 				 pNv->PciTag, pNv->FbAddress,
 				 pNv->FbMapSize);
+#endif
     if (pNv->FbBase == NULL)
 	return FALSE;
 
@@ -1924,7 +2018,11 @@ NVUnmapMem(ScrnInfoPtr pScrn)
     
     pNv = NVPTR(pScrn);
 
+#if XSERVER_LIBPCIACCESS
+    pci_device_unmap_range(pNv->PciInfo, pNv->FbBase, pNv->FbMapSize);
+#else
     xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pNv->FbBase, pNv->FbMapSize);
+#endif
     pNv->FbBase = NULL;
     pNv->FbStart = NULL;
 
diff --git a/src/nv_hw.c b/src/nv_hw.c
index 9bc16f4..0e74e4d 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -677,6 +677,16 @@ static void nForceUpdateArbitrationSettings (
     NVPtr        pNv
 )
 {
+#if XSERVER_LIBPCIACCESS
+    struct pci_device *const dev1 = pci_device_find_by_slot(0, 0, 0, 1);
+    struct pci_device *const dev2 = pci_device_find_by_slot(0, 0, 0, 2);
+    struct pci_device *const dev3 = pci_device_find_by_slot(0, 0, 0, 3);
+    struct pci_device *const dev5 = pci_device_find_by_slot(0, 0, 0, 5);
+    uint32_t tmp;
+    #define READ_LONG(num, offset) ({ pci_device_cfg_read_u32(dev##num, &tmp, (offset)); tmp; })
+#else
+    #define READ_LONG(num, offset) pciReadLong(pciTag(0, 0, num), (offset))
+#endif
     nv10_fifo_info fifo_data;
     nv10_sim_state sim_data;
     unsigned int M, N, P, pll, MClk, NVClk, memctrl;
@@ -684,11 +694,11 @@ static void nForceUpdateArbitrationSettings (
     if((pNv->Chipset & 0x0FF0) == 0x01A0) {
        unsigned int uMClkPostDiv;
 
-       uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
+       uMClkPostDiv = (READ_LONG(3, 0x6C) >> 8) & 0xf;
        if(!uMClkPostDiv) uMClkPostDiv = 4; 
        MClk = 400000 / uMClkPostDiv;
     } else {
-       MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
+       MClk = READ_LONG(5, 0x4C) / 1000;
     }
 
     pll = pNv->PRAMDAC0[0x0500/4];
@@ -697,17 +707,17 @@ static void nForceUpdateArbitrationSettings (
     sim_data.pix_bpp        = (char)pixelDepth;
     sim_data.enable_video   = 0;
     sim_data.enable_mp      = 0;
-    sim_data.memory_type    = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
+    sim_data.memory_type    = (READ_LONG(1, 0x7C) >> 12) & 1;
     sim_data.memory_width   = 64;
 
-    memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
+    memctrl = READ_LONG(3, 0x00) >> 16;
 
     if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
         int dimm[3];
 
-        dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
-        dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
-        dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
+        dimm[0] = (READ_LONG(2, 0x40) >> 8) & 0x4F;
+        dimm[1] = (READ_LONG(2, 0x44) >> 8) & 0x4F;
+        dimm[2] = (READ_LONG(2, 0x48) >> 8) & 0x4F;
 
         if((dimm[0] + dimm[1]) != dimm[2]) {
              ErrorF("WARNING: "
@@ -730,6 +740,8 @@ static void nForceUpdateArbitrationSettings (
         while (b >>= 1) (*burst)++;
         *lwm   = fifo_data.graphics_lwm >> 3;
     }
+
+#undef READ_LONG
 }
 
 
diff --git a/src/nv_setup.c b/src/nv_setup.c
index 5772dd0..72a7844 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -298,6 +298,24 @@ static void nv10GetConfig (NVPtr pNv)
     }
 #endif
 
+#if XSERVER_LIBPCIACCESS
+    {
+    /* [AGP]: I don't know if this is correct */
+    struct pci_device *dev = pci_device_find_by_slot(0, 0, 0, 1);
+
+    if(implementation == 0x01a0) {
+        uint32_t amt;
+        pci_device_cfg_read_u32(dev, &amt, 0x7C);
+        pNv->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
+    } else if(implementation == 0x01f0) {
+        uint32_t amt;
+        pci_device_cfg_read_u32(dev, &amt, 0x84);
+        pNv->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
+    } else {
+        pNv->RamAmountKBytes = (pNv->PFB[0x020C/4] & 0xFFF00000) >> 10;
+    }
+    }
+#else
     if(implementation == 0x01a0) {
         int amt = pciReadLong(pciTag(0, 0, 1), 0x7C);
         pNv->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
@@ -307,6 +325,7 @@ static void nv10GetConfig (NVPtr pNv)
     } else {
         pNv->RamAmountKBytes = (pNv->PFB[0x020C/4] & 0xFFF00000) >> 10;
     }
+#endif
 
     if(pNv->RamAmountKBytes > 256*1024)
         pNv->RamAmountKBytes = 256*1024;
@@ -337,6 +356,7 @@ NVCommonSetup(ScrnInfoPtr pScrn)
     Bool tvB = FALSE;
     int FlatPanel = -1;   /* really means the CRTC is slaved */
     Bool Television = FALSE;
+    void *tmp;
     
     /*
      * Override VGA I/O routines.
@@ -365,10 +385,15 @@ NVCommonSetup(ScrnInfoPtr pScrn)
      */
     pVga->MMIOBase   = (CARD8 *)pNv;
     pVga->MMIOOffset = 0;
-    
-    pNv->REGS = xf86MapPciMem(pScrn->scrnIndex, 
-                              VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 
-                              pNv->PciTag, pNv->IOAddress, 0x01000000);
+
+#if XSERVER_LIBPCIACCESS
+    pci_device_map_range(pNv->PciInfo, pNv->IOAddress, 0x01000000,
+                         PCI_DEV_MAP_FLAG_WRITABLE, &tmp);
+#else
+    tmp = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
+                        pNv->PciTag, pNv->IOAddress, 0x01000000);
+#endif
+    pNv->REGS = tmp;
 
     pNv->PRAMIN   = pNv->REGS + (0x00710000/4);
     pNv->PCRTC0   = pNv->REGS + (0x00600000/4);
diff --git a/src/nv_type.h b/src/nv_type.h
index 160441b..2710c5a 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -79,8 +79,12 @@ typedef struct {
     CARD32              Architecture;
     CARD32              CursorStart;
     EntityInfoPtr       pEnt;
+#if XSERVER_LIBPCIACCESS
+    struct pci_device  *PciInfo;
+#else
     pciVideoPtr         PciInfo;
     PCITAG              PciTag;
+#endif
     int                 Chipset;
     int                 ChipRev;
     Bool                Primary;
diff --git a/src/riva_driver.c b/src/riva_driver.c
index d17d699..b021749 100644
--- a/src/riva_driver.c
+++ b/src/riva_driver.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "nv_const.h"
 #include "riva_include.h"
 
 #include "xf86int10.h"
@@ -479,8 +480,10 @@ RivaPreInit(ScrnInfoPtr pScrn, int flags)
  
     /* Find the PCI info for this screen */
     pRiva->PciInfo = xf86GetPciInfoForEntity(pRiva->pEnt->index);
+#if !XSERVER_LIBPCIACCESS
     pRiva->PciTag = pciTag(pRiva->PciInfo->bus, pRiva->PciInfo->device,
 			  pRiva->PciInfo->func);
+#endif
 
     pRiva->Primary = xf86IsPrimaryPci(pRiva->PciInfo);
 
@@ -499,8 +502,9 @@ RivaPreInit(ScrnInfoPtr pScrn, int flags)
     /* Set pScrn->monitor */
     pScrn->monitor = pScrn->confScreen->monitor;
 
-    pRiva->ChipRev = pRiva->PciInfo->chipRev;
-    if((pRiva->PciInfo->vendor != 0x12D2) || (pRiva->PciInfo->chipType != 0x0018))
+    pRiva->ChipRev = CHIP_REVISION(pRiva->PciInfo);
+    if(VENDOR_ID(pRiva->PciInfo) != PCI_VENDOR_NVIDIA_SGS ||
+       DEVICE_ID(pRiva->PciInfo) != PCI_CHIP_RIVA128)
     {
         xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "This is not a RIVA 128\n");
         xf86FreeInt10(pRiva->pInt);
@@ -690,8 +694,8 @@ RivaPreInit(ScrnInfoPtr pScrn, int flags)
     } else {
 	int i = 1;
 	pRiva->FbBaseReg = i;
-	if (pRiva->PciInfo->memBase[i] != 0) {
-	    pRiva->FbAddress = pRiva->PciInfo->memBase[i] & 0xff800000;
+	if (MEMBASE(pRiva->PciInfo, i) != 0) {
+	    pRiva->FbAddress = MEMBASE(pRiva->PciInfo, i) & 0xff800000;
 	    from = X_PROBED;
 	} else {
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -718,8 +722,8 @@ RivaPreInit(ScrnInfoPtr pScrn, int flags)
 	from = X_CONFIG;
     } else {
 	int i = 0;
-	if (pRiva->PciInfo->memBase[i] != 0) {
-	    pRiva->IOAddress = pRiva->PciInfo->memBase[i] & 0xffffc000;
+	if (MEMBASE(pRiva->PciInfo, i) != 0) {
+	    pRiva->IOAddress = MEMBASE(pRiva->PciInfo, i) & 0xffffc000;
 	    from = X_PROBED;
 	} else {
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -916,22 +920,34 @@ RivaPreInit(ScrnInfoPtr pScrn, int flags)
 static Bool
 RivaMapMem(ScrnInfoPtr pScrn)
 {
-    RivaPtr pRiva;
-        
-    pRiva = RivaPTR(pScrn);
+    RivaPtr pRiva = RivaPTR(pScrn);
 
     /*
      * Map IO registers to virtual address space
      */ 
+#if XSERVER_LIBPCIACCESS
+    void *tmp;
+
+    pci_device_map_range(pRiva->PciInfo, pRiva->IOAddress, 0x1000000,
+                         PCI_DEV_MAP_FLAG_WRITABLE, &tmp);
+    pRiva->IOBase = tmp;
+    pci_device_map_range(pRiva->PciInfo, pRiva->FbAddress, pRiva->FbMapSize,
+                         PCI_DEV_MAP_FLAG_WRITABLE |
+                         PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+                         &tmp);
+    pRiva->FbBase = tmp;
+#else
     pRiva->IOBase = xf86MapPciMem(pScrn->scrnIndex,
                                 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
                                 pRiva->PciTag, pRiva->IOAddress, 0x1000000);
-    if (pRiva->IOBase == NULL)
-	return FALSE;
-
     pRiva->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
 				 pRiva->PciTag, pRiva->FbAddress,
 				 pRiva->FbMapSize);
+#endif
+
+    if (pRiva->IOBase == NULL)
+	return FALSE;
+
     if (pRiva->FbBase == NULL)
 	return FALSE;
 
@@ -974,10 +990,15 @@ RivaUnmapMem(ScrnInfoPtr pScrn)
     /*
      * Unmap IO registers to virtual address space
      */ 
+#if XSERVER_LIBPCIACCESS
+    pci_device_unmap_range(pRiva->PciInfo, pRiva->IOBase, 0x1000000);
+    pci_device_unmap_range(pRiva->PciInfo, pRiva->FbBase, pRiva->FbMapSize);
+#else
     xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pRiva->IOBase, 0x1000000);
-    pRiva->IOBase = NULL;
-
     xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pRiva->FbBase, pRiva->FbMapSize);
+#endif
+
+    pRiva->IOBase = NULL;
     pRiva->FbBase = NULL;
     pRiva->FbStart = NULL;
 
diff --git a/src/riva_setup.c b/src/riva_setup.c
index 7bceb09..b7352b6 100644
--- a/src/riva_setup.c
+++ b/src/riva_setup.c
@@ -187,7 +187,6 @@ Riva3Setup(ScrnInfoPtr pScrn)
     CARD32 regBase = pRiva->IOAddress;
     CARD32 frameBase = pRiva->FbAddress;
     xf86MonPtr monitor;
-    int mmioFlags;
     
     pRiva->Save = RivaDACSave;
     pRiva->Restore = RivaDACRestore;
@@ -229,40 +228,39 @@ Riva3Setup(ScrnInfoPtr pScrn)
     pRiva->riva.EnableIRQ = 0;
     pRiva->riva.IO      = VGA_IOBASE_COLOR;
 
-    mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
+#if XSERVER_LIBPCIACCESS
+#define MAP(ptr, offset, size) { \
+    void *tmp; \
+    pci_device_map_range(pRiva->PciInfo, (offset), (size), \
+                         PCI_DEV_MAP_FLAG_WRITABLE, &tmp); \
+    pRiva->riva.ptr = tmp; \
+ }
+#else
+#define MAP(ptr, offset, size) \
+    pRiva->riva.ptr = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO | \
+                                    VIDMEM_READSIDEEFFECT, pRiva->PciTag, \
+                                    (offset), (size));
+#endif
 
-    pRiva->riva.PRAMDAC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00680000, 0x00003000);
-    pRiva->riva.PFB     = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00100000, 0x00001000);
-    pRiva->riva.PFIFO   = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00002000, 0x00002000);
-    pRiva->riva.PGRAPH  = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00400000, 0x00002000);
-    pRiva->riva.PEXTDEV = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00101000, 0x00001000);
-    pRiva->riva.PTIMER  = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00009000, 0x00001000);
-    pRiva->riva.PMC     = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00000000, 0x00009000);
-    pRiva->riva.FIFO    = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                      regBase+0x00800000, 0x00010000);
-    pRiva->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
-                                     frameBase+0x00C00000, 0x00008000);
+    MAP(PRAMDAC, regBase + 0x00680000, 0x00003000);
+    MAP(PFB,     regBase + 0x00100000, 0x00001000);
+    MAP(PFIFO,   regBase + 0x00002000, 0x00002000);
+    MAP(PGRAPH,  regBase + 0x00400000, 0x00002000);
+    MAP(PEXTDEV, regBase + 0x00101000, 0x00001000);
+    MAP(PTIMER,  regBase + 0x00009000, 0x00001000);
+    MAP(PMC,     regBase + 0x00000000, 0x00009000);
+    MAP(FIFO,    regBase + 0x00800000, 0x00010000);
+    MAP(PRAMIN,  frameBase+0x00C00000, 0x00008000);
 
     /*
      * These registers are read/write as 8 bit values.  Probably have to map
      * sparse on alpha.
      */
-    pRiva->riva.PCIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
-                                           pRiva->PciTag, regBase+0x00601000,
-                                           0x00003000);
-    pRiva->riva.PDIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
-                                           pRiva->PciTag, regBase+0x00681000,
-                                           0x00003000);
-    pRiva->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
-                                           pRiva->PciTag, regBase+0x000C0000,
-                                           0x00001000);
+    MAP(PCIO, regBase + 0x00601000, 0x00003000);
+    MAP(PDIO, regBase + 0x00681000, 0x00003000);
+    MAP(PVIO, regBase + 0x000C0000, 0x00001000);
+
+#undef MAP
 
     pRiva->riva.PCRTC = pRiva->riva.PGRAPH;
 
diff --git a/src/riva_type.h b/src/riva_type.h
index 606e3e5..e9448e6 100644
--- a/src/riva_type.h
+++ b/src/riva_type.h
@@ -51,8 +51,12 @@ typedef struct {
     RIVA_HW_STATE       SavedReg;
     RIVA_HW_STATE       ModeReg;
     EntityInfoPtr       pEnt;
+#if XSERVER_LIBPCIACCESS
+    struct pci_device  *PciInfo;
+#else
     pciVideoPtr         PciInfo;
     PCITAG              PciTag;
+#endif
     xf86AccessRec       Access;
     int                 ChipRev;
     Bool                Primary;