#ifndef __SAVAGE_STREAMS_H__ # define __SAVAGE_STREAMS_H__ /************************************** S3 streams processor **************************************/ #define EXT_MISC_CTRL2 0x67 /* New streams */ /* CR67[2] = 1 : enable secondary stream 1 */ #define ENABLE_STREAM1 0x04 /* CR67[1] = 1 : enable secondary stream 2 */ #define ENABLE_STREAM2 0x02 /* mask to clear CR67[2,1] */ #define NO_STREAMS 0xF9 /* CR67[3] = 1 : Mem-mapped regs */ #define USE_MM_FOR_PRI_STREAM 0x08 #define HDM_SHIFT 16 #define HDSCALE_4 (2 << HDM_SHIFT) #define HDSCALE_8 (3 << HDM_SHIFT) #define HDSCALE_16 (4 << HDM_SHIFT) #define HDSCALE_32 (5 << HDM_SHIFT) #define HDSCALE_64 (6 << HDM_SHIFT) /* Old Streams */ #define ENABLE_STREAMS_OLD 0x0c #define NO_STREAMS_OLD 0xf3 /* CR69[0] = 1 : Mem-mapped regs */ #define USE_MM_FOR_PRI_STREAM_OLD 0x01 /* * There are two different streams engines used in the Savage line. * The old engine is in the 3D, 4, Pro, and Twister. * The new engine is in the 2000, MX, IX, and Super. */ /* streams registers for old engine */ #define PSTREAM_CONTROL_REG 0x8180 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 #define SSTREAM_CONTROL_REG 0x8190 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 #define SSTREAM_STRETCH_REG 0x8198 #define COLOR_ADJUSTMENT_REG 0x819C #define BLEND_CONTROL_REG 0x81A0 #define PSTREAM_FBADDR0_REG 0x81C0 #define PSTREAM_FBADDR1_REG 0x81C4 #define PSTREAM_STRIDE_REG 0x81C8 #define DOUBLE_BUFFER_REG 0x81CC /* updated by peterzhu,original define is DOUBLE_BUFFER_REG*/ #define MULTIPLE_BUFFER_REG 0x81CC #define SSTREAM_FBADDR0_REG 0x81D0 #define SSTREAM_FBADDR1_REG 0x81D4 #define SSTREAM_STRIDE_REG 0x81D8 #define SSTREAM_VSCALE_REG 0x81E0 #define SSTREAM_VINITIAL_REG 0x81E4 #define SSTREAM_LINES_REG 0x81E8 #define STREAMS_FIFO_REG 0x81EC #define PSTREAM_WINDOW_START_REG 0x81F0 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 #define SSTREAM_WINDOW_START_REG 0x81F8 #define SSTREAM_WINDOW_SIZE_REG 0x81FC #define FIFO_CONTROL 0x8200 #define PSTREAM_FBSIZE_REG 0x8300 #define SSTREAM_FBSIZE_REG 0x8304 #define SSTREAM_FBADDR2_REG 0x8308 #define OS_XY(x,y) (((x)<<16)|(y+1)) /*(((x+1)<<16)|(y+1))*/ #define OS_WH(x,y) (((x-1)<<16)|(y)) /* Streams Processor macros */ #define H_Shift 0 #define H_Mask (((1L << 11) - 1) << H_Shift) #define W_Shift 16 #define W_Mask (((1L << 11) - 1) << W_Shift) #define Y_Shift 0 #define Y_Mask (((1L << 11) - 1) << Y_Shift) #define X_Shift 16 #define X_Mask (((1L << 11) - 1) << X_Shift) #define XY(x,y) ((((x+1)< 16 ? (bpp > 24 ? STREAMS_MODE32 :\ STREAMS_MODE24) : STREAMS_MODE16) #endif /*__SAVAGE_STREAMS_H__*/