Cleanup the Lynx register saving/restoring code.

Save some registers not previously tracked, and use pSmi->mode instead
of continuously reading the hardware state.

4 files changed, 310 insertions, 340 deletions

diff --git a/src/smi.h b/src/smi.h
index 32c13b1..ebd8a66 100644
--- a/src/smi.h
+++ b/src/smi.h
@@ -116,28 +116,29 @@ authorization from the XFree86 Project and Silicon Motion.
 /* Driver data structure; this should contain all needed info for a mode */
 typedef struct
 {
-    Bool    modeInit;
-    CARD16	mode;
-    CARD8	SR17, SR18, SR21, SR31, SR32, SR6A, SR6B, SR81, SRA0;
-    CARD8	CR33, CR33_2, CR3A;
-    CARD8	CR40[14], CR40_2[14];
-    CARD8	CR90[16], CR9F_2;
-    CARD8	CRA0[14];
+    CARD16 mode;
+
+    CARD8 SR17, SR18;
+    CARD8 SR20, SR21, SR22, SR23, SR24;
+    CARD8 SR30, SR31, SR32, SR34;
+    CARD8 SR40, SR41, SR42, SR43, SR44, SR45, SR48, SR49, SR4A, SR4B, SR4C;
+    CARD8 SR50, SR51, SR52, SR53, SR54, SR55, SR56, SR57, SR5A;
+    CARD8 SR66, SR68, SR69, SR6A, SR6B, SR6C, SR6D, SR6E, SR6F;
+    CARD8 SR81, SRA0;
+
+    CARD8 CR30, CR33, CR33_2, CR3A;
+    CARD8 CR40[14], CR40_2[14];
+    CARD8 CR90[15], CR9F, CR9F_2;
+    CARD8 CRA0[14];
+
     CARD8	smiDACMask, smiDacRegs[256][3];
-    /* CZ 2.11.2001: for gamma correction */
-    CARD8   CCR66;
-    /* end CZ */
     CARD8	smiFont[8192];
+
     CARD32	DPR10, DPR1C, DPR20, DPR24, DPR28, DPR2C, DPR30, DPR3C, DPR40,
 		DPR44;
     CARD32	VPR00, VPR0C, VPR10;
     CARD32	CPR00;
     CARD32	FPR00_, FPR0C_, FPR10_;
-    /* LCD FIFO regs, etc. - dualhead */
-    CARD8   SR22, SR40, SR41, SR42, SR43, SR44, SR45, SR48, SR49,
-	    SR4A, SR4B, SR4C;
-    /* PLL controls */
-    CARD8   SR68, SR69, SR6C, SR6D, SR6E, SR6F;
 } SMIRegRec, *SMIRegPtr;
 
 /* Global PDEV structure. */
diff --git a/src/smilynx_crtc.c b/src/smilynx_crtc.c
index 9b1b86a..7fafea1 100644
--- a/src/smilynx_crtc.c
+++ b/src/smilynx_crtc.c
@@ -71,48 +71,53 @@ SMILynx_CrtcVideoInit_lcd(xf86CrtcPtr crtc)
 {
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
-    CARD8 SR31;
+    SMIRegPtr mode = pSmi->mode;
     CARD16 fifo_readoffset,fifo_writeoffset;
 
     ENTER();
 
     /* Set display depth */
-    SR31=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31);
     if (pScrn->bitsPerPixel > 8)
-	SR31 |= 0x40; /* 16 bpp */
+	mode->SR31 |= 0x40; /* 16 bpp */
     else
-	SR31 &= ~0x40; /* 8 bpp */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31,SR31);
+	mode->SR31 &= ~0x40; /* 8 bpp */
 
     /* FIFO1/2 Read Offset*/
     fifo_readoffset = (crtc->rotatedData? crtc->mode.HDisplay : pScrn->displayWidth) * pSmi->Bpp;
     fifo_readoffset = ((fifo_readoffset + 15) & ~15) >> 3;
 
     /* FIFO1 Read Offset */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x44, fifo_readoffset & 0x000000FF);
+    mode->SR44 = fifo_readoffset & 0x000000FF;
     /* FIFO2 Read Offset */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4B, fifo_readoffset & 0x000000FF);
+    mode->SR4B = fifo_readoffset & 0x000000FF;
 
     if(pSmi->Chipset == SMI_LYNX3DM){
 	/* FIFO1/2 Read Offset overflow */
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C, (((fifo_readoffset & 0x00000300) >> 8) << 2) |
-		      (((fifo_readoffset & 0x00000300) >> 8) << 6));
+	mode->SR4C = (((fifo_readoffset & 0x00000300) >> 8) << 2) |
+	    (((fifo_readoffset & 0x00000300) >> 8) << 6);
     }else{
 	/* FIFO1 Read Offset overflow */
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45,
-		      (VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x45) & 0x3F) |
-		      ((fifo_readoffset & 0x00000300) >> 8) << 6);
+	mode->SR45 = (mode->SR45 & 0x3F) | ((fifo_readoffset & 0x00000300) >> 8) << 6;
 	/* FIFO2 Read Offset overflow */
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C, ((fifo_readoffset & 0x00000300) >> 8) << 6);
+	mode->SR4C = (((fifo_readoffset & 0x00000300) >> 8) << 6);
     }
 
     /* FIFO Write Offset */
     fifo_writeoffset = crtc->mode.HDisplay * pSmi->Bpp >> 3;
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x48, fifo_writeoffset & 0x000000FF);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x49, (fifo_writeoffset & 0x00000300) >> 8);
+    mode->SR48 = fifo_writeoffset & 0x000000FF;
+    mode->SR49 = (fifo_writeoffset & 0x00000300) >> 8;
 
     /* set FIFO levels */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4A, 0x41);
+    mode->SR4A = 0x41;
+
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, mode->SR31);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x44, mode->SR44);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45, mode->SR45);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x48, mode->SR48);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x49, mode->SR49);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4A, mode->SR4A);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4B, mode->SR4B);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C, mode->SR4C);
 
     LEAVE();
 }
@@ -159,6 +164,7 @@ SMILynx_CrtcAdjustFrame(xf86CrtcPtr crtc, int x, int y)
 {
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
+    SMIRegPtr mode = pSmi->mode;
     xf86CrtcConfigPtr crtcConf = XF86_CRTC_CONFIG_PTR(pScrn);
     CARD32 Base;
 
@@ -192,25 +198,25 @@ SMILynx_CrtcAdjustFrame(xf86CrtcPtr crtc, int x, int y)
 	    /* LCD */
 
 	    /* FIFO1 read start address */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x40,
-			  (Base & 0x000000FF));
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x41,
-			  ((Base & 0x0000FF00) >> 8));
+	    mode->SR40 = Base & 0x000000FF;
+	    mode->SR41 = (Base & 0x0000FF00) >> 8;
 
 	    /* FIFO2 read start address */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x42,
-			  (Base & 0x000000FF));
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x43,
-			  ((Base & 0x0000FF00) >> 8));
+	    mode->SR42 = Base & 0x000000FF;
+	    mode->SR43 = (Base & 0x0000FF00) >> 8;
 
 	    /* FIFO1/2 read start address overflow */
 	    if(pSmi->Chipset == SMI_LYNX3DM)
-		VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45,
-			      ((Base & 0x000F0000) >> 16) | (((Base & 0x000F0000) >> 16) << 4));
+		mode->SR45 = (Base & 0x000F0000) >> 16 | (Base & 0x000F0000) >> 16 << 4;
 	    else
-		VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45,
-			      (VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45) & 0xC0) |
-			      ((Base & 0x00070000) >> 16) | (((Base & 0x00070000) >> 16) << 3));
+		mode->SR45 = (mode->SR45 & 0xC0) |
+		    (Base & 0x00070000) >> 16 | (Base & 0x00070000) >> 16 << 3;
+
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x40, mode->SR40);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x41, mode->SR41);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x42, mode->SR42);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x43, mode->SR43);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45, mode->SR45);
 
 	}else{
 	    /* CRT or single head */
@@ -229,12 +235,12 @@ SMILynx_CrtcModeSet_vga(xf86CrtcPtr crtc,
 {
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
+    SMIRegPtr reg = pSmi->mode;
     vgaHWPtr hwp = VGAHWPTR(pScrn);
     int vgaIOBase  = hwp->IOBase;
     int vgaCRIndex = vgaIOBase + VGA_CRTC_INDEX_OFFSET;
     int vgaCRData  = vgaIOBase + VGA_CRTC_DATA_OFFSET;
     vgaRegPtr vganew = &hwp->ModeReg;
-    CARD8 SR6C, SR6D, CR30, CR33;
 
     ENTER();
 
@@ -252,17 +258,17 @@ SMILynx_CrtcModeSet_vga(xf86CrtcPtr crtc,
 			1, 1, 63, 0, 3,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6C, &SR6D);
+                        &reg->SR6C, &reg->SR6D);
     } else {
         SMI_CommonCalcClock(pScrn->scrnIndex, mode->Clock,
 			1, 1, 63, 0, 1,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6C, &SR6D);
+                        &reg->SR6C, &reg->SR6D);
     }
 
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, SR6C);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, SR6D);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, reg->SR6C);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, reg->SR6D);
 
 
     /* Adjust mode timings */
@@ -296,21 +302,21 @@ SMILynx_CrtcModeSet_vga(xf86CrtcPtr crtc,
 	vganew->CRTC[22] = VBlankEnd & 0xFF;
 
 	/* Write the overflow from several VGA registers */
-	CR30 = (VTotal & 0x400) >> 10 << 3 |
+	reg->CR30 = (VTotal & 0x400) >> 10 << 3 |
 	    (VDisplay & 0x400) >> 10 << 2 |
 	    (VBlankStart & 0x400) >> 10 << 1 |
 	    (VSyncStart & 0x400) >> 10 << 0;
 
 	if(pSmi->Chipset == SMI_LYNX3DM)
-	    CR30 |= (HTotal & 0x100) >> 8 << 6;
+	    reg->CR30 |= (HTotal & 0x100) >> 8 << 6;
 
-	CR33 = (HBlankEnd & 0xC0) >> 6 << 5 | (VBlankEnd & 0x300) >> 8 << 3;
+	reg->CR33 = (HBlankEnd & 0xC0) >> 6 << 5 | (VBlankEnd & 0x300) >> 8 << 3;
     }
 
     vgaHWRestore(pScrn, vganew, VGA_SR_MODE);
 
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, CR30);
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, CR33);
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, reg->CR30);
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, reg->CR33);
 
     LEAVE();
 }
@@ -323,11 +329,12 @@ SMILynx_CrtcModeSet_crt(xf86CrtcPtr crtc,
 {
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
+    SMIRegPtr reg = pSmi->mode;
     vgaHWPtr hwp = VGAHWPTR(pScrn);
     int vgaIOBase  = hwp->IOBase;
     int	vgaCRIndex = vgaIOBase + VGA_CRTC_INDEX_OFFSET;
     int	vgaCRData  = vgaIOBase + VGA_CRTC_DATA_OFFSET;
-    CARD8 SR6C, SR6D, CR30, CR33;
+    int i;
 
     ENTER();
 
@@ -345,27 +352,23 @@ SMILynx_CrtcModeSet_crt(xf86CrtcPtr crtc,
 			1, 1, 63, 0, 3,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6C, &SR6D);
+                        &reg->SR6C, &reg->SR6D);
     } else {
         SMI_CommonCalcClock(pScrn->scrnIndex, mode->Clock,
 			1, 1, 63, 0, 1,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6C, &SR6D);
+                        &reg->SR6C, &reg->SR6D);
     }
 
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, SR6C);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, SR6D);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, reg->SR6C);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, reg->SR6D);
 
 
     /* Adjust mode timings */
     /* In virtual refresh mode, the CRT timings are controlled through
        the shadow VGA registers */
 
-    /* Select primary set of shadow registers */
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E,
-		  VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E) & ~0x20);
-
     {
 	unsigned long HTotal=(mode->CrtcHTotal>>3)-5;
 	unsigned long HDisplay=(mode->CrtcHDisplay>>3)-1;
@@ -384,47 +387,50 @@ SMILynx_CrtcModeSet_crt(xf86CrtcPtr crtc,
 	if((mode->CrtcHBlankEnd >> 3) == (mode->CrtcHTotal >> 3)) HBlankEnd=0;
 	if(mode->CrtcVBlankEnd == mode->CrtcVTotal) VBlankEnd=0;
 
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40, HTotal & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x41, HBlankStart & 0xFF);
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x42, HBlankEnd & 0x1F);
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x43, HSyncStart & 0xFF);
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x44,
-		      (HBlankEnd & 0x20) >> 5 << 7 |
-		      (HSyncEnd & 0x1F) );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x45, VTotal & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x46, VBlankStart & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x47, VBlankEnd & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x48, VSyncStart & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x49, VSyncEnd & 0x0F );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x4A,
-		      (VSyncStart & 0x200) >> 9 << 7 |
-		      (VDisplay & 0x200) >> 9 << 6 |
-		      (VTotal & 0x200) >> 9 << 5 |
-		      (VBlankStart & 0x100) >> 8 << 3 |
-		      (VSyncStart & 0x100) >> 8 << 2 |
-		      (VDisplay & 0x100) >> 8 << 1 |
-		      (VTotal & 0x100) >> 8 << 0 );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x4B,
-		      ((mode->Flags & V_NVSYNC)?1:0) << 7 |
-		      ((mode->Flags & V_NHSYNC)?1:0) << 6 |
-		      (VBlankStart & 0x200) >> 9 << 5 );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x4C, HDisplay & 0xFF );
-	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x4D, VDisplay & 0xFF );
-
-	CR30 = (VTotal & 0x400) >> 10 << 3 |
+	reg->CR40 [0x0] = HTotal & 0xFF;
+	reg->CR40 [0x1] = HBlankStart & 0xFF;
+	reg->CR40 [0x2] = HBlankEnd & 0x1F;
+	reg->CR40 [0x3] = HSyncStart & 0xFF;
+	reg->CR40 [0x4] = (HBlankEnd & 0x20) >> 5 << 7 |
+	    (HSyncEnd & 0x1F);
+	reg->CR40 [0x5] = VTotal & 0xFF;
+	reg->CR40 [0x6] = VBlankStart & 0xFF;
+	reg->CR40 [0x7] = VBlankEnd & 0xFF;
+	reg->CR40 [0x8] = VSyncStart & 0xFF;
+	reg->CR40 [0x9] = VSyncEnd & 0x0F;
+	reg->CR40 [0xA] = (VSyncStart & 0x200) >> 9 << 7 |
+	    (VDisplay & 0x200) >> 9 << 6 |
+	    (VTotal & 0x200) >> 9 << 5 |
+	    (VBlankStart & 0x100) >> 8 << 3 |
+	    (VSyncStart & 0x100) >> 8 << 2 |
+	    (VDisplay & 0x100) >> 8 << 1 |
+	    (VTotal & 0x100) >> 8 << 0;
+	reg->CR40 [0xB] = ((mode->Flags & V_NVSYNC)?1:0) << 7 |
+	    ((mode->Flags & V_NHSYNC)?1:0) << 6 |
+	    (VBlankStart & 0x200) >> 9 << 5;
+	reg->CR40 [0xC] = HDisplay & 0xFF;
+	reg->CR40 [0xD] = VDisplay & 0xFF;
+
+	reg->CR30 = (VTotal & 0x400) >> 10 << 3 |
 	    (VDisplay & 0x400) >> 10 << 2 |
 	    (VBlankStart & 0x400) >> 10 << 1 |
 	    (VSyncStart & 0x400) >> 10 << 0;
 
 	if(pSmi->Chipset == SMI_LYNX3DM)
-	    CR30 |= (HTotal & 0x100) >> 8 << 6;
+	    reg->CR30 |= (HTotal & 0x100) >> 8 << 6;
 
-	CR33 = (HBlankEnd & 0xC0) >> 6 << 5 | (VBlankEnd & 0x300) >> 8 << 3;
+	reg->CR33 = (HBlankEnd & 0xC0) >> 6 << 5 | (VBlankEnd & 0x300) >> 8 << 3;
 
     }
 
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, CR30);
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, CR33);
+    /* Select primary set of shadow registers */
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, reg->CR90[0xE] & ~0x20);
+
+    for(i=0; i <= 0xD; i++)
+	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40 + i, reg->CR40[i]);
+
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, reg->CR30);
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, reg->CR33);
 
     LEAVE();
 }
@@ -437,7 +443,7 @@ SMILynx_CrtcModeSet_lcd(xf86CrtcPtr crtc,
 {
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
-    CARD8 SR32, SR6E, SR6F;
+    SMIRegPtr reg = pSmi->mode;
 
     ENTER();
 
@@ -455,16 +461,16 @@ SMILynx_CrtcModeSet_lcd(xf86CrtcPtr crtc,
 			1, 1, 63, 0, 1,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6E, &SR6F);
+                        &reg->SR6E, &reg->SR6F);
     } else {
         SMI_CommonCalcClock(pScrn->scrnIndex, mode->Clock,
 			1, 1, 63, 0, 0,
                         pSmi->clockRange.minClock,
                         pSmi->clockRange.maxClock,
-                        &SR6E, &SR6F);
+                        &reg->SR6E, &reg->SR6F);
     }
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6E, SR6E);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6F, SR6F);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6E, reg->SR6E);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6F, reg->SR6F);
 
 
     /* Adjust mode timings */
@@ -478,36 +484,42 @@ SMILynx_CrtcModeSet_lcd(xf86CrtcPtr crtc,
 	unsigned long VSyncStart=mode->CrtcVSyncStart-1;
 	unsigned long VSyncWidth=mode->CrtcVSyncEnd - mode->CrtcVSyncStart - 1;
 
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x50,
-		      (VTotal & 0x700) >> 8 << 1 |
-		      (HSyncStart & 0x100) >> 8 << 0);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x51,
-		      (VSyncStart & 0x700) >> 8 << 5 |
-		      (VDisplay & 0x700) >> 8 << 2 |
-		      (HDisplay & 0x100) >> 8 << 1 |
-		      (HTotal & 0x100) >> 8 << 0);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x52, HTotal & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x53, HDisplay & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x54, HSyncStart & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x55, VTotal & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x56, VDisplay & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x57, VSyncStart & 0xFF);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x5A,
-		      (HSyncWidth & 0x1F) << 3 |
-		      (VSyncWidth & 0x07) << 0);
+	reg->SR50 = (VTotal & 0x700) >> 8 << 1 |
+	    (HSyncStart & 0x100) >> 8 << 0;
+	reg->SR51 = (VSyncStart & 0x700) >> 8 << 5 |
+	    (VDisplay & 0x700) >> 8 << 2 |
+	    (HDisplay & 0x100) >> 8 << 1 |
+	    (HTotal & 0x100) >> 8 << 0;
+	reg->SR52 = HTotal & 0xFF;
+	reg->SR53 = HDisplay & 0xFF;
+	reg->SR54 = HSyncStart & 0xFF;
+	reg->SR55 = VTotal & 0xFF;
+	reg->SR56 = VDisplay & 0xFF;
+	reg->SR57 = VSyncStart & 0xFF;
+	reg->SR5A = (HSyncWidth & 0x1F) << 3 |
+	    (VSyncWidth & 0x07) << 0;
 
 	/* XXX - Why is the polarity hardcoded here? */
-	SR32=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x32);
-	SR32 &= ~0x18;
+	reg->SR32 &= ~0x18;
 	if (mode->HDisplay == 800) {
-	    SR32 |= 0x18;
+	    reg->SR32 |= 0x18;
 	}
 	if ((mode->HDisplay == 1024) && SMI_LYNXM_SERIES(pSmi->Chipset)) {
-	    SR32 |= 0x18;
+	    reg->SR32 |= 0x18;
 	}
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x32,SR32);
     }
 
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32, reg->SR32);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x50, reg->SR50);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x51, reg->SR51);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x52, reg->SR52);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x53, reg->SR53);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x54, reg->SR54);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x55, reg->SR55);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x56, reg->SR56);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x57, reg->SR57);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x5A, reg->SR5A);
+
     LEAVE();
 }
 
@@ -516,16 +528,14 @@ SMILynx_CrtcLoadLUT_crt(xf86CrtcPtr crtc)
 {
     ScrnInfoPtr pScrn = crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
+    SMIRegPtr mode = pSmi->mode;
     SMICrtcPrivatePtr crtcPriv = SMICRTC(crtc);
-    CARD8 SR66;
     int i;
 
     ENTER();
 
-    SR66 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x66);
-
     /* Write CRT RAM only */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x66,(SR66 & ~0x30) | 0x20);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x66,(mode->SR66 & ~0x30) | 0x20);
 
     for(i=0;i<256;i++){
 	VGAOUT8(pSmi, VGA_DAC_WRITE_ADDR, i);
@@ -534,7 +544,6 @@ SMILynx_CrtcLoadLUT_crt(xf86CrtcPtr crtc)
 	VGAOUT8(pSmi, VGA_DAC_DATA, crtcPriv->lut_b[i] >> 8);
     }
 
-
     LEAVE();
 }
 
diff --git a/src/smilynx_hw.c b/src/smilynx_hw.c
index f15a436..115a442 100644
--- a/src/smilynx_hw.c
+++ b/src/smilynx_hw.c
@@ -40,77 +40,60 @@ Bool
 SMILynx_HWInit(ScrnInfoPtr pScrn)
 {
     SMIPtr pSmi = SMIPTR(pScrn);
+    SMIRegPtr mode = pSmi->mode;
     vgaHWPtr	hwp = VGAHWPTR(pScrn);
     int		vgaIOBase  = hwp->IOBase;
     int		vgaCRIndex = vgaIOBase + VGA_CRTC_INDEX_OFFSET;
     int		vgaCRData  = vgaIOBase + VGA_CRTC_DATA_OFFSET;
-    CARD8 SR17, SR20, SR21, SR22, SR24, SR30, SR31, SR32, SR34,
-	SR66, SR68, SR69, SR6A, SR6B, CR9E;
 
     ENTER();
 
-    SR17 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x17);
-    SR20 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x20);
-    SR21 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x21);
-    SR22 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x22);
-    SR24 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x24);
-    SR30 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x30);
-    SR31 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31);
-    SR32 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x32);
-    SR34 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x34);
-    SR66 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x66);
-    SR68 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x68);
-    SR69 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x69);
-    SR6A = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x6A);
-    SR6B = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x6B);
-    CR9E = VGAIN8_INDEX(pSmi, vgaCRIndex,vgaCRData,0x9E);
-
     if (pSmi->PCIBurst) {
-	SR17 |= 0x20;
+	mode->SR17 |= 0x20;
     } else {
-	SR17 &= ~0x20;
+	mode->SR17 &= ~0x20;
     }
 
     /* Disable DAC and LCD framebuffer r/w operation */
-    SR21 |= 0xB0;
+    mode->SR21 |= 0xB0;
 
     /* Power down mode is standby mode, VCLK and MCLK divided by 4 in standby mode */
-    SR20  = (SR20 & ~0xB0) | 0x10;
+    mode->SR20  = (mode->SR20 & ~0xB0) | 0x10;
 
     /* Set DPMS state to Off */
-    SR22 |= 0x30;
+    mode->SR22 |= 0x30;
 
     /* VESA compliance power down mode */
-    SR24 &= ~0x01;
+    mode->SR24 &= ~0x01;
 
     if (pSmi->Chipset != SMI_COUGAR3DR) {
 	/* Select no displays */
-	SR31 &= ~0x07;
+	mode->SR31 &= ~0x07;
 
 	/* Enable virtual refresh */
 	if(pSmi->Dualhead){
-	    SR31 |= 0x80;
+	    mode->SR31 |= 0x80;
 	}else{
-	    SR31 &= ~0x80;
+	    mode->SR31 &= ~0x80;
 	}
 
         /* Disable expansion */
-	SR32 &= ~0x03;
+	mode->SR32 &= ~0x03;
 	/* Enable autocentering */
 	if (SMI_LYNXM_SERIES(pSmi->Chipset))
-	    SR32 |= 0x04;
+	    mode->SR32 |= 0x04;
 	else
-	    SR32 &= ~0x04;
+	    mode->SR32 &= ~0x04;
 
 	if (pSmi->lcd == 2) /* Panel is DSTN */
-	    SR21 = 0x00;
+	    mode->SR21 = 0x00;
 
 	/* Enable HW LCD power sequencing */
-	SR34 |= 0x80;
+	mode->SR34 |= 0x80;
     }
 
     /* Disable Vertical Expansion/Vertical Centering/Horizontal Centering */
-    CR9E &= ~0x7;
+    mode->CR90[0xE] &= ~0x7;
 
     /* Program MCLK */
     if (pSmi->MCLK > 0)
@@ -118,43 +101,48 @@ SMILynx_HWInit(ScrnInfoPtr pScrn)
 			    1, 1, 63, 0, 0,
                             pSmi->clockRange.minClock,
                             pSmi->clockRange.maxClock,
-                             &SR6A, &SR6B);
+                             &mode->SR6A, &mode->SR6B);
 
     /* use vclk1 */
-    SR68 = 0x54;
+    mode->SR68 = 0x54;
 
     if(pSmi->Dualhead){
 	/* set LCD to vclk2 */
-	SR69 = 0x04;
+	mode->SR69 = 0x04;
     }
 
     /* Gamma correction */
     if (pSmi->Chipset == SMI_LYNX3DM || pSmi->Chipset == SMI_COUGAR3DR) {
 	if(pScrn->bitsPerPixel == 8)
-	    SR66 = (SR66 & 0x33) | 0x00; /* Both RAMLUT on, 6 bits-RAM */
+	    mode->SR66 = (mode->SR66 & 0x33) | 0x00; /* Both RAMLUT on, 6 bits-RAM */
 	else
-	    SR66 = (SR66 & 0x33) | 0x04; /* Both RAMLUT on, Gamma correct ON */
+	    mode->SR66 = (mode->SR66 & 0x33) | 0x04; /* Both RAMLUT on, Gamma correct ON */
     }
 
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x17,SR17);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x20,SR20);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x21,SR21);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x22,SR22);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x24,SR24);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x30,SR30);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31,SR31);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x32,SR32);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x34,SR34);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x66,SR66);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x68,SR68);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x69,SR69);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x6A,SR6A);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x6B,SR6B);
-
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0xA0, 0x00);
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, 0x00);
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A, 0x00);
-    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData,0x9E, CR9E);
+    /* Disable panel video */
+    mode->SRA0 = 0;
+
+    mode->CR33 = 0;
+    mode->CR3A = 0;
+
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x17, mode->SR17);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x20, mode->SR20);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, mode->SR21);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, mode->SR22);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x24, mode->SR24);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, mode->SR31);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32, mode->SR32);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x34, mode->SR34);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x66, mode->SR66);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x68, mode->SR68);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x69, mode->SR69);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6A, mode->SR6A);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6B, mode->SR6B);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0xA0, mode->SRA0);
+
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, mode->CR33);
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A, mode->CR3A);
+    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, mode->CR90[0xE]);
 
     LEAVE(TRUE);
 }
@@ -195,23 +183,29 @@ SMILynx_Save(ScrnInfoPtr pScrn)
     /* Now we save all the extended registers we need. */
     save->SR17 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x17);
     save->SR18 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18);
+
+    save->SR20 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x20);
     save->SR21 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21);
+    save->SR22 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22);
+    save->SR23 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23);
+    save->SR24 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x24);
+
     save->SR31 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31);
     save->SR32 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32);
+
+    save->SR66 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x66);
+    save->SR68 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x68);
+    save->SR69 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x69);
     save->SR6A = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6A);
     save->SR6B = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6B);
-    save->SR81 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x81);
-    save->SRA0 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0xA0);
-
-    /* vclk1 */
     save->SR6C = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C);
     save->SR6D = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D);
-    /* vclk1 control */
-    save->SR68 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x68);
+
+    save->SR81 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x81);
+    save->SRA0 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0xA0);
 
     if (pSmi->Dualhead) {
 	/* dualhead stuff */
-	save->SR22 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22);
 	save->SR40 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x40);
 	save->SR41 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x41);
 	save->SR42 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x42);
@@ -223,25 +217,41 @@ SMILynx_Save(ScrnInfoPtr pScrn)
 	save->SR4A = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4A);
 	save->SR4B = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4B);
 	save->SR4C = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C);
+
+	save->SR50 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x50);
+	save->SR51 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x51);
+	save->SR52 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x52);
+	save->SR53 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x53);
+	save->SR54 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x54);
+	save->SR55 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x55);
+	save->SR56 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x56);
+	save->SR57 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x57);
+	save->SR5A = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x5A);
+
 	/* PLL2 stuff */
-	save->SR69 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x69);
 	save->SR6E = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6E);
 	save->SR6F = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6F);
     }
 
     if (SMI_LYNXM_SERIES(pSmi->Chipset)) {
+	/* Save common registers */
+	save->CR30 = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30);
+	save->CR3A = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A);
+	for (i = 0; i < 15; i++) {
+	    save->CR90[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x90 + i);
+	}
+	for (i = 0; i < 14; i++) {
+	    save->CRA0[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0xA0 + i);
+	}
+
 	/* Save primary registers */
-	save->CR90[14] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E);
 	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, save->CR90[14] & ~0x20);
 
-	for (i = 0; i < 16; i++) {
-	    save->CR90[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x90 + i);
-	}
 	save->CR33 = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33);
-	save->CR3A = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A);
 	for (i = 0; i < 14; i++) {
 	    save->CR40[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40 + i);
 	}
+	save->CR9F = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9F);
 
 	/* Save secondary registers */
 	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, save->CR90[14] | 0x20);
@@ -251,15 +261,12 @@ SMILynx_Save(ScrnInfoPtr pScrn)
 	}
 	save->CR9F_2 = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9F);
 
-	/* Save common registers */
-	for (i = 0; i < 14; i++) {
-	    save->CRA0[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0xA0 + i);
-	}
-
 	/* PDR#1069 */
 	VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, save->CR90[14]);
+
     }
     else {
+	save->CR30 = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30);
 	save->CR33 = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33);
 	save->CR3A = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A);
 	for (i = 0; i < 14; i++) {
@@ -267,12 +274,6 @@ SMILynx_Save(ScrnInfoPtr pScrn)
 	}
     }
 
-    /* CZ 2.11.2001: for gamma correction (TODO: other chipsets?) */
-    if ((pSmi->Chipset == SMI_LYNX3DM) || (pSmi->Chipset == SMI_COUGAR3DR)) {
-	save->CCR66 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x66);
-    }
-    /* end CZ */
-
     save->DPR10 = READ_DPR(pSmi, 0x10);
     save->DPR1C = READ_DPR(pSmi, 0x1C);
     save->DPR20 = READ_DPR(pSmi, 0x20);
@@ -297,7 +298,6 @@ SMILynx_Save(ScrnInfoPtr pScrn)
     save->CPR00 = READ_CPR(pSmi, 0x00);
 
     if (!pSmi->ModeStructInit) {
-	/* XXX Should check the return value of vgaHWCopyReg() */
 	vgaHWCopyReg(&hwp->ModeReg, vgaSavePtr);
 	memcpy(pSmi->mode, save, sizeof(SMIRegRec));
 	pSmi->ModeStructInit = TRUE;
@@ -331,8 +331,8 @@ SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore)
 {
     SMIPtr	pSmi = SMIPTR(pScrn);
     int		i;
-    CARD8		tmp;
-    CARD32		offset;
+    CARD8	tmp;
+    CARD32	offset;
     vgaHWPtr	hwp = VGAHWPTR(pScrn);
     int		vgaIOBase  = hwp->IOBase;
     int		vgaCRIndex = vgaIOBase + VGA_CRTC_INDEX_OFFSET;
@@ -357,21 +357,25 @@ SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore)
 	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, tmp & ~0x03);
     } else {
 	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x17, restore->SR17);
-	tmp = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18) & ~0x1F;
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18, tmp |
-		      (restore->SR18 & 0x1F));
-	tmp = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, tmp & ~0x03);
-	tmp = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31) & ~0xC0;
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, tmp |
-		      (restore->SR31 & 0xC0));
-	tmp = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32) & ~0x07;
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32, tmp |
-		      (restore->SR32 & 0x07));
-	if (restore->SR6B != 0xFF) {
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6A, restore->SR6A);
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6B, restore->SR6B);
-	}
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18, restore->SR18);
+
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x20, restore->SR20);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, restore->SR21);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, restore->SR22);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23, restore->SR23);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x24, restore->SR24);
+
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, restore->SR31);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x32, restore->SR32);
+
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x66, restore->SR66);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x68, restore->SR68);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x69, restore->SR69);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6A, restore->SR6A);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6B, restore->SR6B);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, restore->SR6C);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, restore->SR6D);
+
 	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x81, restore->SR81);
 	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0xA0, restore->SRA0);
 
@@ -409,35 +413,26 @@ SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore)
 			  restore->CR90[14] & ~0x20);
 
 	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, restore->CR33);
-	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A, restore->CR3A);
 	    for (i = 0; i < 14; i++) {
 		VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40 + i,
 			      restore->CR40[i]);
 	    }
-	    for (i = 0; i < 16; i++) {
-		if (i != 14) {
-		    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x90 + i,
-				  restore->CR90[i]);
-		}
-	    }
-	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9E, restore->CR90[14]);
+	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x9F, restore->CR9F);
 
 	    /* Restore common registers */
-	    for (i = 0; i < 14; i++) {
-		VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0xA0 + i,
-			      restore->CRA0[i]);
-	    }
-	}
+	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, restore->CR30);
+	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A, restore->CR3A);
 
-	/* Restore the standard VGA registers */
-	if (xf86IsPrimaryPci(pSmi->PciInfo)) {
-	    vgaHWRestore(pScrn, vgaSavePtr, VGA_SR_CMAP | VGA_SR_FONTS);
-	}
+	    for (i = 0; i < 15; i++)
+		VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x90 + i,
+			      restore->CR90[i]);
 
-	if (restore->modeInit)
-	    vgaHWRestore(pScrn, vgaSavePtr, VGA_SR_ALL);
+	    for (i = 0; i < 14; i++)
+		VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0xA0 + i,
+			      restore->CRA0[i]);
 
-	if (!SMI_LYNXM_SERIES(pSmi->Chipset)) {
+	}else{
+	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x30, restore->CR30);
 	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, restore->CR33);
 	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x3A, restore->CR3A);
 	    for (i = 0; i < 14; i++) {
@@ -446,64 +441,36 @@ SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore)
 	    }
 	}
 
-	/* vclk1 */
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x68, restore->SR68);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6C, restore->SR6C);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6D, restore->SR6D);
-
 	if (pSmi->Dualhead) {
-
-	    /* TFT panel uses FIFO1, DSTN panel uses FIFO1 for upper panel and
-	     * FIFO2 for lower panel.  I don't have a DSTN panel, so it's untested.
-	     * -- AGD
-	     */
-
-	    /* PLL2 regs */
-
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x69, restore->SR69);
-
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6E, restore->SR6E);
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6F, restore->SR6F);
-
-	    /* setting SR21 bit 2 disables ZV circuitry,
-	     * if ZV is needed, SR21 = 0x20
-	     */
-	    /* enable DAC, PLL, etc. */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, restore->SR21);
-
-	    /* clear DPMS state */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, restore->SR22);
-
-	    /* enable virtual refresh and LCD and CRT outputs */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, restore->SR31);
-
-	    /* FIFO1 Read Offset */
+	    /* dualhead stuff */
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x40, restore->SR40);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x41, restore->SR41);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x42, restore->SR42);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x43, restore->SR43);
 	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x44, restore->SR44);
-	    /* FIFO2 Read Offset */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4B, restore->SR4B);
-	    /* FIFO1/2 Read Offset overflow */
-	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C, restore->SR4C);
-
-	    /* FIFO Write Offset */
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x45, restore->SR45);
 	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x48, restore->SR48);
 	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x49, restore->SR49);
-
-	    /* set FIFO levels */
 	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4A, restore->SR4A);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4B, restore->SR4B);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x4C, restore->SR4C);
 
-	    VGAOUT8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x33, restore->CR33);
-
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x50, restore->SR50);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x51, restore->SR51);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x52, restore->SR52);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x53, restore->SR53);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x54, restore->SR54);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x55, restore->SR55);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x56, restore->SR56);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x57, restore->SR57);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x5A, restore->SR5A);
+
+	    /* PLL2 stuff */
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6E, restore->SR6E);
+	    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x6F, restore->SR6F);
 	}
     }
 
-    /* CZ 2.11.2001: for gamma correction (TODO: other chipsets?) */
-    if ((pSmi->Chipset == SMI_LYNX3DM) || (pSmi->Chipset == SMI_COUGAR3DR)) {
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x66, restore->CCR66);
-    }
-    /* end CZ */
-
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x81, 0x00);
-
     /* Reset the graphics engine */
     WRITE_DPR(pSmi, 0x10, restore->DPR10);
     WRITE_DPR(pSmi, 0x1C, restore->DPR1C);
@@ -550,6 +517,7 @@ SMILynx_DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
 							  int flags)
 {
     SMIPtr	pSmi = SMIPTR(pScrn);
+    SMIRegPtr	mode = pSmi->mode;
     vgaHWPtr	hwp = VGAHWPTR(pScrn);
 
     ENTER();
@@ -558,21 +526,20 @@ SMILynx_DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
     if (pSmi->CurrentDPMS != PowerManagementMode) {
 	/* Read the required SR registers for the DPMS handler */
 	CARD8 SR01 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x01);
-	CARD8 SR23 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23);
 
 	switch (PowerManagementMode) {
 	    case DPMSModeOn:
 		SR01 &= ~0x20; /* Screen on */
-		SR23 &= ~0xC0; /* Disable chip activity detection */
+		mode->SR23 &= ~0xC0; /* Disable chip activity detection */
 		break;
 	    case DPMSModeStandby:
 	    case DPMSModeSuspend:
 	    case DPMSModeOff:
-		SR01 |= 0x20; /*Screen off*/
-		SR23  = (SR23 & ~0x07) | 0xD8; /*Enable chip activity detection
-						 Enable internal auto-standby mode
-					         Enable both IO Write and Host Memory write detect
-					         0 minutes timeout */
+		SR01 |= 0x20; /* Screen off */
+		mode->SR23 = (mode->SR23 & ~0x07) | 0xD8; /* Enable chip activity detection
+							     Enable internal auto-standby mode
+							     Enable both IO Write and Host Memory write detect
+							     0 minutes timeout */
 		break;
 	}
 
@@ -582,7 +549,7 @@ SMILynx_DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
 
 	/* Write the registers */
 	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x01, SR01);
-	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23, SR23);
+	VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23, mode->SR23);
 
 	/* Set the DPMS mode to every output and CRTC */
 	xf86DPMSSet(pScrn, PowerManagementMode, flags);
diff --git a/src/smilynx_output.c b/src/smilynx_output.c
index 40fe710..f9bd79f 100644
--- a/src/smilynx_output.c
+++ b/src/smilynx_output.c
@@ -39,35 +39,31 @@ SMILynx_OutputDPMS_crt(xf86OutputPtr output, int mode)
 {
     ScrnInfoPtr pScrn = output->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
-    vgaHWPtr	hwp = VGAHWPTR(pScrn);
-    CARD8 SR21, SR22, SR31;
+    SMIRegPtr reg = pSmi->mode;
+    vgaHWPtr hwp = VGAHWPTR(pScrn);
 
     ENTER();
 
-    SR21=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x21);
-    SR22=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x22);
-    SR31=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31);
-
     switch (mode) {
     case DPMSModeOn:
-	SR21 &= ~0x88; /* Enable DAC and color palette RAM */
-	SR31 |= 0x02; /* Enable CRT display*/
-	SR22 = (SR22 & ~0x30) | 0x00; /* Set DPMS state*/
+	reg->SR21 &= ~0x88; /* Enable DAC and color palette RAM */
+	reg->SR31 |= 0x02; /* Enable CRT display*/
+	reg->SR22 = (reg->SR22 & ~0x30) | 0x00; /* Set DPMS state*/
 	break;
     case DPMSModeStandby:
-	SR21 |= 0x88; /* Disable DAC and color palette RAM */
-	SR31 |= 0x02; /* Enable CRT display*/
-	SR22 = (SR22 & ~0x30) | 0x10; /* Set DPMS state*/
+	reg->SR21 |= 0x88; /* Disable DAC and color palette RAM */
+	reg->SR31 |= 0x02; /* Enable CRT display*/
+	reg->SR22 = (reg->SR22 & ~0x30) | 0x10; /* Set DPMS state*/
 	break;
     case DPMSModeSuspend:
-	SR21 |= 0x88; /* Disable DAC and color palette RAM */
-	SR31 |= 0x02; /* Enable CRT display*/
-	SR22 = (SR22 & ~0x30) | 0x20; /* Set DPMS state*/
+	reg->SR21 |= 0x88; /* Disable DAC and color palette RAM */
+	reg->SR31 |= 0x02; /* Enable CRT display*/
+	reg->SR22 = (reg->SR22 & ~0x30) | 0x20; /* Set DPMS state*/
 	break;
     case DPMSModeOff:
-	SR21 |= 0x88; /* Disable DAC and color palette RAM */
-	SR31 &= ~0x02; /* Disable CRT display*/
-	SR22 = (SR22 & ~0x30) | 0x30; /* Set DPMS state*/
+	reg->SR21 |= 0x88; /* Disable DAC and color palette RAM */
+	reg->SR31 &= ~0x02; /* Disable CRT display*/
+	reg->SR22 = (reg->SR22 & ~0x30) | 0x30; /* Set DPMS state*/
 	break;
     }
 
@@ -77,9 +73,9 @@ SMILynx_OutputDPMS_crt(xf86OutputPtr output, int mode)
     while (!(hwp->readST01(hwp) & 0x8)) ;
 
     /* Write the registers */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, SR21);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, SR22);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, SR31);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, reg->SR21);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, reg->SR22);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, reg->SR31);
 
     LEAVE();
 
@@ -91,35 +87,32 @@ SMILynx_OutputDPMS_lcd(xf86OutputPtr output, int mode)
 {
     ScrnInfoPtr pScrn = output->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
-    CARD8 SR21, SR31;
+    SMIRegPtr reg = pSmi->mode;
 
     ENTER();
 
-    SR21=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x21);
-    SR31=VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX,VGA_SEQ_DATA,0x31);
-
     switch (mode) {
     case DPMSModeOn:
 	if(pSmi->lcd == 2 /* LCD is DSTN */
 	   || pSmi->Dualhead /* Virtual Refresh is enabled */)
-	    SR21 &= ~0x10; /* Enable LCD framebuffer read operation and DSTN dithering engine */
+	    reg->SR21 &= ~0x10; /* Enable LCD framebuffer read operation and DSTN dithering engine */
 	if(pSmi->lcd == 2 /* LCD is DSTN */
 	   && !pSmi->Dualhead /* Virtual Refresh is disabled */)
-	    SR21 &= ~0x20; /* Enable LCD framebuffer write operation */
+	    reg->SR21 &= ~0x20; /* Enable LCD framebuffer write operation */
 
-	SR31 |= 0x01; /* Enable LCD display*/
+	reg->SR31 |= 0x01; /* Enable LCD display*/
 	break;
     case DPMSModeStandby:
     case DPMSModeSuspend:
     case DPMSModeOff:
-	SR21 |= 0x30; /* Disable LCD framebuffer r/w operation */
-	SR31 &= ~0x01; /* Disable LCD display*/
+	reg->SR21 |= 0x30; /* Disable LCD framebuffer r/w operation */
+	reg->SR31 &= ~0x01; /* Disable LCD display*/
 	break;
     }
 
     /* Write the registers */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, SR21);
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, SR31);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, reg->SR21);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x31, reg->SR31);
 
     LEAVE();
 
@@ -178,16 +171,16 @@ static xf86OutputStatus
 SMILynx_OutputDetect_crt(xf86OutputPtr output)
 {
     SMIPtr pSmi = SMIPTR(output->scrn);
-    vgaHWPtr	hwp = VGAHWPTR(output->scrn);
-    CARD8 SR21, SR7D;
+    SMIRegPtr mode = pSmi->mode;
+    vgaHWPtr hwp = VGAHWPTR(output->scrn);
+    CARD8 SR7D;
     Bool status;
 
     ENTER();
 
-    SR21 = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21);
     SR7D = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x7D);
 
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, SR21 & ~0x80); /* Enable DAC */
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, mode->SR21 & ~0x80); /* Enable DAC */
     VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x7B, 0x40); /* "TV and RAMDAC Testing Power", Green component */
     VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x7D, SR7D | 0x10); /* Enable monitor detect */
 
@@ -198,7 +191,7 @@ SMILynx_OutputDetect_crt(xf86OutputPtr output)
     status = MMIO_IN8(pSmi->IOBase, 0x3C2) & 0x10;
 
     /* Restore previous state */
-    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, SR21);
+    VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, mode->SR21);
     VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x7D, SR7D);
 
     if(status)