Unless there is a xorg.conf option, don't modify mclck neither mxclck.

  The option set_mclck was renamed to just MCLK, and a new MXCLCK option
was added for smi501/502 chips.
  Note that previously, on MSOC chips, the set_mclck option actually
changed mxclck, what is now done by the MXCLK option.
  The manpage was also update to reflect the options usage.
  A new SMI501_FindMemClock() function was added, as a possible
placeholder for choosing alternate clocks when programming MMIO 0x68.
But it should be noted that the smi 501 databook says:
Miscellaneous Timing
	Read/Write MMIO_base + 0x000068
	Power-on Default 0x00000000
	[...]
	5:4 Divider Output Frequency Selection for Second PLL.
		00: 336 MHz.
		01: 288 MHz.
		10: 240 MHz.
		11: 192 MHz.
while the 502 databook says:
	Miscellaneous Timing
	Read/Write MMIO_base + 0x000068
	Power-on Default 0b0000.00xx.0000.1001.0000.1001.0000.0000
	[...]
	5:4 Reserved These bits are reserved.
but still tells to refer to those bits.

1 files changed, 15 insertions, 9 deletions

diff --git a/man/siliconmotion.man b/man/siliconmotion.man
index 9211ff8..bc50756 100644
--- a/man/siliconmotion.man
+++ b/man/siliconmotion.man
@@ -131,16 +131,22 @@ The following video memory
 .B Options
 are supported:
 .TP
-.BI "Option \*qset_mclk\*q \*q" integer \*q
-sets the memory clock, where
-.I integer
-is in kHz, and
-.I integer
-<= 100000.  Default: probe the memory clock value,
-and use it at server start.
-
-
+.BI "Option \*qmclk\*q \*q" integer \*q
+Sets the memory clock. You must specify the units.  For example \fI50Mhz\fP
+is the same as \fI50000Khz\fP or \fI50000000Hz\fP.
+On MSOC chips this is the main clock source for all functional blocks, such
+as the 2D engine, GPIO, Video Engine, and DMA Engine. This option is only
+used for debugging purposes on MSOC chips.
+Default: probe the memory clock value, and use it at server start.
+.TP
+.BI "Option \*qmxclk\*q \*q" integer \*q
+Sets the memory clock. You must specify the units.  For example \fI50Mhz\fP
+is the same as \fI50000Khz\fP or \fI50000000Hz\fP.
+Clock source for the local SDRAM controller. This option is only available
+on MSOC chips and used only for debugging purposes.
+Default: probe the memory clock value, and use it at server start.
 .PP
+
 The following acceleration and graphics engine
 .B Options
 are supported: