Fix incorrect understanding of the pixel clock from specs.

  The clock that should be programmed is the bandwidth, and not the pixel
clock itself. Based on analysis of register contents, after "importing"
a slightly modified version of xf86ModeBandwidth() and properly converting
values, now it properly programs both, the LCD and a "clone" CRT or just
a secondary panel.

  Modes generated by either gtf or cvt correctly works.

  A (hopefully temporary) fallback was also added, and if the option
"UseFBDev" is used, the driver will not attempt to set/modify the
current video mode.

  TODO: Generate a modeline "on the fly", based on monitor configured
specs, or some set of defaults, so that it should not be required to
specify a modeline in xorg.conf.

1 files changed, 1 insertions, 0 deletions

diff --git a/src/smi.h b/src/smi.h
index cdd12d8..11bb060 100644
--- a/src/smi.h
+++ b/src/smi.h
@@ -266,6 +266,7 @@ typedef struct
     EntityInfoPtr	pEnt;
 
     Bool		IsSwitching; /* when switching modes */
+    Bool		UseFBDev;
 
 } SMIRec, *SMIPtr;