Unless there is a xorg.conf option, don't modify mclck neither mxclck.

  The option set_mclck was renamed to just MCLK, and a new MXCLCK option
was added for smi501/502 chips.
  Note that previously, on MSOC chips, the set_mclck option actually
changed mxclck, what is now done by the MXCLK option.
  The manpage was also update to reflect the options usage.
  A new SMI501_FindMemClock() function was added, as a possible
placeholder for choosing alternate clocks when programming MMIO 0x68.
But it should be noted that the smi 501 databook says:
Miscellaneous Timing
	Read/Write MMIO_base + 0x000068
	Power-on Default 0x00000000
	[...]
	5:4 Divider Output Frequency Selection for Second PLL.
		00: 336 MHz.
		01: 288 MHz.
		10: 240 MHz.
		11: 192 MHz.
while the 502 databook says:
	Miscellaneous Timing
	Read/Write MMIO_base + 0x000068
	Power-on Default 0b0000.00xx.0000.1001.0000.1001.0000.0000
	[...]
	5:4 Reserved These bits are reserved.
but still tells to refer to those bits.

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