Correct problems in clock setting.

  One clock must be changed at a time, first setting the pll value,
then waiting for 16ms (one vsync), then setting the divider/shift
values, and again waiting 16ms.
  Code was working after split of SMI501_ModeInit(), because some
clocks were already using system boot default, but would most likely
cause a crash when actually changing values (currently only p2_xxx
or v2_xxx is changed, but it would cause problems on some system where
the initial values don't match the ones set by the driver).

  TODO: Either don't change m2clk and mclk or ensure other values
work correctly (don't change because the kernel should already
have set those if a value other then the boot default should be
used).

0 files changed, 0 insertions, 0 deletions