Crt interface corrections.

  Correct wrong clock calculation for the 501 clock setting, that is used
for pre 502 panel interface and crt.
  Adds a few new programmable fields to MSOCRegRec:crt_display_ctl.
  Call SMI501_CrtcAdjustFrame() after adjusting a mode, instead of
before changing registers.

3 files changed, 31 insertions, 22 deletions

diff --git a/src/smi501_crtc.c b/src/smi501_crtc.c
index 18fa764..9802ba9 100644
--- a/src/smi501_crtc.c
+++ b/src/smi501_crtc.c
@@ -45,6 +45,7 @@ SMI501_CrtcVideoInit_lcd(xf86CrtcPtr crtc)
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
     MSOCRegPtr mode = pSmi->mode;
+    int		pitch, width;
 
     ENTER();
 
@@ -56,13 +57,13 @@ SMI501_CrtcVideoInit_lcd(xf86CrtcPtr crtc)
 	pScrn->bitsPerPixel == 8 ? 0 :
 	pScrn->bitsPerPixel == 16 ? 1 : 2;
 
-    int pitch = (crtc->rotatedData? crtc->mode.HDisplay : pScrn->displayWidth) * pSmi->Bpp;
-    pitch = (pitch + 15) & ~15;
+    pitch = (((crtc->rotatedData? crtc->mode.HDisplay : pScrn->displayWidth) *
+	      pSmi->Bpp) + 15) & ~15;
+    width = crtc->mode.HDisplay * pSmi->Bpp;
 
     /* >> 4 because of the "unused bits" that should be set to 0 */
-    /* FIXME this should be used for virtual size? */
     mode->panel_fb_width.f.offset = pitch >> 4;
-    mode->panel_fb_width.f.width = pitch >> 4;
+    mode->panel_fb_width.f.width = width >> 4;
 
     WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
     WRITE_SCR(pSmi, PANEL_FB_WIDTH, mode->panel_fb_width.value);
@@ -76,6 +77,7 @@ SMI501_CrtcVideoInit_crt(xf86CrtcPtr crtc)
     ScrnInfoPtr pScrn=crtc->scrn;
     SMIPtr pSmi = SMIPTR(pScrn);
     MSOCRegPtr mode = pSmi->mode;
+    int		pitch, width;
 
     ENTER();
 
@@ -87,13 +89,13 @@ SMI501_CrtcVideoInit_crt(xf86CrtcPtr crtc)
 	pScrn->bitsPerPixel == 8 ? 0 :
 	pScrn->bitsPerPixel == 16 ? 1 : 2;
 
-    int pitch = (crtc->rotatedData? crtc->mode.HDisplay : pScrn->displayWidth) * pSmi->Bpp;
-    pitch = (pitch + 15) & ~15;
+    pitch = (((crtc->rotatedData? crtc->mode.HDisplay : pScrn->displayWidth) *
+	      pSmi->Bpp) + 15) & ~15;
+    width = crtc->mode.HDisplay * pSmi->Bpp;
 
     /* >> 4 because of the "unused bits" that should be set to 0 */
-    /* FIXME this should be used for virtual size? */
     mode->crt_fb_width.f.offset = pitch >> 4;
-    mode->crt_fb_width.f.width = pitch >> 4;
+    mode->crt_fb_width.f.width = width >> 4;
 
 
     WRITE_SCR(pSmi, CRT_DISPLAY_CTL, mode->crt_display_ctl.value);
@@ -122,9 +124,11 @@ SMI501_CrtcAdjustFrame(xf86CrtcPtr crtc, int x, int y)
 
     if(crtc == crtcConf->crtc[0]){
 	mode->panel_fb_address.f.address = Base >> 4;
+	mode->panel_fb_address.f.pending = 1;
 	WRITE_SCR(pSmi, PANEL_FB_ADDRESS, mode->panel_fb_address.value);
     }else{
 	mode->crt_fb_address.f.address = Base >> 4;
+	mode->crt_fb_address.f.pending = 1;
 	WRITE_SCR(pSmi, CRT_FB_ADDRESS, mode->crt_fb_address.value);
     }
 
@@ -153,7 +157,6 @@ SMI501_CrtcModeSet_lcd(xf86CrtcPtr crtc,
     /* Initialize the display controller */
 
     SMI501_CrtcVideoInit_lcd(crtc);
-    SMI501_CrtcAdjustFrame(crtc, x,y);
 
     /* P2CLK have dividers 1, 3 and 5 */
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, VERBLEV,
@@ -237,6 +240,7 @@ SMI501_CrtcModeSet_lcd(xf86CrtcPtr crtc,
 
 
     SMI501_WriteMode_lcd(pScrn,mode);
+    SMI501_CrtcAdjustFrame(crtc, x, y);
 
     LEAVE();
 }
@@ -257,7 +261,6 @@ SMI501_CrtcModeSet_crt(xf86CrtcPtr crtc,
     /* Initialize the display controller */
 
     SMI501_CrtcVideoInit_crt(crtc);
-    SMI501_CrtcAdjustFrame(crtc, x,y);
 
     /* V2CLK have dividers 1 and 3 */
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, VERBLEV,
@@ -275,11 +278,9 @@ SMI501_CrtcModeSet_crt(xf86CrtcPtr crtc,
     mode->crt_display_ctl.f.select = 1;
     mode->crt_display_ctl.f.enable = 1;
 
-    /* FIXME if non clone dual head, and secondary, need to
-     * properly set crt fb address ... */
-    mode->crt_fb_address.f.address = 0;
     mode->crt_fb_address.f.mextern = 0;	/* local memory */
-    mode->crt_fb_address.f.pending = 0;	/* FIXME required? */
+    mode->crt_fb_address.f.timing = 1;
+    mode->crt_display_ctl.f.blank = 0;
 
     /* 0 means pulse high */
     mode->crt_display_ctl.f.hsync = !(xf86mode->Flags & V_PHSYNC);
@@ -300,6 +301,7 @@ SMI501_CrtcModeSet_crt(xf86CrtcPtr crtc,
 	xf86mode->HSyncStart;
 
     SMI501_WriteMode_crt(pScrn,mode);
+    SMI501_CrtcAdjustFrame(crtc, x, y);
 
     LEAVE();
 }
diff --git a/src/smi_501.c b/src/smi_501.c
index 26669cf..f973ed7 100644
--- a/src/smi_501.c
+++ b/src/smi_501.c
@@ -206,13 +206,12 @@ SMI501_HWInit(ScrnInfoPtr pScrn)
 	    break;
     }
 
-
-    /* FIXME: No dual head setup, and in this case, crt may
-     * just be another panel */
-    /* crt clones panel */
+    /* By default, crt clones panel */
     mode->crt_display_ctl.f.enable = 1;
     /* 0: select panel - 1: select crt */
     mode->crt_display_ctl.f.select = 0;
+    /* FIXME correct? */
+    mode->crt_display_ctl.f.timing = 0;
 
     SMI501_WriteMode_common(pScrn, mode);
 
@@ -382,6 +381,7 @@ SMI501_FindClock(double clock, int32_t max_divider, Bool has1xclck,
 		    if (fabs(diff) < best) {
 			*x2_shift = shift;
 			*x2_divider = divider == 1 ? 0 : divider == 3 ? 1 : 2;
+			*x2_select = mclk == 12 * 24 * 1000.0 ? 0 : 1;
 			*x2_1xclck = xclck == 0;
 
 			/* Remember best diff */
@@ -392,8 +392,6 @@ SMI501_FindClock(double clock, int32_t max_divider, Bool has1xclck,
 	}
     }
 
-    *x2_select = mclk == 12 * 24 * 1000.0 ? 0 : 1;
-
     xf86ErrorFVerb(VERBLEV,
 		   "\tMatching clock %5.2f, diff %5.2f (%d/%d/%d/%d)\n",
 		   ((*x2_select ? 14 : 12) * 24 * 1000.0) /
diff --git a/src/smi_501.h b/src/smi_501.h
index e42606a..1d68ebe 100644
--- a/src/smi_501.h
+++ b/src/smi_501.h
@@ -634,9 +634,16 @@ typedef struct _MSOCRegRec {
      *	2:2	CRT Graphics Plane Enable.
      *		0: Disable CRT Graphics plane.
      *		1: Enable CRT Graphics plane.
+     *	8:8	Enable CRT Timing.
+     *		0: Disable CRT timing.
+     *		1: Enable CRT timing.
      *	9:9:	CRT Data Select.
      *		0: CRT will display panel data.
      *		1: CRT will display CRT data.
+     *	10:10	CRT Data Blanking.
+     *		0: CRT will show pixels.
+     *		1: CRT will be blank.
+     *	11:11	Vertical Sync. This bit is read only.
      *	12:12	Horizontal Sync Pulse Phase Select.
      *		0: Horizontal sync pulse active high.
      *		1: Horizontal sync pulse active low.
@@ -648,9 +655,11 @@ typedef struct _MSOCRegRec {
 	struct {
 	    int32_t	format		: bits( 0,  1);
 	    int32_t	enable		: bits( 2,  2);
-	    int32_t	u0		: bits( 3,  8);
+	    int32_t	u0		: bits( 3,  7);
+	    int32_t	timing		: bits( 8,  8);
 	    int32_t	select		: bits( 9,  9);
-	    int32_t	u1		: bits(10, 11);
+	    int32_t	blank		: bits(10, 10);
+	    int32_t	sync		: bits(11, 11);
 	    int32_t	hsync		: bits(12, 12);
 	    int32_t	vsync		: bits(13, 13);
 	} f;