diff options
| -rw-r--r-- | src/Makefile.am | 2 | ||||
| -rw-r--r-- | src/regsmi.h | 164 | ||||
| -rw-r--r-- | src/smi.h | 4 | ||||
| -rw-r--r-- | src/smi_501.c | 906 | ||||
| -rw-r--r-- | src/smi_501.h | 1315 |
5 files changed, 2386 insertions, 5 deletions
diff --git a/src/Makefile.am b/src/Makefile.am index 7cdf9ab..63510f5 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -30,6 +30,8 @@ siliconmotion_drv_ladir = @moduledir@/drivers siliconmotion_drv_la_SOURCES = \ regsmi.h \ + smi_501.c \ + smi_501.h \ smi_accel.c \ smi_xaa.c \ smi_exa.c \ diff --git a/src/regsmi.h b/src/regsmi.h index c5af8cc..3a6d0e1 100644 --- a/src/regsmi.h +++ b/src/regsmi.h @@ -30,11 +30,16 @@ authorization from the XFree86 Project and SIlicon Motion. #ifndef _REGSMI_H #define _REGSMI_H +#ifndef PCI_CHIP_SMI501 +#define PCI_CHIP_SMI501 0x0501 +#endif + #define SMI_LYNX_SERIES(chip) ((chip & 0xF0F0) == 0x0010) #define SMI_LYNX3D_SERIES(chip) ((chip & 0xF0F0) == 0x0020) #define SMI_COUGAR_SERIES(chip) ((chip & 0xF0F0) == 0x0030) #define SMI_LYNXEM_SERIES(chip) ((chip & 0xFFF0) == 0x0710) #define SMI_LYNXM_SERIES(chip) ((chip & 0xFF00) == 0x0700) +#define SMI_MSOC_SERIES(chip) ((chip & 0xFF00) == 0x0500) /* Chip tags */ #define PCI_SMI_VENDOR_ID PCI_VENDOR_SMI @@ -46,6 +51,10 @@ authorization from the XFree86 Project and SIlicon Motion. #define SMI_LYNXEMplus PCI_CHIP_SMI712 #define SMI_LYNX3DM PCI_CHIP_SMI720 #define SMI_COUGAR3DR PCI_CHIP_SMI731 +#define SMI_MSOC PCI_CHIP_SMI501 + +/* Mobile-System-on-a-Chip */ +#define IS_MSOC(pSmi) ((pSmi)->Chipset == SMI_MSOC) /* I/O Functions */ static __inline__ CARD8 @@ -105,6 +114,20 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define READ_CPR(pSmi, cpr) MMIO_IN32(pSmi->CPRBase, cpr) #define WRITE_FPR(pSmi, fpr, data) MMIO_OUT32(pSmi->FPRBase, fpr, data); DEBUG((VERBLEV, "FPR%02X = %08X\n", fpr, data)) #define READ_FPR(pSmi, fpr) MMIO_IN32(pSmi->FPRBase, fpr) +#define WRITE_DCR(pSmi, dcr, data) MMIO_OUT32(pSmi->DCRBase, dcr, data); DEBUG((VERBLEV, "DCR%02X = %08X\n", dcr, data)) +#define READ_DCR(pSmi, dcr) MMIO_IN32(pSmi->DCRBase, dcr) +#define WRITE_SCR(pSmi, scr, data) MMIO_OUT32(pSmi->SCRBase, scr, data); DEBUG((VERBLEV, "SCR%02X = %08X\n", scr, data)) +#define READ_SCR(pSmi, scr) MMIO_IN32(pSmi->SCRBase, scr) + +#define CHECK_SECONDARY(pSmi) \ + if (IS_MSOC(pSmi) && !(pSmi)->IsSecondary) { \ + WRITE_DPR(pSmi, 0x40, 0); \ + WRITE_DPR(pSmi, 0x44, 0); \ + } \ + else { \ + WRITE_DPR(pSmi, 0x40, pScrn->fbOffset / 16 << 4); \ + WRITE_DPR(pSmi, 0x44, pScrn->fbOffset / 16 << 4); \ + } /* 2D Engine commands */ #define SMI_TRANSPARENT_SRC 0x00000100 @@ -152,15 +175,24 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define MAXLOOP 0x100000 /* timeout value for engine waits */ -#define ENGINE_IDLE() \ - ((VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x08) == 0) -#define FIFO_EMPTY() \ - ((VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x10) != 0) +#define ENGINE_IDLE() \ + IS_MSOC(pSmi) ? \ + (READ_SCR(pSmi, SCR00) & 0x00080000) == 0 : \ + (VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x08) == 0 +#define FIFO_EMPTY() \ + IS_MSOC(pSmi) ? \ + READ_SCR(pSmi, SCR00) & 0x00100000 : \ + VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x10 /* Wait until "v" queue entries are free */ +/**** FIXME + **** This is completely ilogical. Argument "v" is ignored, and + **** pSmi->NoPCIRetry defaults to true (but on smi sources this + **** macro is a noop and will get stuck on engine reset timeouts if enabled...) + ***/ #define WaitQueue(v) \ do { \ - if (pSmi->NoPCIRetry) { \ + if (!IS_MSOC(pSmi) && pSmi->NoPCIRetry) { \ int loop = MAXLOOP; mem_barrier(); \ while (!FIFO_EMPTY()) \ if (loop-- == 0) break; \ @@ -240,6 +272,128 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define FPR15C_MASK_HWCADDREN 0xFFFF0000 #define FPR15C_MASK_HWCENABLE 0x80000000 +/* SM501 System Configuration Registers */ +#define SCR00 0x0000 +#define SCR04 0x0004 +#define SCR08 0x0008 +#define SCR0C 0x000C +#define SCR10 0x0010 +#define SCR10_LOCAL_MEM_SIZE 0x0000E000 +#define SCR10_LOCAL_MEM_SIZE_SHIFT 13 +#define SCR14 0x0014 +#define SCR18 0x0018 +#define SCR1C 0x001C +#define SCR20 0x0020 +#define SCR24 0x0024 +#define SCR28 0x0028 +#define SCR2C 0x002C +#define SCR30 0x0030 +#define SCR34 0x0034 +#define SCR38 0x0038 +#define SCR3C 0x003C +#define SCR40 0x0040 +#define SCR44 0x0044 +#define SCR48 0x0048 +#define SCR4C 0x004C +#define SCR50 0x0050 +#define SCR54 0x0054 +#define SCR58 0x0058 +#define SCR5C 0x005C +#define SCR60 0x0060 +#define SCR64 0x0064 +#define SCR68 0x0068 +#define SCR6C 0x006C + +/* SM501 Panel Graphics Control */ +#define DCR00 0x0000 +#define DCR04 0x0004 +#define DCR08 0x0008 +#define DCR0C 0x000C +#define DCR10 0x0010 +#define DCR14 0x0014 +#define DCR18 0x0018 +#define DCR1C 0x001C +#define DCR20 0x0020 +#define DCR24 0x0024 +#define DCR28 0x0028 +#define DCR2c 0x002c +#define DCR30 0x0030 +#define DCR34 0x0034 + +/* SM 501 Video Control */ +#define DCR40 0x0040 +#define DCR44 0x0044 +#define DCR48 0x0048 +#define DCR4C 0x004C +#define DCR50 0x0050 +#define DCR54 0x0054 +#define DCR58 0x0058 +#define DCR5C 0x005C +#define DCR60 0x0060 +#define DCR64 0x0064 +#define DCR68 0x0068 + +/* SM501 Video Alpha Control */ +#define DCR80 0x0080 +#define DCR84 0x0084 +#define DCR88 0x0088 +#define DCR8C 0x008C +#define DCR90 0x0090 +#define DCR94 0x0094 +#define DCR98 0x0098 +#define DCR9C 0x009C +#define DCRA0 0x00A0 +#define DCRA4 0x00A4 + +/* SM501 Panel Cursor Control */ +#define DCRF0 0x00F0 +#define DCRF4 0x00F4 +#define DCRF8 0x00F8 +#define DCRFC 0x00FC + +/* SM 501 Alpha Control */ +#define DCR100 0x0100 +#define DCR104 0x0104 +#define DCR108 0x0108 +#define DCR10C 0x010C +#define DCR110 0x0110 +#define DCR114 0x0114 +#define DCR118 0x0118 + +/* SM 501 CRT Graphics Control */ +#define DCR200 0x0200 +#define DCR200_CRT_BLANK 0x00000400 +#define DCR200_CRT_GRAPHICS_PLN_FMT 0x00000003 +#define CRT_GRAPHICS_PLN_FMT_8 0x00 +#define CRT_GRAPHICS_PLN_FMT_16 0x01 +#define CRT_GRAPHICS_PLN_FMT_32 0x10 +#define DCR204 0x0204 +#define DCR208 0x0208 +#define DCR20C 0x020C +#define DCR210 0x0210 +#define DCR214 0x0214 +#define DCR218 0x0218 +#define DCR21C 0x021C +#define DCR220 0x0220 +#define DCR224 0x0224 + +/* SM 501 CRT Cursor Control */ +#define DCR230 0x0230 +#define DCR234 0x0234 +#define DCR238 0x0238 +#define DCR23C 0x023C + +/* SM 501 Palette Ram */ +#define DCR400 0x0400 /* Panel */ +#define DCR800 0x0800 /* Video */ +#define DCRC00 0x0C00 /* CRT */ + +/* HWCursor definitons for Panel AND CRT */ +#define SMI501_MASK_HWCENABLE 0x80000000 +#define SMI501_MASK_MAXBITS 0x000007FF +#define SMI501_MASK_BOUNDARY 0x00000800 +#define SMI501_HWCFBADDR_MASK 0x0CFFFFFF + /* panel sizes returned by the bios */ #define PANEL_640x480 0x00 @@ -145,6 +145,8 @@ typedef struct CARD8 * VPRBase; /* Base of VPR registers */ CARD8 * CPRBase; /* Base of CPR registers */ CARD8 * FPRBase; /* Base of FPR registers - for 0730 chipset */ + CARD8 * DCRBase; /* Base of DCR registers - for 0501 chipset */ + CARD8 * SCRBase; /* Base of SCR registers - for 0501 chipset */ CARD8 * DataPortBase; /* Base of data port */ int DataPortSize; /* Size of data port */ CARD8 * IOBase; /* Base of MMIO VGA ports */ @@ -259,6 +261,8 @@ typedef struct CARD8 DACmask; Bool Dualhead; + Bool IsSecondary; + EntityInfoPtr pEnt; Bool IsSwitching; /* when switching modes */ diff --git a/src/smi_501.c b/src/smi_501.c new file mode 100644 index 0000000..e41ab84 --- /dev/null +++ b/src/smi_501.c @@ -0,0 +1,906 @@ +/* Header: //Mercury/Projects/archives/XFree86/4.0/smi_driver.c-arc 1.42 03 Jan 2001 13:52:16 Frido $ */ + +/* +Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. +Copyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- +NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of The XFree86 Project and +Silicon Motion shall not be used in advertising or otherwise to promote the +sale, use or other dealings in this Software without prior written +authorization from The XFree86 Project or Silicon Motion. +*/ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/siliconmotion/smi_driver.c,v 1.30 2003/04/23 21:51:44 tsi Exp $ */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86Resources.h" +#include "xf86RAC.h" +#include "xf86DDC.h" +#include "xf86int10.h" +#include "vbe.h" +#include "shadowfb.h" + +#include "smi.h" +#include "smi_501.h" +#include "regsmi.h" + +#include "globals.h" +#define DPMS_SERVER +#include <X11/extensions/dpms.h> + + +/* + * Forward definitions for the functions that make up the driver. + */ +static void panelPowerSequence(SMIPtr pSmi, panel_state_t on_off, int vsync_delay); + +/* + * Add comment here about this module. + */ + +/* Mode table. */ +mode_table_t mode_table[] = { + /*---------------------------------------------------------------------------------------- + * H. H. H. H. H. V. V. V. V. V. Pixel H. V. + * tot. disp. sync sync sync tot. disp. sync sync sinc clock freq. freq. + * end start wdth polarity end start hght polarity + *---------------------------------------------------------------------------------------*/ + + /* 640 x 480 */ + { 800, 640, 656, 96, NEGATIVE, 525, 480, 490, 2, NEGATIVE, 25175000, 31469, 60 }, + { 832, 640, 664, 40, NEGATIVE, 520, 480, 489, 3, NEGATIVE, 31500000, 37861, 72 }, + { 840, 640, 656, 64, NEGATIVE, 500, 480, 481, 3, NEGATIVE, 31500000, 37500, 75 }, + { 832, 640, 696, 56, NEGATIVE, 509, 480, 481, 3, NEGATIVE, 36000000, 43269, 85 }, + + /* 800 x 600 */ + { 1024, 800, 824, 72, POSITIVE, 625, 600, 601, 2, POSITIVE, 36000000, 35156, 56 }, + { 1056, 800, 840, 128, POSITIVE, 628, 600, 601, 4, POSITIVE, 40000000, 37879, 60 }, + { 1040, 800, 856, 120, POSITIVE, 666, 600, 637, 6, POSITIVE, 50000000, 48077, 72 }, + { 1056, 800, 816, 80, POSITIVE, 625, 600, 601, 3, POSITIVE, 49500000, 46875, 75 }, + { 1048, 800, 832, 64, POSITIVE, 631, 600, 601, 3, POSITIVE, 56250000, 53674, 85 }, + + /* 1024 x 768*/ + { 1344, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 65000000, 48363, 60 }, + { 1328, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 75000000, 56476, 70 }, + { 1312, 1024, 1040, 96, POSITIVE, 800, 768, 769, 3, POSITIVE, 78750000, 60023, 75 }, + { 1376, 1024, 1072, 96, POSITIVE, 808, 768, 769, 3, POSITIVE, 94500000, 68677, 85 }, + + /* End of table. */ + { 0, 0, 0, 0, NEGATIVE, 0, 0, 0, 0, NEGATIVE, 0, 0, 0 }, +}; + + +/********************************************************************** + * regRead32 + * Read the value of the 32-bit register specified by nOffset + **********************************************************************/ +unsigned int +regRead32(SMIPtr pSmi, unsigned int nOffset) +{ + unsigned int result; + + result = READ_SCR(pSmi, nOffset); + + return (result); +} + +/********************************************************************** + * regWrite32 + * Write the 32-bit value, nData, to the 32-bit register specified by + * nOffset + **********************************************************************/ +void +regWrite32(SMIPtr pSmi, unsigned int nOffset, unsigned int nData) +{ + WRITE_SCR(pSmi, nOffset, nData); +} + + +/* Perform a rounded division. */ +int +roundDiv(int num, int denom) +{ + /* n / d + 1 / 2 = (2n + d) / 2d */ + return (2 * num + denom) / (2 * denom); +} + +/* Finds clock closest to the requested. */ +int +findClock(int requested_clock, clock_select_t *clock, display_t display) +{ + int mclk; + int divider, shift; + int best_diff = 999999999; + + /* Try 288MHz and 336MHz clocks. */ + for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { + /* For CRT, try dividers 1 and 3, for panel, try divider 5 as well. */ + for (divider = 1; divider <= (display == PANEL ? 5 : 3); divider += 2) { + /* Try all 8 shift values. */ + for (shift = 0; shift < 8; shift++) { + /* Calculate difference with requested clock. */ + int diff = roundDiv(mclk, (divider << shift)) - requested_clock; + if (diff < 0) + diff = -diff; + + /* If the difference is less than the current, use it. */ + if (diff < best_diff) { + /* Store best difference. */ + best_diff = diff; + + /* Store clock values. */ + clock->mclk = mclk; + clock->divider = divider; + clock->shift = shift; + } + } + } + } + + /* Return best clock. */ + return clock->mclk / (clock->divider << clock->shift); +} + + +/* Finds the requested mode in the mode table. */ +mode_table_t * +findMode(mode_table_t *mode_table, int width, int height, int refresh_rate) +{ + /* Walk the entire mode table. */ + while (mode_table->pixel_clock != 0) { + /* If this mode matches the requested mode, return it! */ + if (mode_table->horizontal_display_end == width && + mode_table->vertical_display_end == height && + mode_table->vertical_frequency == refresh_rate) + return (mode_table); + + /* Next entry in the mode table. */ + mode_table++; + } + + /* No mode found. */ + return (NULL); +} + +/* Converts the VESA timing into Voyager timing. */ +void +adjustMode(mode_table_t *vesaMode, mode_table_t *mode, display_t display) +{ + int blank_width, sync_start, sync_width; + clock_select_t clock; + + /* Calculate the VESA line and screen frequencies. */ + vesaMode->horizontal_frequency = roundDiv(vesaMode->pixel_clock, + vesaMode->horizontal_total); + vesaMode->vertical_frequency = roundDiv(vesaMode->horizontal_frequency, + vesaMode->vertical_total); + + /* Calculate the sync percentages of the VESA mode. */ + blank_width = vesaMode->horizontal_total - vesaMode->horizontal_display_end; + sync_start = roundDiv((vesaMode->horizontal_sync_start - + vesaMode->horizontal_display_end) * 100, blank_width); + sync_width = roundDiv(vesaMode->horizontal_sync_width * 100, blank_width); + + /* Copy VESA mode into Voyager mode. */ + *mode = *vesaMode; + + /* Find the best pixel clock. */ + mode->pixel_clock = findClock(vesaMode->pixel_clock * 2, + &clock, display) / 2; + + /* Calculate the horizontal total based on the pixel clock and VESA line + * frequency. */ + mode->horizontal_total = roundDiv(mode->pixel_clock, + vesaMode->horizontal_frequency); + + /* Calculate the sync start and width based on the VESA percentages. */ + blank_width = mode->horizontal_total - mode->horizontal_display_end; + mode->horizontal_sync_start = mode->horizontal_display_end + + roundDiv(blank_width * sync_start, 100); + mode->horizontal_sync_width = roundDiv(blank_width * sync_width, 100); + + /* Calculate the line and screen frequencies. */ + mode->horizontal_frequency = roundDiv(mode->pixel_clock, + mode->horizontal_total); + mode->vertical_frequency = roundDiv(mode->horizontal_frequency, + mode->vertical_total); +} + +/* Fill the register structure. */ +void +setModeRegisters(reg_table_t *register_table, mode_table_t *mode, + display_t display, int bpp, int fbPitch) +{ + clock_select_t clock; + + memset(&clock, 0, sizeof(clock)); + + /* Calculate the clock register values. */ + findClock(mode->pixel_clock * 2, &clock, display); + + if (display == PANEL) { + /* Set clock value for panel. */ + register_table->clock = + (clock.mclk == 288000000 ? + FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 288) : + FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 336)) | + (clock.divider == 1 ? + FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 1) : + (clock.divider == 3 ? + FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 3) : + FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 5))) | + FIELD_VALUE(0, CURRENT_POWER_CLOCK, P2XCLK_SHIFT, clock.shift); + + /* Set control register value. */ + register_table->control = + (mode->vertical_sync_polarity == POSITIVE ? + FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH) : + FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW)) | + (mode->horizontal_sync_polarity == POSITIVE ? + FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH) : + FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW)) | + FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE) | + FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE) | + (bpp == 8 ? + FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 8) : + (bpp == 16 ? + FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 16) : + FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 32))); + + /* Set timing registers. */ + register_table->horizontal_total = + FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, + mode->horizontal_total - 1) | + FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, + mode->horizontal_display_end - 1); + + register_table->horizontal_sync = + FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, + mode->horizontal_sync_width) | + FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, + mode->horizontal_sync_start - 1); + + register_table->vertical_total = + FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, + mode->vertical_total - 1) | + FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, + mode->vertical_display_end - 1); + + register_table->vertical_sync = + FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, + mode->vertical_sync_height) | + FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, + mode->vertical_sync_start - 1); + } + else { + /* Set clock value for CRT. */ + register_table->clock = + (clock.mclk == 288000000 ? + FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 288) : + FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 336)) | + (clock.divider == 1 ? + FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 1) : + FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 3)) | + FIELD_VALUE(0, CURRENT_POWER_CLOCK, V2XCLK_SHIFT, clock.shift); + + /* Set control register value.*/ + register_table->control = + (mode->vertical_sync_polarity == POSITIVE ? + FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH) : + FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW)) | + (mode->horizontal_sync_polarity == POSITIVE ? + FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH) : + FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW)) | + FIELD_SET(0, CRT_DISPLAY_CTRL, SELECT, CRT) | + FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE) | + FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE) | + (bpp == 8 ? + FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 8) : + (bpp == 16 ? + FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 16) : + FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 32))); + + /* Set timing registers. */ + register_table->horizontal_total = + FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, + mode->horizontal_total - 1) | + FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, + mode->horizontal_display_end - 1); + + register_table->horizontal_sync = + FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, + mode->horizontal_sync_width) | + FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, + mode->horizontal_sync_start - 1); + + register_table->vertical_total = + FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, + mode->vertical_total - 1) | + FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, + mode->vertical_display_end - 1); + register_table->vertical_sync = + FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, + mode->vertical_sync_height) | + FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, + mode->vertical_sync_start - 1); + } + + /* Set up framebuffer pitch, from passed in value */ + register_table->fb_width = mode->horizontal_display_end * (bpp / 8); + register_table->fb_width = fbPitch; + + /* Calculate frame buffer width and height. */ + register_table->width = mode->horizontal_display_end; + register_table->height = mode->vertical_display_end; + + /* Save display type. */ + register_table->display = display; +} + +/* Program the mode with the registers specified. */ +void +programMode(SMIPtr pSmi, reg_table_t *register_table) +{ + unsigned int value, gate, clock; + unsigned int palette_ram; + unsigned int fb_size, offset; + + /* Get current power configuration. */ + gate = regRead32(pSmi, CURRENT_POWER_GATE); + gate |= 0x08; /* Enable power to 2D engine */ + gate = FIELD_SET(gate, CURRENT_POWER_GATE, CSC, ENABLE); + gate = FIELD_SET(gate, CURRENT_POWER_GATE, ZVPORT, ENABLE); + gate = FIELD_SET(gate, CURRENT_POWER_GATE, GPIO_PWM_I2C, ENABLE); + + clock = regRead32(pSmi, CURRENT_POWER_CLOCK); + + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 336); + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 3); + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 0); + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SELECT, 336); + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_DIVIDER, 1); + clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SHIFT, 1); + + /* Program panel. */ + if (register_table->display == PANEL) { + /* Program clock, enable display controller. */ + gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE); + clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_SELECT) & + FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_DIVIDER) & + FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_SHIFT); + setPower(pSmi, gate, clock | register_table->clock); + + /* Calculate frame buffer address. */ + value = 0; + fb_size = register_table->fb_width * register_table->height; + if (FIELD_GET(regRead32(pSmi, CRT_DISPLAY_CTRL), + CRT_DISPLAY_CTRL, + PLANE) == CRT_DISPLAY_CTRL_PLANE_ENABLE) { + value = FIELD_GET(regRead32(pSmi, CRT_FB_ADDRESS), + CRT_FB_ADDRESS, ADDRESS); + if (fb_size < value) + value = 0; + else + value += FIELD_GET(regRead32(pSmi, CRT_FB_WIDTH), + CRT_FB_WIDTH, OFFSET) * + (FIELD_GET(regRead32(pSmi, CRT_VERTICAL_TOTAL), + CRT_VERTICAL_TOTAL, DISPLAY_END) + 1); + } + + /* Program panel registers. */ + regWrite32(pSmi, PANEL_FB_ADDRESS, + FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, PENDING) | + FIELD_SET(0, PANEL_FB_ADDRESS, EXT, LOCAL) | + FIELD_VALUE(0, PANEL_FB_ADDRESS, ADDRESS, value)); + + regWrite32(pSmi, PANEL_FB_WIDTH, + FIELD_VALUE(0, PANEL_FB_WIDTH, WIDTH, + register_table->fb_width) | + FIELD_VALUE(0, PANEL_FB_WIDTH, OFFSET, + register_table->fb_width)); + + regWrite32(pSmi, PANEL_WINDOW_WIDTH, + FIELD_VALUE(0, PANEL_WINDOW_WIDTH, WIDTH, + register_table->width) | + FIELD_VALUE(0, PANEL_WINDOW_WIDTH, X, 0)); + + regWrite32(pSmi, PANEL_WINDOW_HEIGHT, + FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, HEIGHT, + register_table->height) | + FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, Y, 0)); + + regWrite32(pSmi, PANEL_PLANE_TL, + FIELD_VALUE(0, PANEL_PLANE_TL, TOP, 0) | + FIELD_VALUE(0, PANEL_PLANE_TL, LEFT, 0)); + + regWrite32(pSmi, PANEL_PLANE_BR, + FIELD_VALUE(0, PANEL_PLANE_BR, BOTTOM, + register_table->height - 1) | + FIELD_VALUE(0, PANEL_PLANE_BR, RIGHT, + register_table->width - 1)); + + regWrite32(pSmi, PANEL_HORIZONTAL_TOTAL, + register_table->horizontal_total); + regWrite32(pSmi, PANEL_HORIZONTAL_SYNC, + register_table->horizontal_sync); + regWrite32(pSmi, PANEL_VERTICAL_TOTAL, + register_table->vertical_total); + regWrite32(pSmi, PANEL_VERTICAL_SYNC, + register_table->vertical_sync); + + /* Program panel display control register. */ + value = regRead32(pSmi, PANEL_DISPLAY_CTRL) & + FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) & + FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) & + FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) & + FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE) & + FIELD_CLEAR(PANEL_DISPLAY_CTRL, FORMAT); + + regWrite32(pSmi, PANEL_DISPLAY_CTRL, value | register_table->control); + + /* Palette RAM. */ + palette_ram = PANEL_PALETTE_RAM; + + /* Turn on panel. */ + panelPowerSequence(pSmi, PANEL_ON, 4); + + regWrite32(pSmi, MISC_CTRL, + FIELD_SET (regRead32 (pSmi, MISC_CTRL), MISC_CTRL, + DAC_POWER, ENABLE)); + regWrite32(pSmi, CRT_DISPLAY_CTRL, + FIELD_SET (regRead32 (pSmi, CRT_DISPLAY_CTRL), + CRT_DISPLAY_CTRL, SELECT, PANEL)); + } + + /* Program CRT. */ + else { + /* Program clock, enable display controller. */ + gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE); + clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SELECT) & + FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_DIVIDER) & + FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SHIFT); + + setPower(pSmi, gate, clock | register_table->clock); + + /* Turn on DAC. */ + regWrite32(pSmi, MISC_CTRL, FIELD_SET(regRead32(pSmi, MISC_CTRL), + MISC_CTRL, DAC_POWER, ENABLE)); + + /* Calculate frame buffer address. */ + value = 0; + fb_size = register_table->fb_width * register_table->height; + if (FIELD_GET(regRead32(pSmi, PANEL_DISPLAY_CTRL), + PANEL_DISPLAY_CTRL, + PLANE) == PANEL_DISPLAY_CTRL_PLANE_ENABLE) { + value = FIELD_GET(regRead32(pSmi, PANEL_FB_ADDRESS), + PANEL_FB_ADDRESS, ADDRESS); + if (fb_size < value) + value = 0; + else + value += FIELD_GET(regRead32(pSmi, PANEL_FB_WIDTH), + PANEL_FB_WIDTH, OFFSET) * + FIELD_GET(regRead32(pSmi, PANEL_WINDOW_HEIGHT), + PANEL_WINDOW_HEIGHT, HEIGHT); + } + + /* Program CRT registers. */ + regWrite32(pSmi, CRT_FB_ADDRESS, + FIELD_SET(0, CRT_FB_ADDRESS, STATUS, PENDING) | + FIELD_SET(0, CRT_FB_ADDRESS, EXT, LOCAL) | + FIELD_VALUE(0, CRT_FB_ADDRESS, ADDRESS, value)); + + regWrite32(pSmi, CRT_FB_WIDTH, + FIELD_VALUE(0, CRT_FB_WIDTH, WIDTH, + register_table->fb_width) | + FIELD_VALUE(0, CRT_FB_WIDTH, OFFSET, + register_table->fb_width)); + + regWrite32(pSmi, CRT_HORIZONTAL_TOTAL, + register_table->horizontal_total); + regWrite32(pSmi, CRT_HORIZONTAL_SYNC, + register_table->horizontal_sync); + regWrite32(pSmi, CRT_VERTICAL_TOTAL, + register_table->vertical_total); + regWrite32(pSmi, CRT_VERTICAL_SYNC, + register_table->vertical_sync); + + /* Program CRT display control register. */ + value = regRead32(pSmi, CRT_DISPLAY_CTRL) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, SELECT) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE) & + FIELD_CLEAR(CRT_DISPLAY_CTRL, FORMAT); + + regWrite32(pSmi, CRT_DISPLAY_CTRL, value | register_table->control); + + /* Palette RAM. */ + palette_ram = CRT_PALETTE_RAM; + + /* Turn on CRT. */ + setDPMS(pSmi, DPMS_ON); + } + + /* In case of 8-bpp, fill palette. */ + if (FIELD_GET(register_table->control, + PANEL_DISPLAY_CTRL, + FORMAT) == PANEL_DISPLAY_CTRL_FORMAT_8) { + /* Start with RGB = 0,0,0. */ + BYTE red = 0, green = 0, blue = 0; + unsigned int gray = 0; + + for (offset = 0; offset < 256 * 4; offset += 4) { + /* Store current RGB value. */ + /* ERROR!!!!! IGX RGB should be a function, maybe RGB16? + regWrite32(pSmi, (palette_ram + offset), + (gray ? (RGB((gray + 50) / 100, + (gray + 50) / 100, + (gray + 50) / 100)) + : (RGB(red, green, blue)))); + */ + + if (gray) /* Walk through grays (40 in total). */ + gray += 654; + else { /* Walk through colors (6 per base color). */ + if (blue != 255) + blue += 51; + else if (green != 255) { + blue = 0; + green += 51; + } + else if (red != 255) { + green = blue = 0; + red += 51; + } + else + gray = 1; + } + } + } + + /* For 16- and 32-bpp, fill palette with gamma values. */ + else { + /* Start with RGB = 0,0,0. */ + value = 0x000000; + for (offset = 0; offset < 256 * 4; offset += 4) { + regWrite32(pSmi, palette_ram + offset, value); + /* Advance RGB by 1,1,1. */ + value += 0x010101; + } + } +} + +void +SetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, display_t display, + int fbPitch, int bpp) +{ + mode_table_t mode; + pmode_table_t vesaMode; + reg_table_t register_table; + + /* Locate the mode */ + vesaMode = findMode(mode_table, nWidth, nHeight, nHertz); + + if (vesaMode != NULL) { + /* Convert VESA timing into Voyager timing */ + adjustMode(vesaMode, &mode, display); + + /* Fill the register structure */ + setModeRegisters(®ister_table, &mode, display, bpp, fbPitch); + + /* Program the registers */ + programMode(pSmi, ®ister_table); + } +} + +void +panelSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp) +{ + SetMode(pSmi, nWidth, nHeight, fMode, 60 /* was nHertz */, PANEL, + fbPitch, bpp); +} + +void +crtSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp) +{ + SetMode(pSmi, nWidth, nHeight, fMode, nHertz, CRT, + fbPitch, bpp); +} + +/* + * + * + * From POWER.C + * + * + */ +/* Program new power mode. */ +void +setPower(SMIPtr pSmi, unsigned int nGates, unsigned int Clock) +{ + unsigned int gate_reg, clock_reg; + unsigned int control_value; + + /* Get current power mode. */ + control_value = FIELD_GET(regRead32(pSmi, POWER_MODE_CTRL), + POWER_MODE_CTRL, MODE); + + switch (control_value) { + case POWER_MODE_CTRL_MODE_MODE0: + + /* Switch from mode 0 to mode 1. */ + gate_reg = POWER_MODE1_GATE; + clock_reg = POWER_MODE1_CLOCK; + control_value = FIELD_SET(control_value, + POWER_MODE_CTRL, MODE, MODE1); + break; + + case POWER_MODE_CTRL_MODE_MODE1: + case POWER_MODE_CTRL_MODE_SLEEP: + + /* Switch from mode 1 or sleep to mode 0. */ + gate_reg = POWER_MODE0_GATE; + clock_reg = POWER_MODE0_CLOCK; + control_value = FIELD_SET(control_value, + POWER_MODE_CTRL, MODE, MODE0); + break; + + default: + /* Invalid mode */ + return; + } + + /* Program new power mode. */ + regWrite32(pSmi, gate_reg, nGates); + regWrite32(pSmi, clock_reg, Clock); + regWrite32(pSmi, POWER_MODE_CTRL, control_value); + + /* When returning from sleep, wait until finished. */ + /* IGX -- comment out for now, gets us in an infinite loop! + while (FIELD_GET(regRead32(pSmi, POWER_MODE_CTRL), + POWER_MODE_CTRL, + SLEEP_STATUS) == POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE) ; + */ +} + +/* Set DPMS state. */ +void +setDPMS(SMIPtr pSmi, DPMS_t state) +{ + unsigned int value; + + value = regRead32(pSmi, SYSTEM_CTRL); + switch (state) { + case DPMS_ON: + value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VPHP); + break; + + case DPMS_STANDBY: + value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VPHN); + break; + + case DPMS_SUSPEND: + value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VNHP); + break; + + case DPMS_OFF: + value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VNHN); + break; + } + + regWrite32(pSmi, SYSTEM_CTRL, value); +} + +/* Panel Code */ +/********************************************************************** + * + * panelWaitVSync + * + * Purpose + * Wait for the specified number of panel Vsyncs + * + * Parameters + * [in] + * vsync_count - Number of Vsyncs to wait + * + * [out] + * None + * + * Returns + * Nothing + * + **********************************************************************/ +static void +panelWaitVSync(SMIPtr pSmi, int vsync_count) +{ + unsigned int status; + unsigned int timeout; + + while (vsync_count-- > 0) { + /* Wait for end of vsync */ + timeout = 0; + do { + status = FIELD_GET(regRead32(pSmi, CMD_INTPR_STATUS), + CMD_INTPR_STATUS, PANEL_SYNC); + if (++timeout == VSYNCTIMEOUT) + break; + } while (status == CMD_INTPR_STATUS_PANEL_SYNC_ACTIVE); + + /* Wait for start of vsync */ + timeout = 0; + do { + status = FIELD_GET(regRead32(pSmi, CMD_INTPR_STATUS), + CMD_INTPR_STATUS, PANEL_SYNC); + if (++timeout == VSYNCTIMEOUT) + break; + } while (status == CMD_INTPR_STATUS_PANEL_SYNC_INACTIVE); + } +} + +/********************************************************************** + * + * panelPowerSequence + * + * Purpose + * Turn the panel On/Off + * + * Parameters + * [in] + * on_off - Turn panel On/Off. Can be: + * PANEL_ON + * PANEL_OFF + * vsync_delay - Number of Vsyncs to wait after each signal is + * turned on/off + * + * [out] + * None + * + * Returns + * Nothing + * + **********************************************************************/ +static void +panelPowerSequence(SMIPtr pSmi, panel_state_t on_off, int vsync_delay) +{ + unsigned int panelControl = regRead32(pSmi, PANEL_DISPLAY_CTRL); + + if (on_off == PANEL_ON) { + /* Turn on FPVDDEN. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, FPVDDEN, HIGH); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn on FPDATA. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, DATA, ENABLE); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn on FPVBIAS. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, VBIASEN, HIGH); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn on FPEN. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, FPEN, HIGH); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + } + else { + /* Turn off FPEN. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, FPEN, LOW); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn off FPVBIASEN. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, VBIASEN, LOW); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn off FPDATA. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, DATA, DISABLE); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + panelWaitVSync(pSmi, vsync_delay); + + /* Turn off FPVDDEN. */ + panelControl = FIELD_SET(panelControl, + PANEL_DISPLAY_CTRL, FPVDDEN, LOW); + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + } +} + +/********************************************************************** + * + * panelUseCRT + * + * Purpose + * Enable/disable routing of panel output to CRT monitor + * + * Parameters + * [in] + * bEnable - TRUE enables routing of panel output to CRT monitor + * FALSE disables routing of panel output to CRT monitor + * + * [out] + * None + * + * Returns + * Nothing + * + **********************************************************************/ +void +panelUseCRT(SMIPtr pSmi, BOOL bEnable) +{ + unsigned int panel_ctrl = 0; + unsigned int crt_ctrl = 0; + + panel_ctrl = regRead32(pSmi, PANEL_DISPLAY_CTRL); + crt_ctrl = regRead32(pSmi, CRT_DISPLAY_CTRL); + + if (bEnable) { + /* Enable panel graphics plane */ + panel_ctrl = FIELD_SET(panel_ctrl, PANEL_DISPLAY_CTRL, PLANE, ENABLE); + + /* Disable CRT graphics plane */ + crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, PLANE, DISABLE); + + /* Route panel data to CRT monitor */ + crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL); + } + else { + /* Disable panel graphics plane */ + panel_ctrl = FIELD_SET(panel_ctrl, PANEL_DISPLAY_CTRL, PLANE, DISABLE); + + /* Enable CRT graphics plane */ + crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, PLANE, ENABLE); + + /* Do not route panel data to CRT monitor */ + crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, SELECT, CRT); + } + + regWrite32(pSmi, PANEL_DISPLAY_CTRL, panel_ctrl); + regWrite32(pSmi, CRT_DISPLAY_CTRL, crt_ctrl); +} + +void +DisableOverlay(SMIPtr pSmi) +{ + int dwVal = READ_VPR(pSmi, 0x00); + + WRITE_VPR(pSmi, 0x00, dwVal & 0xfffffffb); +} +void +EnableOverlay(SMIPtr pSmi) +{ + int dwVal = READ_VPR(pSmi, 0x00); + + WRITE_VPR(pSmi, 0x00, dwVal | 0x00000004); +} diff --git a/src/smi_501.h b/src/smi_501.h new file mode 100644 index 0000000..5f4809e --- /dev/null +++ b/src/smi_501.h @@ -0,0 +1,1315 @@ +/* Header: //Mercury/Projects/archives/XFree86/4.0/smi.h-arc 1.51 29 Nov 2000 17:45:16 Frido $ */ + +/* +Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. +Copyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- +NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the XFree86 Project and +Silicon Motion shall not be used in advertising or otherwise to promote the +sale, use or other dealings in this Software without prior written +authorization from the XFree86 Project and Silicon Motion. +*/ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/siliconmotion/smi.h,v 1.13 2003/04/23 21:51:44 tsi Exp $ */ + +#ifndef _SMI_501_H +#define _SMI_501_H + + +/****************************************************************************** + * D E F I N I T I O N S + ******************************************************************************/ + +/* Use PLL with 12MHz crystal instead of test clock. */ +#define USE_CRYSTAL_12 0 +/* Use PLL with 24MHz crystal instead of test clock. */ +#define USE_CRYSTAL_24 1 + +/* In Kb - documentation says it is 64Kb... */ +#define FB_RESERVE4USB 512 + +/* Power constants to use with setDPMS function. */ +typedef enum _DPMS_t { + DPMS_ON, + DPMS_STANDBY, + DPMS_SUSPEND, + DPMS_OFF +} DPMS_t; + +/* Display type constants to use with setMode function and others. */ +typedef enum _display_t { + PANEL, + CRT +} display_t; + +/* Type of LCD display */ +typedef enum _lcd_display_t { + LCD_TFT = 0, + LCD_STN_8 = 2, + LCD_STN_12 = 3 +} lcd_display_t; + +/* Polarity constants. */ +typedef enum _polarity_t { + POSITIVE, + NEGATIVE +} polarity_t; + +/* RGB color structure. */ +typedef struct { + unsigned char cBlue; + unsigned char cGreen; + unsigned char cRed; + unsigned char cFiller; +} RGB; + +/* Format of mode table record */ +typedef struct _mode_table_t { + /* Horizontal timing */ + int horizontal_total; + int horizontal_display_end; + int horizontal_sync_start; + int horizontal_sync_width; + polarity_t horizontal_sync_polarity; + + /* Vertical timing. */ + int vertical_total; + int vertical_display_end; + int vertical_sync_start; + int vertical_sync_height; + polarity_t vertical_sync_polarity; + + /* Refresh timing. */ + int pixel_clock; + int horizontal_frequency; + int vertical_frequency; +} mode_table_t, *pmode_table_t; + +/* Clock value structure. */ +typedef struct clock_select_t { + int mclk; + int divider; + int shift; +} clock_select_t, *pclock_select_t; + +/* Registers necessary to set mode. */ +typedef struct _reg_table_t { + unsigned int clock; + unsigned int control; + unsigned int fb_width; + unsigned int horizontal_total; + unsigned int horizontal_sync; + unsigned int vertical_total; + unsigned int vertical_sync; + unsigned int width; + unsigned int height; + display_t display; +} reg_table_t, *preg_table_t; + +/* Structure used to initialize CRT hardware module */ +typedef struct { + unsigned int mask; /* Holds flags indicating which register + * bitfields to init */ + unsigned int fifo_level; /* FIFO request level */ + unsigned int tvp; /* TV clock phase select */ + unsigned int cp; /* CRT clock phase select */ + unsigned int blank; /* CRT data blanking */ + unsigned int format; /* CRT graphics plane format */ +} init_crt, *pinit_crt; + +/* Structure used to initialize CRT cursor hardware module */ +typedef struct { + unsigned int mask; /* Holds flags indicating which register + * bitfields to init */ +} init_crt_hwc, *pinit_crt_hwc; + + +/* Panel On/Off constants to use with panelPowerSequence. */ +typedef enum _panel_state_t { + PANEL_OFF, + PANEL_ON +} panel_state_t; + +/******************************************************************************/ +/* M A C R O S */ +/******************************************************************************/ +/* Direct register access macro */ +#define REG_READ8(r) (*(volatile unsigned char *) &g_pRegisters[r]) +#define REG_READ16(r) (*(volatile unsighed short *)&g_pRegisters[r]) +#define REG_READ32(r) (*(volatile unsighed int *) &g_pRegisters[r]) +#define REG_WRITE8(r, v) \ + { *(volatile unsigned char *) &g_pRegisters[r] = (v); } +#define REG_WRITE16(r, v) \ + { *(volatile unsighed short *)&g_pRegisters[r] = (v); } +#define REG_WRITE32(r, v) \ + { *(volatile unsigned long *) &g_pRegisters[r] = (v); } + +/* Internal macros */ +#define _F_START(f) (0 ? f) +#define _F_END(f) (1 ? f) +#define _F_SIZE(f) (1 + _F_END(f) - _F_START(f)) +#define _F_MASK(f) (((1 << _F_SIZE(f)) - 1) << _F_START(f)) +#define _F_NORMALIZE(v, f) (((v) & _F_MASK(f)) >> _F_START(f)) +#define _F_DENORMALIZE(v, f) (((v) << _F_START(f)) & _F_MASK(f)) + +/* Global macros */ +#define FIELD_GET(x, reg, field) \ +( \ + _F_NORMALIZE((x), reg ## _ ## field) \ +) + +#define FIELD_SET(x, reg, field, value) \ +( \ + (x & ~_F_MASK(reg ## _ ## field)) | \ + _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ +) + +#define FIELD_VALUE(x, reg, field, value) \ +( \ + (x & ~_F_MASK(reg ## _ ## field)) | \ + _F_DENORMALIZE(value, reg ## _ ## field) \ +) + +#define FIELD_CLEAR(reg, field) \ +( \ + ~ _F_MASK(reg ## _ ## field) \ +) + +/* Field Macros */ +#define FIELD_START(field) (0 ? field) +#define FIELD_END(field) (1 ? field) +#define FIELD_SIZE(field) \ + (1 + FIELD_END(field) - FIELD_START(field)) +#define FIELD_MASK(field) \ + (((1 << (FIELD_SIZE(field)-1)) | \ + ((1 << (FIELD_SIZE(field)-1)) - 1)) << FIELD_START(field)) +#define FIELD_NORMALIZE(reg, field) \ + (((reg) & FIELD_MASK(field)) >> FIELD_START(field)) +#define FIELD_DENORMALIZE(field, value) \ + (((value) << FIELD_START(field)) & FIELD_MASK(field)) + +#define FIELD_INIT(reg, field, value) \ + FIELD_DENORMALIZE(reg ## _ ## field, \ + reg ## _ ## field ## _ ## value) +#define FIELD_INIT_VAL(reg, field, value) \ + FIELD_DENORMALIZE(reg ## _ ## field, value) +#define FIELD_VAL_SET(x, r, f, v) x = x & ~FIELD_MASK(r ## _ ## f) + + +/****************************************************************************** + * F U N C T I O N P R O T O T Y P E S + ******************************************************************************/ +/* Set gate and power mode. */ +void setPower(SMIPtr pSmi, unsigned int nGates, unsigned int nClock); +/* Set DPMS state. */ +void setDPMS(SMIPtr pSmi, DPMS_t state); +/* Calculate memory clock settings of input clock. */ + +/* Init flags and values used in init_crt structure */ + +/* TV clock phase select */ +#define DISP_CRT_TVP 0x00000100 +#define DISP_CRT_TVP_HIGH 0x00000000 +#define DISP_CRT_TVP_LOW 0x00008000 + +/* CRT clock phase select */ +#define DISP_CRT_CP 0x00000200 +#define DISP_CRT_CP_HIGH 0x00000000 +#define DISP_CRT_CP_LOW 0x00004000 + +/* CRT data blanking */ +#define DISP_CRT_BLANK 0x00000400 +#define DISP_CRT_BLANK_OFF 0x00000000 +#define DISP_CRT_BLANK_ON 0x00000400 + +/* CRT graphics plane format */ +#define DISP_CRT_FORMAT 0x00000800 +#define DISP_CRT_FORMAT_8 0x00000000 +#define DISP_CRT_FORMAT_16 0x00000001 +#define DISP_CRT_FORMAT_32 0x00000002 + +#define DISP_MODE_8_BPP 0 /* 8 bpp i8RGB */ +#define DISP_MODE_16_BPP 1 /* 16 bpp RGB565 */ +#define DISP_MODE_32_BPP 2 /* 32 bpp RGB888 */ +#define DISP_MODE_YUV 3 /* 16 bpp YUV422 */ +#define DISP_MODE_ALPHA_8 4 /* 8 bpp a4i4RGB */ +#define DISP_MODE_ALPHA_16 5 /* 16 bpp a4RGB444 */ + +#define DISP_PAN_LEFT 0 /* Pan left */ +#define DISP_PAN_RIGHT 1 /* Pan right */ +#define DISP_PAN_UP 2 /* Pan upwards */ +#define DISP_PAN_DOWN 3 /* Pan downwards */ + +#define DISP_DPMS_QUERY -1 /* Query DPMS value */ +#define DISP_DPMS_ON 0 /* DPMS on */ +#define DISP_DPMS_STANDBY 1 /* DPMS standby */ +#define DISP_DPMS_SUSPEND 2 /* DPMS suspend */ +#define DISP_DPMS_OFF 3 /* DPMS off */ + +#define DISP_DELAY_DEFAULT 0 /* Default delay */ + +/* Used in panelSetTiming, crtSetTiming if nHTotal, nVTotal not specified */ +#define DISP_HVTOTAL_UNKNOWN -1 +/* Used in panelSetTiming, crtSetTiming if nHTotal, nVTotal not specified */ +#define DISP_HVTOTAL_SCALEFACTOR 1.25 + +#define VGX_SIGNAL_PANEL_VSYNC 100 /* Panel VSYNC */ +#define VGX_SIGNAL_PANEL_PAN 101 /* auto panning complete*/ +#define VGX_SIGNAL_CRT_VSYNC 102 /* CRT VSYNC */ + +#define VSYNCTIMEOUT 10000 + +/* Use per-pixel alpha values */ +#define ALPHA_MODE_PER_PIXEL 0 +/* Use alpha value specified in Alpha bitfield */ +#define ALPHA_MODE_ALPHA 1 +/* Number of colors in alpha/video alpha palette */ +#define ALPHA_COLOR_LUT_SIZE 16 + +/* Cursor is within screen top/left boundary */ +#define HWC_ON_SCREEN 0 +/* Cursor is outside screen top/left boundary */ +#define HWC_OFF_SCREEN 1 +/* Number of cursor colors */ +#define HWC_NUM_COLORS 3 + +#define RGB565_R_MASK 0xF8 /* Mask for red color */ +#define RGB565_G_MASK 0xFC /* Mask for green color */ +#define RGB565_B_MASK 0xF8 /* Mask for blue color */ + +/* Number of bits to shift for red color */ +#define RGB565_R_SHIFT 8 +/* Number of bits to shift for green color */ +#define RGB565_G_SHIFT 3 +/* Number of bits to shift for blue color */ +#define RGB565_B_SHIFT 3 + +#define RGB16(r, g, b) \ +( \ + (unsigned short)((((r) & RGB565_R_MASK) << RGB565_R_SHIFT) | \ + (((g) & RGB565_G_MASK) << RGB565_G_SHIFT) | \ + (((b) & RGB565_B_MASK) >> RGB565_B_SHIFT)) \ +) + +/* Sets the same mode both on panel and crt */ +void SetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, display_t display, + int fbPitch, int bpp); +/* Initialize the panel hardware module */ + +/* Initialize the CRT hardware module */ +void crtInit(pinit_crt init); +/* Enable CRT gamma control (RGB 5:6:5 and RGB 8:8:8 modes only) */ +void crtSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp); +/* Get and/or set CRT DPMS.*/ +unsigned int crtDPMS(int nDPMS); +/* Set CRT frame buffer pointer. */ +void crtSetTiming(unsigned int nHDisplay, unsigned int nHTotal, + unsigned int nHSyncStart, unsigned int nHSyncEnd, + unsigned int nVDisplay, unsigned int nVTotal, + unsigned int nVSyncStart, unsigned int nVSyncEnd, + unsigned int nPixelClock, unsigned int nHPolarity, + unsigned int nVPolarity); +/* Get CRT LUT palette. */ +void crtHwcInit(pinit_crt_hwc init); +/* Enable CRT hardware cursor */ +void crtHwcEnable(void); +/* Disable CRT hardware cursor */ +void crtHwcDisable(void); +/* Set CRT pointer shape and/or colors. */ +void crtPointerShape(unsigned char *pShape, int nWidth, int nHeight, + int nHotX, int nHotY, RGB rgbColor[3]); +/* Set CRT cursor on-screen position. */ +void crtPointerPosition(int nX, int nY, int nTopSelect, int nLeftSelect); +/* Set CRT cursor on-screen position. */ +void crtHwcSetPosition(int nX, int nY, int nTopSelect, int nLeftSelect); +/* Set CRT cursor colors */ +void crtHwcSetColors(RGB rgbColor[HWC_NUM_COLORS]); + +/* Route Panel data to CRT for Simultaneous mode */ +void panelUseCRT(SMIPtr pSmi, BOOL bEnable); + +void panelSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, + unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp); + +/* REGISTER DEFINITIONS */ + +/* regSC.h */ +#define SYSTEM_CTRL 0x000000 +#define SYSTEM_CTRL_DPMS 31:30 +#define SYSTEM_CTRL_DPMS_VPHP 0 +#define SYSTEM_CTRL_DPMS_VPHN 1 +#define SYSTEM_CTRL_DPMS_VNHP 2 +#define SYSTEM_CTRL_DPMS_VNHN 3 +#define SYSTEM_CTRL_PCI_BURST 29:29 +#define SYSTEM_CTRL_PCI_BURST_DISABLE 0 +#define SYSTEM_CTRL_PCI_BURST_ENABLE 1 +#define SYSTEM_CTRL_CSC_STATUS 28:28 +#define SYSTEM_CTRL_CSC_STATUS_IDLE 0 +#define SYSTEM_CTRL_CSC_STATUS_BUSY 1 +#define SYSTEM_CTRL_PCI_MASTER 25:25 +#define SYSTEM_CTRL_PCI_MASTER_STOP 0 +#define SYSTEM_CTRL_PCI_MASTER_START 1 +#define SYSTEM_CTRL_LATENCY_TIMER 24:24 +#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE 0 +#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE 1 +#define SYSTEM_CTRL_PANEL_STATUS 23:23 +#define SYSTEM_CTRL_PANEL_STATUS_CURRENT 0 +#define SYSTEM_CTRL_PANEL_STATUS_PENDING 1 +#define SYSTEM_CTRL_VIDEO_STATUS 22:22 +#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT 0 +#define SYSTEM_CTRL_VIDEO_STATUS_PENDING 1 +#define SYSTEM_CTRL_DE_FIFO 20:20 +#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY 0 +#define SYSTEM_CTRL_DE_FIFO_EMPTY 1 +#define SYSTEM_CTRL_DE_STATUS 19:19 +#define SYSTEM_CTRL_DE_STATUS_IDLE 0 +#define SYSTEM_CTRL_DE_STATUS_BUSY 1 +#define SYSTEM_CTRL_CRT_STATUS 17:17 +#define SYSTEM_CTRL_CRT_STATUS_CURRENT 0 +#define SYSTEM_CTRL_CRT_STATUS_PENDING 1 +#define SYSTEM_CTRL_ZVPORT 16:16 +#define SYSTEM_CTRL_ZVPORT_0 0 +#define SYSTEM_CTRL_ZVPORT_1 1 +#define SYSTEM_CTRL_PCI_BURST_READ 15:15 +#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE 0 +#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE 1 +#define SYSTEM_CTRL_DE_ABORT 13:12 +#define SYSTEM_CTRL_DE_ABORT_NORMAL 0 +#define SYSTEM_CTRL_DE_ABORT_2D_ABORT 3 +#define SYSTEM_CTRL_PCI_SUBSYS_LOCK 11:11 +#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE 0 +#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE 1 +#define SYSTEM_CTRL_PCI_RETRY 7:7 +#define SYSTEM_CTRL_PCI_RETRY_ENABLE 0 +#define SYSTEM_CTRL_PCI_RETRY_DISABLE 1 +#define SYSTEM_CTRL_PCI_CLOCK_RUN 6:6 +#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE 0 +#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE 1 +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE 5:4 +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 0 +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 1 +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 2 +#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 3 +#define SYSTEM_CTRL_CRT_TRISTATE 2:2 +#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE 0 +#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE 1 +#define SYSTEM_CTRL_INTMEM_TRISTATE 1:1 +#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE 0 +#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE 1 +#define SYSTEM_CTRL_PANEL_TRISTATE 0:0 +#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE 0 +#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE 1 + +#define DRAM_CTRL 0x000010 +#define DRAM_CTRL_EMBEDDED 31:31 +#define DRAM_CTRL_EMBEDDED_ENABLE 0 +#define DRAM_CTRL_EMBEDDED_DISABLE 1 +#define DRAM_CTRL_CPU_BURST 30:28 +#define DRAM_CTRL_CPU_BURST_1 0 +#define DRAM_CTRL_CPU_BURST_2 1 +#define DRAM_CTRL_CPU_BURST_4 2 +#define DRAM_CTRL_CPU_BURST_8 3 +#define DRAM_CTRL_CPU_CAS_LATENCY 27:27 +#define DRAM_CTRL_CPU_CAS_LATENCY_2 0 +#define DRAM_CTRL_CPU_CAS_LATENCY_3 1 +#define DRAM_CTRL_CPU_SIZE 26:24 +#define DRAM_CTRL_CPU_SIZE_2 0 +#define DRAM_CTRL_CPU_SIZE_4 1 +#define DRAM_CTRL_CPU_SIZE_64 4 +#define DRAM_CTRL_CPU_SIZE_32 5 +#define DRAM_CTRL_CPU_SIZE_16 6 +#define DRAM_CTRL_CPU_SIZE_8 7 +#define DRAM_CTRL_CPU_COLUMN_SIZE 23:22 +#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 0 +#define DRAM_CTRL_CPU_COLUMN_SIZE_512 2 +#define DRAM_CTRL_CPU_COLUMN_SIZE_256 3 +#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE 21:21 +#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_6 0 +#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_7 1 +#define DRAM_CTRL_CPU_RESET 20:20 +#define DRAM_CTRL_CPU_RESET_ENABLE 0 +#define DRAM_CTRL_CPU_RESET_DISABLE 1 +#define DRAM_CTRL_CPU_BANKS 19:19 +#define DRAM_CTRL_CPU_BANKS_2 0 +#define DRAM_CTRL_CPU_BANKS_4 1 +#define DRAM_CTRL_CPU_WRITE_PRECHARGE 18:18 +#define DRAM_CTRL_CPU_WRITE_PRECHARGE_2 0 +#define DRAM_CTRL_CPU_WRITE_PRECHARGE_1 1 +#define DRAM_CTRL_BLOCK_WRITE 17:17 +#define DRAM_CTRL_BLOCK_WRITE_DISABLE 0 +#define DRAM_CTRL_BLOCK_WRITE_ENABLE 1 +#define DRAM_CTRL_REFRESH_COMMAND 16:16 +#define DRAM_CTRL_REFRESH_COMMAND_10 0 +#define DRAM_CTRL_REFRESH_COMMAND_12 1 +#define DRAM_CTRL_SIZE 15:13 +#define DRAM_CTRL_SIZE_4 0 +#define DRAM_CTRL_SIZE_8 1 +#define DRAM_CTRL_SIZE_16 2 +#define DRAM_CTRL_SIZE_32 3 +#define DRAM_CTRL_SIZE_64 4 +#define DRAM_CTRL_SIZE_2 5 +#define DRAM_CTRL_COLUMN_SIZE 12:11 +#define DRAM_CTRL_COLUMN_SIZE_256 0 +#define DRAM_CTRL_COLUMN_SIZE_512 2 +#define DRAM_CTRL_COLUMN_SIZE_1024 3 +#define DRAM_CTRL_BLOCK_WRITE_TIME 10:10 +#define DRAM_CTRL_BLOCK_WRITE_TIME_1 0 +#define DRAM_CTRL_BLOCK_WRITE_TIME_2 1 +#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE 9:9 +#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_4 0 +#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_1 1 +#define DRAM_CTRL_ACTIVE_PRECHARGE 8:8 +#define DRAM_CTRL_ACTIVE_PRECHARGE_6 0 +#define DRAM_CTRL_ACTIVE_PRECHARGE_7 1 +#define DRAM_CTRL_RESET 7:7 +#define DRAM_CTRL_RESET_ENABLE 0 +#define DRAM_CTRL_RESET_DISABLE 1 +#define DRAM_CTRL_REMAIN_ACTIVE 6:6 +#define DRAM_CTRL_REMAIN_ACTIVE_ENABLE 0 +#define DRAM_CTRL_REMAIN_ACTIVE_DISABLE 1 +#define DRAM_CTRL_BANKS 1:1 +#define DRAM_CTRL_BANKS_2 1 +#define DRAM_CTRL_BANKS_4 0 +#define DRAM_CTRL_WRITE_PRECHARGE 0:0 +#define DRAM_CTRL_WRITE_PRECHARGE_2 0 +#define DRAM_CTRL_WRITE_PRECHARGE_1 1 + +#define CURRENT_POWER_CLOCK 0x00003C +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT 29:29 +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER 28:27 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5 2 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT 26:24 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT 20:20 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER 19:19 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT 18:16 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_MCLK_SELECT 12:12 +#define CURRENT_POWER_CLOCK_MCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_MCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER 11:11 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT 10:8 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT 4:4 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER 3:3 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT 2:0 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7 7 + +#define CURRENT_POWER_GATE 0x000038 +#define CURRENT_POWER_GATE_AC97_I2S 18:18 +#define CURRENT_POWER_GATE_AC97_I2S_DISABLE 0 +#define CURRENT_POWER_GATE_AC97_I2S_ENABLE 1 +#define CURRENT_POWER_GATE_8051 17:17 +#define CURRENT_POWER_GATE_8051_DISABLE 0 +#define CURRENT_POWER_GATE_8051_ENABLE 1 +#define CURRENT_POWER_GATE_PLL 16:16 +#define CURRENT_POWER_GATE_PLL_DISABLE 0 +#define CURRENT_POWER_GATE_PLL_ENABLE 1 +#define CURRENT_POWER_GATE_OSCILLATOR 15:15 +#define CURRENT_POWER_GATE_OSCILLATOR_DISABLE 0 +#define CURRENT_POWER_GATE_OSCILLATOR_ENABLE 1 +#define CURRENT_POWER_GATE_PLL_RECOVERY 14:13 +#define CURRENT_POWER_GATE_PLL_RECOVERY_32 0 +#define CURRENT_POWER_GATE_PLL_RECOVERY_64 1 +#define CURRENT_POWER_GATE_PLL_RECOVERY_96 2 +#define CURRENT_POWER_GATE_PLL_RECOVERY_128 3 +#define CURRENT_POWER_GATE_USB_SLAVE 12:12 +#define CURRENT_POWER_GATE_USB_SLAVE_DISABLE 0 +#define CURRENT_POWER_GATE_USB_SLAVE_ENABLE 1 +#define CURRENT_POWER_GATE_USB_HOST 11:11 +#define CURRENT_POWER_GATE_USB_HOST_DISABLE 0 +#define CURRENT_POWER_GATE_USB_HOST_ENABLE 1 +#define CURRENT_POWER_GATE_SSP0_SSP1 10:10 +#define CURRENT_POWER_GATE_SSP0_SSP1_DISABLE 0 +#define CURRENT_POWER_GATE_SSP0_SSP1_ENABLE 1 +#define CURRENT_POWER_GATE_UART1 8:8 +#define CURRENT_POWER_GATE_UART1_DISABLE 0 +#define CURRENT_POWER_GATE_UART1_ENABLE 1 +#define CURRENT_POWER_GATE_UART0 7:7 +#define CURRENT_POWER_GATE_UART0_DISABLE 0 +#define CURRENT_POWER_GATE_UART0_ENABLE 1 +#define CURRENT_POWER_GATE_GPIO_PWM_I2C 6:6 +#define CURRENT_POWER_GATE_GPIO_PWM_I2C_DISABLE 0 +#define CURRENT_POWER_GATE_GPIO_PWM_I2C_ENABLE 1 +#define CURRENT_POWER_GATE_ZVPORT 5:5 +#define CURRENT_POWER_GATE_ZVPORT_DISABLE 0 +#define CURRENT_POWER_GATE_ZVPORT_ENABLE 1 +#define CURRENT_POWER_GATE_CSC 4:4 +#define CURRENT_POWER_GATE_CSC_DISABLE 0 +#define CURRENT_POWER_GATE_CSC_ENABLE 1 +#define CURRENT_POWER_GATE_2D 3:3 +#define CURRENT_POWER_GATE_2D_DISABLE 0 +#define CURRENT_POWER_GATE_2D_ENABLE 1 +#define CURRENT_POWER_GATE_DISPLAY 2:2 +#define CURRENT_POWER_GATE_DISPLAY_DISABLE 0 +#define CURRENT_POWER_GATE_DISPLAY_ENABLE 1 +#define CURRENT_POWER_GATE_INTMEM 1:1 +#define CURRENT_POWER_GATE_INTMEM_DISABLE 0 +#define CURRENT_POWER_GATE_INTMEM_ENABLE 1 +#define CURRENT_POWER_GATE_HOST 0:0 +#define CURRENT_POWER_GATE_HOST_DISABLE 0 +#define CURRENT_POWER_GATE_HOST_ENABLE 1 + +#define CURRENT_POWER_CLOCK 0x00003C +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT 29:29 +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER 28:27 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5 2 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT 26:24 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT 20:20 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER 19:19 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT 18:16 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_MCLK_SELECT 12:12 +#define CURRENT_POWER_CLOCK_MCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_MCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER 11:11 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT 10:8 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7 7 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT 4:4 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288 0 +#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336 1 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER 3:3 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1 0 +#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3 1 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT 2:0 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0 0 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1 1 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2 2 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3 3 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4 4 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5 5 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6 6 +#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7 7 + +#define POWER_MODE0_GATE 0x000040 +#define POWER_MODE0_GATE_AC97_I2S 18:18 +#define POWER_MODE0_GATE_AC97_I2S_DISABLE 0 +#define POWER_MODE0_GATE_AC97_I2S_ENABLE 1 +#define POWER_MODE0_GATE_8051 17:17 +#define POWER_MODE0_GATE_8051_DISABLE 0 +#define POWER_MODE0_GATE_8051_ENABLE 1 +#define POWER_MODE0_GATE_USB_SLAVE 12:12 +#define POWER_MODE0_GATE_USB_SLAVE_DISABLE 0 +#define POWER_MODE0_GATE_USB_SLAVE_ENABLE 1 +#define POWER_MODE0_GATE_USB_HOST 11:11 +#define POWER_MODE0_GATE_USB_HOST_DISABLE 0 +#define POWER_MODE0_GATE_USB_HOST_ENABLE 1 +#define POWER_MODE0_GATE_SSP0_SSP1 10:10 +#define POWER_MODE0_GATE_SSP0_SSP1_DISABLE 0 +#define POWER_MODE0_GATE_SSP0_SSP1_ENABLE 1 +#define POWER_MODE0_GATE_UART1 8:8 +#define POWER_MODE0_GATE_UART1_DISABLE 0 +#define POWER_MODE0_GATE_UART1_ENABLE 1 +#define POWER_MODE0_GATE_UART0 7:7 +#define POWER_MODE0_GATE_UART0_DISABLE 0 +#define POWER_MODE0_GATE_UART0_ENABLE 1 +#define POWER_MODE0_GATE_GPIO_PWM_I2C 6:6 +#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE 0 +#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE 1 +#define POWER_MODE0_GATE_ZVPORT 5:5 +#define POWER_MODE0_GATE_ZVPORT_DISABLE 0 +#define POWER_MODE0_GATE_ZVPORT_ENABLE 1 +#define POWER_MODE0_GATE_CSC 4:4 +#define POWER_MODE0_GATE_CSC_DISABLE 0 +#define POWER_MODE0_GATE_CSC_ENABLE 1 +#define POWER_MODE0_GATE_2D 3:3 +#define POWER_MODE0_GATE_2D_DISABLE 0 +#define POWER_MODE0_GATE_2D_ENABLE 1 +#define POWER_MODE0_GATE_DISPLAY 2:2 +#define POWER_MODE0_GATE_DISPLAY_DISABLE 0 +#define POWER_MODE0_GATE_DISPLAY_ENABLE 1 +#define POWER_MODE0_GATE_INTMEM 1:1 +#define POWER_MODE0_GATE_INTMEM_DISABLE 0 +#define POWER_MODE0_GATE_INTMEM_ENABLE 1 +#define POWER_MODE0_GATE_HOST 0:0 +#define POWER_MODE0_GATE_HOST_DISABLE 0 +#define POWER_MODE0_GATE_HOST_ENABLE 1 + +#define POWER_MODE0_CLOCK 0x000044 +#define POWER_MODE0_CLOCK_P2XCLK_SELECT 29:29 +#define POWER_MODE0_CLOCK_P2XCLK_SELECT_288 0 +#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336 1 +#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER 28:27 +#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1 0 +#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3 1 +#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5 2 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT 26:24 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_0 0 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_1 1 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_2 2 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_3 3 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_4 4 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_5 5 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_6 6 +#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_7 7 +#define POWER_MODE0_CLOCK_V2XCLK_SELECT 20:20 +#define POWER_MODE0_CLOCK_V2XCLK_SELECT_288 0 +#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336 1 +#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER 19:19 +#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1 0 +#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3 1 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT 18:16 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_0 0 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_1 1 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_2 2 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_3 3 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_4 4 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_5 5 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_6 6 +#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_7 7 +#define POWER_MODE0_CLOCK_MCLK_SELECT 12:12 +#define POWER_MODE0_CLOCK_MCLK_SELECT_288 0 +#define POWER_MODE0_CLOCK_MCLK_SELECT_336 1 +#define POWER_MODE0_CLOCK_MCLK_DIVIDER 11:11 +#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1 0 +#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3 1 +#define POWER_MODE0_CLOCK_MCLK_SHIFT 10:8 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_0 0 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_1 1 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_2 2 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_3 3 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_4 4 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_5 5 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_6 6 +#define POWER_MODE0_CLOCK_MCLK_SHIFT_7 7 +#define POWER_MODE0_CLOCK_M2XCLK_SELECT 4:4 +#define POWER_MODE0_CLOCK_M2XCLK_SELECT_288 0 +#define POWER_MODE0_CLOCK_M2XCLK_SELECT_336 1 +#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER 3:3 +#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_1 0 +#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_3 1 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT 2:0 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_0 0 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_1 1 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_2 2 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_3 3 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_4 4 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_5 5 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_6 6 +#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_7 7 + +#define POWER_MODE1_GATE 0x000048 +#define POWER_MODE1_GATE_AC97_I2S 18:18 +#define POWER_MODE1_GATE_AC97_I2S_DISABLE 0 +#define POWER_MODE1_GATE_AC97_I2S_ENABLE 1 +#define POWER_MODE1_GATE_8051 17:17 +#define POWER_MODE1_GATE_8051_DISABLE 0 +#define POWER_MODE1_GATE_8051_ENABLE 1 +#define POWER_MODE1_GATE_USB_SLAVE 12:12 +#define POWER_MODE1_GATE_USB_SLAVE_DISABLE 0 +#define POWER_MODE1_GATE_USB_SLAVE_ENABLE 1 +#define POWER_MODE1_GATE_USB_HOST 11:11 +#define POWER_MODE1_GATE_USB_HOST_DISABLE 0 +#define POWER_MODE1_GATE_USB_HOST_ENABLE 1 +#define POWER_MODE1_GATE_SSP0_SSP1 10:10 +#define POWER_MODE1_GATE_SSP0_SSP1_DISABLE 0 +#define POWER_MODE1_GATE_SSP0_SSP1_ENABLE 1 +#define POWER_MODE1_GATE_UART1 8:8 +#define POWER_MODE1_GATE_UART1_DISABLE 0 +#define POWER_MODE1_GATE_UART1_ENABLE 1 +#define POWER_MODE1_GATE_UART0 7:7 +#define POWER_MODE1_GATE_UART0_DISABLE 0 +#define POWER_MODE1_GATE_UART0_ENABLE 1 +#define POWER_MODE1_GATE_GPIO_PWM_I2C 6:6 +#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE 0 +#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE 1 +#define POWER_MODE1_GATE_ZVPORT 5:5 +#define POWER_MODE1_GATE_ZVPORT_DISABLE 0 +#define POWER_MODE1_GATE_ZVPORT_ENABLE 1 +#define POWER_MODE1_GATE_CSC 4:4 +#define POWER_MODE1_GATE_CSC_DISABLE 0 +#define POWER_MODE1_GATE_CSC_ENABLE 1 +#define POWER_MODE1_GATE_2D 3:3 +#define POWER_MODE1_GATE_2D_DISABLE 0 +#define POWER_MODE1_GATE_2D_ENABLE 1 +#define POWER_MODE1_GATE_DISPLAY 2:2 +#define POWER_MODE1_GATE_DISPLAY_DISABLE 0 +#define POWER_MODE1_GATE_DISPLAY_ENABLE 1 +#define POWER_MODE1_GATE_INTMEM 1:1 +#define POWER_MODE1_GATE_INTMEM_DISABLE 0 +#define POWER_MODE1_GATE_INTMEM_ENABLE 1 +#define POWER_MODE1_GATE_HOST 0:0 +#define POWER_MODE1_GATE_HOST_DISABLE 0 +#define POWER_MODE1_GATE_HOST_ENABLE 1 + +#define POWER_MODE1_CLOCK 0x00004C +#define POWER_MODE1_CLOCK_P2XCLK_SELECT 29:29 +#define POWER_MODE1_CLOCK_P2XCLK_SELECT_288 0 +#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336 1 +#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER 28:27 +#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1 0 +#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3 1 +#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5 2 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT 26:24 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_0 0 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_1 1 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_2 2 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_3 3 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_4 4 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_5 5 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_6 6 +#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_7 7 +#define POWER_MODE1_CLOCK_V2XCLK_SELECT 20:20 +#define POWER_MODE1_CLOCK_V2XCLK_SELECT_288 0 +#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336 1 +#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER 19:19 +#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1 0 +#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3 1 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT 18:16 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_0 0 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_1 1 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_2 2 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_3 3 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_4 4 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_5 5 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_6 6 +#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_7 7 +#define POWER_MODE1_CLOCK_MCLK_SELECT 12:12 +#define POWER_MODE1_CLOCK_MCLK_SELECT_288 0 +#define POWER_MODE1_CLOCK_MCLK_SELECT_336 1 +#define POWER_MODE1_CLOCK_MCLK_DIVIDER 11:11 +#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1 0 +#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3 1 +#define POWER_MODE1_CLOCK_MCLK_SHIFT 10:8 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_0 0 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_1 1 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_2 2 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_3 3 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_4 4 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_5 5 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_6 6 +#define POWER_MODE1_CLOCK_MCLK_SHIFT_7 7 +#define POWER_MODE1_CLOCK_M2XCLK_SELECT 4:4 +#define POWER_MODE1_CLOCK_M2XCLK_SELECT_288 0 +#define POWER_MODE1_CLOCK_M2XCLK_SELECT_336 1 +#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER 3:3 +#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_1 0 +#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_3 1 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT 2:0 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_0 0 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_1 1 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_2 2 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_3 3 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_4 4 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_5 5 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_6 6 +#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_7 7 + +#define POWER_SLEEP_GATE 0x000050 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK 22:19 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4096 0 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2048 1 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_1024 2 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_512 3 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_256 4 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_128 5 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_64 6 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_32 7 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_16 8 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_8 9 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4 10 +#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2 11 +#define POWER_SLEEP_GATE_PLL_RECOVERY 14:13 +#define POWER_SLEEP_GATE_PLL_RECOVERY_32 0 +#define POWER_SLEEP_GATE_PLL_RECOVERY_64 1 +#define POWER_SLEEP_GATE_PLL_RECOVERY_96 2 +#define POWER_SLEEP_GATE_PLL_RECOVERY_128 3 + +#define POWER_MODE_CTRL 0x000054 +#define POWER_MODE_CTRL_SLEEP_STATUS 2:2 +#define POWER_MODE_CTRL_SLEEP_STATUS_INACTIVE 0 +#define POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE 1 +#define POWER_MODE_CTRL_MODE 1:0 +#define POWER_MODE_CTRL_MODE_MODE0 0 +#define POWER_MODE_CTRL_MODE_MODE1 1 +#define POWER_MODE_CTRL_MODE_SLEEP 2 + +#define MISC_CTRL 0x000004 +#define MISC_CTRL_PCI_PAD 31:30 +#define MISC_CTRL_PCI_PAD_24MA 0 +#define MISC_CTRL_PCI_PAD_12MA 1 +#define MISC_CTRL_PCI_PAD_8MA 2 +#define MISC_CTRL_48_SELECT 29:28 +#define MISC_CTRL_48_SELECT_CRYSTAL 0 +#define MISC_CTRL_48_SELECT_CPU_96 2 +#define MISC_CTRL_48_SELECT_CPU_48 3 +#define MISC_CTRL_UART1_SELECT 27:27 +#define MISC_CTRL_UART1_SELECT_UART 0 +#define MISC_CTRL_UART1_SELECT_SSP 1 +#define MISC_CTRL_8051_LATCH 26:26 +#define MISC_CTRL_8051_LATCH_DISABLE 0 +#define MISC_CTRL_8051_LATCH_ENABLE 1 +#define MISC_CTRL_FPDATA 25:25 +#define MISC_CTRL_FPDATA_18 0 +#define MISC_CTRL_FPDATA_24 1 +#define MISC_CTRL_CRYSTAL 24:24 +#define MISC_CTRL_CRYSTAL_24 0 +#define MISC_CTRL_CRYSTAL_12 1 +#define MISC_CTRL_DRAM_REFRESH 22:21 +#define MISC_CTRL_DRAM_REFRESH_8 0 +#define MISC_CTRL_DRAM_REFRESH_16 1 +#define MISC_CTRL_DRAM_REFRESH_32 2 +#define MISC_CTRL_DRAM_REFRESH_64 3 +#define MISC_CTRL_BUS_HOLD 20:18 +#define MISC_CTRL_BUS_HOLD_FIFO_EMPTY 0 +#define MISC_CTRL_BUS_HOLD_8 1 +#define MISC_CTRL_BUS_HOLD_16 2 +#define MISC_CTRL_BUS_HOLD_24 3 +#define MISC_CTRL_BUS_HOLD_32 4 +#define MISC_CTRL_HITACHI_READY 17:17 +#define MISC_CTRL_HITACHI_READY_NEGATIVE 0 +#define MISC_CTRL_HITACHI_READY_POSITIVE 1 +#define MISC_CTRL_INTERRUPT 16:16 +#define MISC_CTRL_INTERRUPT_NORMAL 0 +#define MISC_CTRL_INTERRUPT_INVERT 1 +#define MISC_CTRL_PLL_CLOCK_COUNT 15:15 +#define MISC_CTRL_PLL_CLOCK_COUNT_DISABLE 0 +#define MISC_CTRL_PLL_CLOCK_COUNT_ENABLE 1 +#define MISC_CTRL_DAC_BAND_GAP 14:13 +#define MISC_CTRL_DAC_POWER 12:12 +#define MISC_CTRL_DAC_POWER_ENABLE 0 +#define MISC_CTRL_DAC_POWER_DISABLE 1 +#define MISC_CTRL_USB_SLAVE_CONTROLLER 11:11 +#define MISC_CTRL_USB_SLAVE_CONTROLLER_CPU 0 +#define MISC_CTRL_USB_SLAVE_CONTROLLER_8051 1 +#define MISC_CTRL_BURST_LENGTH 10:10 +#define MISC_CTRL_BURST_LENGTH_8 0 +#define MISC_CTRL_BURST_LENGTH_1 1 +#define MISC_CTRL_USB_SELECT 9:9 +#define MISC_CTRL_USB_SELECT_MASTER 0 +#define MISC_CTRL_USB_SELECT_SLAVE 1 +#define MISC_CTRL_LOOPBACK 8:8 +#define MISC_CTRL_LOOPBACK_NORMAL 0 +#define MISC_CTRL_LOOPBACK_USB_HOST 1 +#define MISC_CTRL_CLOCK_DIVIDER_RESET 7:7 +#define MISC_CTRL_CLOCK_DIVIDER_RESET_ENABLE 0 +#define MISC_CTRL_CLOCK_DIVIDER_RESET_DISABLE 1 +#define MISC_CTRL_TEST_MODE 6:5 +#define MISC_CTRL_TEST_MODE_NORMAL 0 +#define MISC_CTRL_TEST_MODE_DEBUGGING 1 +#define MISC_CTRL_TEST_MODE_NAND 2 +#define MISC_CTRL_TEST_MODE_MEMORY 3 +#define MISC_CTRL_NEC_MMIO 4:4 +#define MISC_CTRL_NEC_MMIO_30 0 +#define MISC_CTRL_NEC_MMIO_62 1 +#define MISC_CTRL_CLOCK 3:3 +#define MISC_CTRL_CLOCK_PLL 0 +#define MISC_CTRL_CLOCK_TEST 1 +#define MISC_CTRL_HOST_BUS 2:0 +#define MISC_CTRL_HOST_BUS_HITACHI 0 +#define MISC_CTRL_HOST_BUS_PCI 1 +#define MISC_CTRL_HOST_BUS_XSCALE 2 +#define MISC_CTRL_HOST_BUS_STRONGARM 4 +#define MISC_CTRL_HOST_BUS_NEC 6 + +#define CMD_INTPR_STATUS 0x000024 +#define CMD_INTPR_STATUS_2D_MEMORY_FIFO 20:20 +#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_NOT_EMPTY 0 +#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_EMPTY 1 +#define CMD_INTPR_STATUS_COMMAND_FIFO 19:19 +#define CMD_INTPR_STATUS_COMMAND_FIFO_NOT_EMPTY 0 +#define CMD_INTPR_STATUS_COMMAND_FIFO_EMPTY 1 +#define CMD_INTPR_STATUS_CSC_STATUS 18:18 +#define CMD_INTPR_STATUS_CSC_STATUS_IDLE 0 +#define CMD_INTPR_STATUS_CSC_STATUS_BUSY 1 +#define CMD_INTPR_STATUS_MEMORY_DMA 17:17 +#define CMD_INTPR_STATUS_MEMORY_DMA_IDLE 0 +#define CMD_INTPR_STATUS_MEMORY_DMA_BUSY 1 +#define CMD_INTPR_STATUS_CRT_STATUS 16:16 +#define CMD_INTPR_STATUS_CRT_STATUS_CURRENT 0 +#define CMD_INTPR_STATUS_CRT_STATUS_PENDING 1 +#define CMD_INTPR_STATUS_CURRENT_FIELD 15:15 +#define CMD_INTPR_STATUS_CURRENT_FIELD_ODD 0 +#define CMD_INTPR_STATUS_CURRENT_FIELD_EVEN 1 +#define CMD_INTPR_STATUS_VIDEO_STATUS 14:14 +#define CMD_INTPR_STATUS_VIDEO_STATUS_CURRENT 0 +#define CMD_INTPR_STATUS_VIDEO_STATUS_PENDING 1 +#define CMD_INTPR_STATUS_PANEL_STATUS 13:13 +#define CMD_INTPR_STATUS_PANEL_STATUS_CURRENT 0 +#define CMD_INTPR_STATUS_PANEL_STATUS_PENDING 1 +#define CMD_INTPR_STATUS_CRT_SYNC 12:12 +#define CMD_INTPR_STATUS_CRT_SYNC_INACTIVE 0 +#define CMD_INTPR_STATUS_CRT_SYNC_ACTIVE 1 +#define CMD_INTPR_STATUS_PANEL_SYNC 11:11 +#define CMD_INTPR_STATUS_PANEL_SYNC_INACTIVE 0 +#define CMD_INTPR_STATUS_PANEL_SYNC_ACTIVE 1 +#define CMD_INTPR_STATUS_2D_SETUP 2:2 +#define CMD_INTPR_STATUS_2D_SETUP_IDLE 0 +#define CMD_INTPR_STATUS_2D_SETUP_BUSY 1 +#define CMD_INTPR_STATUS_2D_FIFO 1:1 +#define CMD_INTPR_STATUS_2D_FIFO_NOT_EMPTY 0 +#define CMD_INTPR_STATUS_2D_FIFO_EMPTY 1 +#define CMD_INTPR_STATUS_2D_ENGINE 0:0 +#define CMD_INTPR_STATUS_2D_ENGINE_IDLE 0 +#define CMD_INTPR_STATUS_2D_ENGINE_BUSY 1 + +/* regDC.h */ +/* Panel Graphics Control */ +#define PANEL_DISPLAY_CTRL 0x080000 +#define PANEL_DISPLAY_CTRL_FPEN 27:27 +#define PANEL_DISPLAY_CTRL_FPEN_LOW 0 +#define PANEL_DISPLAY_CTRL_FPEN_HIGH 1 +#define PANEL_DISPLAY_CTRL_VBIASEN 26:26 +#define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0 +#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1 +#define PANEL_DISPLAY_CTRL_DATA 25:25 +#define PANEL_DISPLAY_CTRL_DATA_DISABLE 0 +#define PANEL_DISPLAY_CTRL_DATA_ENABLE 1 +#define PANEL_DISPLAY_CTRL_FPVDDEN 24:24 +#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0 +#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1 +#define PANEL_DISPLAY_CTRL_PATTERN 23:23 +#define PANEL_DISPLAY_CTRL_PATTERN_4 0 +#define PANEL_DISPLAY_CTRL_PATTERN_8 1 +#define PANEL_DISPLAY_CTRL_TFT 22:21 +#define PANEL_DISPLAY_CTRL_TFT_24 0 +#define PANEL_DISPLAY_CTRL_TFT_9 1 +#define PANEL_DISPLAY_CTRL_TFT_12 2 +#define PANEL_DISPLAY_CTRL_DITHER 20:20 +#define PANEL_DISPLAY_CTRL_DITHER_DISABLE 0 +#define PANEL_DISPLAY_CTRL_DITHER_ENABLE 1 +#define PANEL_DISPLAY_CTRL_LCD 19:18 +#define PANEL_DISPLAY_CTRL_LCD_TFT 0 +#define PANEL_DISPLAY_CTRL_LCD_STN_8 2 +#define PANEL_DISPLAY_CTRL_LCD_STN_12 3 +#define PANEL_DISPLAY_CTRL_FIFO 17:16 +#define PANEL_DISPLAY_CTRL_FIFO_1 0 +#define PANEL_DISPLAY_CTRL_FIFO_3 1 +#define PANEL_DISPLAY_CTRL_FIFO_7 2 +#define PANEL_DISPLAY_CTRL_FIFO_11 3 +#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 +#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 +#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 +#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 +#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 +#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 +#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 +#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 +#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 +#define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 +#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 +#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 +#define PANEL_DISPLAY_CTRL_TIMING 8:8 +#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 +#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0 +#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 +#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 +#define PANEL_DISPLAY_CTRL_GAMMA 3:3 +#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 +#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 +#define PANEL_DISPLAY_CTRL_PLANE 2:2 +#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 +#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 +#define PANEL_DISPLAY_CTRL_FORMAT 1:0 +#define PANEL_DISPLAY_CTRL_FORMAT_8 0 +#define PANEL_DISPLAY_CTRL_FORMAT_16 1 +#define PANEL_DISPLAY_CTRL_FORMAT_32 2 + +#define PANEL_PAN_CTRL 0x080004 +#define PANEL_PAN_CTRL_VERTICAL_PAN 31:24 +#define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16 +#define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8 +#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0 + +#define PANEL_COLOR_KEY 0x080008 +#define PANEL_COLOR_KEY_MASK 31:16 +#define PANEL_COLOR_KEY_VALUE 15:0 + +#define PANEL_FB_ADDRESS 0x08000C +#define PANEL_FB_ADDRESS_STATUS 31:31 +#define PANEL_FB_ADDRESS_STATUS_CURRENT 0 +#define PANEL_FB_ADDRESS_STATUS_PENDING 1 +#define PANEL_FB_ADDRESS_EXT 27:27 +#define PANEL_FB_ADDRESS_EXT_LOCAL 0 +#define PANEL_FB_ADDRESS_EXT_EXTERNAL 1 +#define PANEL_FB_ADDRESS_CS 26:26 +#define PANEL_FB_ADDRESS_CS_0 0 +#define PANEL_FB_ADDRESS_CS_1 1 +#define PANEL_FB_ADDRESS_ADDRESS 25:0 + +#define PANEL_FB_WIDTH 0x080010 +#define PANEL_FB_WIDTH_WIDTH 29:16 +#define PANEL_FB_WIDTH_OFFSET 13:0 + +#define PANEL_WINDOW_WIDTH 0x080014 +#define PANEL_WINDOW_WIDTH_WIDTH 27:16 +#define PANEL_WINDOW_WIDTH_X 11:0 + +#define PANEL_WINDOW_HEIGHT 0x080018 +#define PANEL_WINDOW_HEIGHT_HEIGHT 27:16 +#define PANEL_WINDOW_HEIGHT_Y 11:0 + +#define PANEL_PLANE_TL 0x08001C +#define PANEL_PLANE_TL_TOP 26:16 +#define PANEL_PLANE_TL_LEFT 10:0 + +#define PANEL_PLANE_BR 0x080020 +#define PANEL_PLANE_BR_BOTTOM 26:16 +#define PANEL_PLANE_BR_RIGHT 10:0 + +#define PANEL_HORIZONTAL_TOTAL 0x080024 +#define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16 +#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0 + +#define PANEL_HORIZONTAL_SYNC 0x080028 +#define PANEL_HORIZONTAL_SYNC_WIDTH 23:16 +#define PANEL_HORIZONTAL_SYNC_START 11:0 + +#define PANEL_VERTICAL_TOTAL 0x08002C +#define PANEL_VERTICAL_TOTAL_TOTAL 26:16 +#define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0 + +#define PANEL_VERTICAL_SYNC 0x080030 +#define PANEL_VERTICAL_SYNC_HEIGHT 21:16 +#define PANEL_VERTICAL_SYNC_START 10:0 + +#define PANEL_CURRENT_LINE 0x080034 +#define PANEL_CURRENT_LINE_LINE 10:0 + +/* CRT Graphics Control */ + +#define CRT_DISPLAY_CTRL 0x080200 +#define CRT_DISPLAY_CTRL_FIFO 17:16 +#define CRT_DISPLAY_CTRL_FIFO_1 0 +#define CRT_DISPLAY_CTRL_FIFO_3 1 +#define CRT_DISPLAY_CTRL_FIFO_7 2 +#define CRT_DISPLAY_CTRL_FIFO_11 3 +#define CRT_DISPLAY_CTRL_TV_PHASE 15:15 +#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_HIGH 0 +#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_LOW 1 +#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14 +#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 +#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 +#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13 +#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 +#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 +#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12 +#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 +#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 +#define CRT_DISPLAY_CTRL_BLANK 10:10 +#define CRT_DISPLAY_CTRL_BLANK_OFF 0 +#define CRT_DISPLAY_CTRL_BLANK_ON 1 +#define CRT_DISPLAY_CTRL_SELECT 9:9 +#define CRT_DISPLAY_CTRL_SELECT_PANEL 0 +#define CRT_DISPLAY_CTRL_SELECT_CRT 1 +#define CRT_DISPLAY_CTRL_TIMING 8:8 +#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0 +#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1 +#define CRT_DISPLAY_CTRL_PIXEL 7:4 +#define CRT_DISPLAY_CTRL_GAMMA 3:3 +#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0 +#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1 +#define CRT_DISPLAY_CTRL_PLANE 2:2 +#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0 +#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1 +#define CRT_DISPLAY_CTRL_FORMAT 1:0 +#define CRT_DISPLAY_CTRL_FORMAT_8 0 +#define CRT_DISPLAY_CTRL_FORMAT_16 1 +#define CRT_DISPLAY_CTRL_FORMAT_32 2 + +#define CRT_FB_ADDRESS 0x080204 +#define CRT_FB_ADDRESS_STATUS 31:31 +#define CRT_FB_ADDRESS_STATUS_CURRENT 0 +#define CRT_FB_ADDRESS_STATUS_PENDING 1 +#define CRT_FB_ADDRESS_EXT 27:27 +#define CRT_FB_ADDRESS_EXT_LOCAL 0 +#define CRT_FB_ADDRESS_EXT_EXTERNAL 1 +#define CRT_FB_ADDRESS_CS 26:26 +#define CRT_FB_ADDRESS_CS_0 0 +#define CRT_FB_ADDRESS_CS_1 1 +#define CRT_FB_ADDRESS_ADDRESS 25:0 + +#define CRT_FB_WIDTH 0x080208 +#define CRT_FB_WIDTH_WIDTH 29:16 +#define CRT_FB_WIDTH_OFFSET 13:0 + +#define CRT_HORIZONTAL_TOTAL 0x08020C +#define CRT_HORIZONTAL_TOTAL_TOTAL 27:16 +#define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0 + +#define CRT_HORIZONTAL_SYNC 0x080210 +#define CRT_HORIZONTAL_SYNC_WIDTH 23:16 +#define CRT_HORIZONTAL_SYNC_START 11:0 + +#define CRT_VERTICAL_TOTAL 0x080214 +#define CRT_VERTICAL_TOTAL_TOTAL 26:16 +#define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0 + +#define CRT_VERTICAL_SYNC 0x080218 +#define CRT_VERTICAL_SYNC_HEIGHT 21:16 +#define CRT_VERTICAL_SYNC_START 10:0 + +#define CRT_SIGNATURE_ANALYZER 0x08021C +#define CRT_SIGNATURE_ANALYZER_STATUS 31:16 +#define CRT_SIGNATURE_ANALYZER_ENABLE 3:3 +#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0 +#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1 +#define CRT_SIGNATURE_ANALYZER_RESET 2:2 +#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0 +#define CRT_SIGNATURE_ANALYZER_RESET_RESET 1 +#define CRT_SIGNATURE_ANALYZER_SOURCE 1:0 +#define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 +#define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 +#define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 + +#define CRT_CURRENT_LINE 0x080220 +#define CRT_CURRENT_LINE_LINE 10:0 + +#define CRT_MONITOR_DETECT 0x080224 +#define CRT_MONITOR_DETECT_ENABLE 24:24 +#define CRT_MONITOR_DETECT_ENABLE_DISABLE 0 +#define CRT_MONITOR_DETECT_ENABLE_ENABLE 1 +#define CRT_MONITOR_DETECT_RED 23:16 +#define CRT_MONITOR_DETECT_GREEN 15:8 +#define CRT_MONITOR_DETECT_BLUE 7:0 + +/* CRT Cursor Control */ +#define CRT_HWC_ADDRESS 0x080230 +#define CRT_HWC_ADDRESS_ENABLE 31:31 +#define CRT_HWC_ADDRESS_ENABLE_DISABLE 0 +#define CRT_HWC_ADDRESS_ENABLE_ENABLE 1 +#define CRT_HWC_ADDRESS_EXT 27:27 +#define CRT_HWC_ADDRESS_EXT_LOCAL 0 +#define CRT_HWC_ADDRESS_EXT_EXTERNAL 1 +#define CRT_HWC_ADDRESS_CS 26:26 +#define CRT_HWC_ADDRESS_CS_0 0 +#define CRT_HWC_ADDRESS_CS_1 1 +#define CRT_HWC_ADDRESS_ADDRESS 25:0 + +#define CRT_HWC_LOCATION 0x080234 +#define CRT_HWC_LOCATION_TOP 27:27 +#define CRT_HWC_LOCATION_TOP_INSIDE 0 +#define CRT_HWC_LOCATION_TOP_OUTSIDE 1 +#define CRT_HWC_LOCATION_Y 26:16 +#define CRT_HWC_LOCATION_LEFT 11:11 +#define CRT_HWC_LOCATION_LEFT_INSIDE 0 +#define CRT_HWC_LOCATION_LEFT_OUTSIDE 1 +#define CRT_HWC_LOCATION_X 10:0 + +#define CRT_HWC_COLOR_12 0x080238 +#define CRT_HWC_COLOR_12_2_RGB565 31:16 +#define CRT_HWC_COLOR_12_1_RGB565 15:0 + +#define CRT_HWC_COLOR_3 0x08023C +#define CRT_HWC_COLOR_3_RGB565 15:0 + +#define CRT_HWC_COLOR_01 0x080238 +#define CRT_HWC_COLOR_01_1_RED 31:27 +#define CRT_HWC_COLOR_01_1_GREEN 26:21 +#define CRT_HWC_COLOR_01_1_BLUE 20:16 +#define CRT_HWC_COLOR_01_0_RED 15:11 +#define CRT_HWC_COLOR_01_0_GREEN 10:5 +#define CRT_HWC_COLOR_01_0_BLUE 4:0 + +#define CRT_HWC_COLOR_2 0x08023C +#define CRT_HWC_COLOR_2_RED 15:11 +#define CRT_HWC_COLOR_2_GREEN 10:5 +#define CRT_HWC_COLOR_2_BLUE 4:0 + +#define CRT_PALETTE_RAM 0x080400 +#define PANEL_PALETTE_RAM 0x080800 +#define VIDEO_PALETTE_RAM 0x080C00 + +#endif /*_SMI_H*/ |